1 //===--- LiveRangeEdit.cpp - Basic tools for editing a register live range --===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // The LiveRangeEdit class represents changes done to a virtual register when it 11 // is spilled or split. 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "regalloc" 15 #include "LiveRangeEdit.h" 16 #include "VirtRegMap.h" 17 #include "llvm/ADT/SetVector.h" 18 #include "llvm/CodeGen/CalcSpillWeights.h" 19 #include "llvm/CodeGen/LiveIntervalAnalysis.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/Target/TargetInstrInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/raw_ostream.h" 24 25 using namespace llvm; 26 27 LiveInterval &LiveRangeEdit::createFrom(unsigned OldReg, 28 LiveIntervals &LIS, 29 VirtRegMap &VRM) { 30 MachineRegisterInfo &MRI = VRM.getRegInfo(); 31 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); 32 VRM.grow(); 33 VRM.setIsSplitFromReg(VReg, VRM.getOriginal(OldReg)); 34 LiveInterval &LI = LIS.getOrCreateInterval(VReg); 35 newRegs_.push_back(&LI); 36 return LI; 37 } 38 39 bool LiveRangeEdit::checkRematerializable(VNInfo *VNI, 40 const MachineInstr *DefMI, 41 const TargetInstrInfo &tii, 42 AliasAnalysis *aa) { 43 assert(DefMI && "Missing instruction"); 44 scannedRemattable_ = true; 45 if (!tii.isTriviallyReMaterializable(DefMI, aa)) 46 return false; 47 remattable_.insert(VNI); 48 return true; 49 } 50 51 void LiveRangeEdit::scanRemattable(LiveIntervals &lis, 52 const TargetInstrInfo &tii, 53 AliasAnalysis *aa) { 54 for (LiveInterval::vni_iterator I = parent_.vni_begin(), 55 E = parent_.vni_end(); I != E; ++I) { 56 VNInfo *VNI = *I; 57 if (VNI->isUnused()) 58 continue; 59 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def); 60 if (!DefMI) 61 continue; 62 checkRematerializable(VNI, DefMI, tii, aa); 63 } 64 scannedRemattable_ = true; 65 } 66 67 bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis, 68 const TargetInstrInfo &tii, 69 AliasAnalysis *aa) { 70 if (!scannedRemattable_) 71 scanRemattable(lis, tii, aa); 72 return !remattable_.empty(); 73 } 74 75 /// allUsesAvailableAt - Return true if all registers used by OrigMI at 76 /// OrigIdx are also available with the same value at UseIdx. 77 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI, 78 SlotIndex OrigIdx, 79 SlotIndex UseIdx, 80 LiveIntervals &lis) { 81 OrigIdx = OrigIdx.getUseIndex(); 82 UseIdx = UseIdx.getUseIndex(); 83 for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) { 84 const MachineOperand &MO = OrigMI->getOperand(i); 85 if (!MO.isReg() || !MO.getReg() || MO.isDef()) 86 continue; 87 // Reserved registers are OK. 88 if (MO.isUndef() || !lis.hasInterval(MO.getReg())) 89 continue; 90 // We cannot depend on virtual registers in uselessRegs_. 91 if (uselessRegs_) 92 for (unsigned ui = 0, ue = uselessRegs_->size(); ui != ue; ++ui) 93 if ((*uselessRegs_)[ui]->reg == MO.getReg()) 94 return false; 95 96 LiveInterval &li = lis.getInterval(MO.getReg()); 97 const VNInfo *OVNI = li.getVNInfoAt(OrigIdx); 98 if (!OVNI) 99 continue; 100 if (OVNI != li.getVNInfoAt(UseIdx)) 101 return false; 102 } 103 return true; 104 } 105 106 bool LiveRangeEdit::canRematerializeAt(Remat &RM, 107 SlotIndex UseIdx, 108 bool cheapAsAMove, 109 LiveIntervals &lis) { 110 assert(scannedRemattable_ && "Call anyRematerializable first"); 111 112 // Use scanRemattable info. 113 if (!remattable_.count(RM.ParentVNI)) 114 return false; 115 116 // No defining instruction provided. 117 SlotIndex DefIdx; 118 if (RM.OrigMI) 119 DefIdx = lis.getInstructionIndex(RM.OrigMI); 120 else { 121 DefIdx = RM.ParentVNI->def; 122 RM.OrigMI = lis.getInstructionFromIndex(DefIdx); 123 assert(RM.OrigMI && "No defining instruction for remattable value"); 124 } 125 126 // If only cheap remats were requested, bail out early. 127 if (cheapAsAMove && !RM.OrigMI->getDesc().isAsCheapAsAMove()) 128 return false; 129 130 // Verify that all used registers are available with the same values. 131 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis)) 132 return false; 133 134 return true; 135 } 136 137 SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB, 138 MachineBasicBlock::iterator MI, 139 unsigned DestReg, 140 const Remat &RM, 141 LiveIntervals &lis, 142 const TargetInstrInfo &tii, 143 const TargetRegisterInfo &tri, 144 bool Late) { 145 assert(RM.OrigMI && "Invalid remat"); 146 tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri); 147 rematted_.insert(RM.ParentVNI); 148 return lis.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late) 149 .getDefIndex(); 150 } 151 152 void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) { 153 if (delegate_ && delegate_->LRE_CanEraseVirtReg(Reg)) 154 LIS.removeInterval(Reg); 155 } 156 157 bool LiveRangeEdit::foldAsLoad(LiveInterval *LI, 158 SmallVectorImpl<MachineInstr*> &Dead, 159 MachineRegisterInfo &MRI, 160 LiveIntervals &LIS, 161 const TargetInstrInfo &TII) { 162 MachineInstr *DefMI = 0, *UseMI = 0; 163 164 // Check that there is a single def and a single use. 165 for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg), 166 E = MRI.reg_nodbg_end(); I != E; ++I) { 167 MachineOperand &MO = I.getOperand(); 168 MachineInstr *MI = MO.getParent(); 169 if (MO.isDef()) { 170 if (DefMI && DefMI != MI) 171 return false; 172 if (!MI->getDesc().canFoldAsLoad()) 173 return false; 174 DefMI = MI; 175 } else if (!MO.isUndef()) { 176 if (UseMI && UseMI != MI) 177 return false; 178 // FIXME: Targets don't know how to fold subreg uses. 179 if (MO.getSubReg()) 180 return false; 181 UseMI = MI; 182 } 183 } 184 if (!DefMI || !UseMI) 185 return false; 186 187 DEBUG(dbgs() << "Try to fold single def: " << *DefMI 188 << " into single use: " << *UseMI); 189 190 SmallVector<unsigned, 8> Ops; 191 if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second) 192 return false; 193 194 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI); 195 if (!FoldMI) 196 return false; 197 DEBUG(dbgs() << " folded: " << *FoldMI); 198 LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI); 199 UseMI->eraseFromParent(); 200 DefMI->addRegisterDead(LI->reg, 0); 201 Dead.push_back(DefMI); 202 return true; 203 } 204 205 void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead, 206 LiveIntervals &LIS, VirtRegMap &VRM, 207 const TargetInstrInfo &TII) { 208 SetVector<LiveInterval*, 209 SmallVector<LiveInterval*, 8>, 210 SmallPtrSet<LiveInterval*, 8> > ToShrink; 211 MachineRegisterInfo &MRI = VRM.getRegInfo(); 212 213 for (;;) { 214 // Erase all dead defs. 215 while (!Dead.empty()) { 216 MachineInstr *MI = Dead.pop_back_val(); 217 assert(MI->allDefsAreDead() && "Def isn't really dead"); 218 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex(); 219 220 // Never delete inline asm. 221 if (MI->isInlineAsm()) { 222 DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI); 223 continue; 224 } 225 226 // Use the same criteria as DeadMachineInstructionElim. 227 bool SawStore = false; 228 if (!MI->isSafeToMove(&TII, 0, SawStore)) { 229 DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI); 230 continue; 231 } 232 233 DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI); 234 235 // Check for live intervals that may shrink 236 for (MachineInstr::mop_iterator MOI = MI->operands_begin(), 237 MOE = MI->operands_end(); MOI != MOE; ++MOI) { 238 if (!MOI->isReg()) 239 continue; 240 unsigned Reg = MOI->getReg(); 241 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 242 continue; 243 LiveInterval &LI = LIS.getInterval(Reg); 244 245 // Shrink read registers, unless it is likely to be expensive and 246 // unlikely to change anything. We typically don't want to shrink the 247 // PIC base register that has lots of uses everywhere. 248 // Always shrink COPY uses that probably come from live range splitting. 249 if (MI->readsVirtualRegister(Reg) && 250 (MI->isCopy() || MOI->isDef() || MRI.hasOneNonDBGUse(Reg) || 251 LI.killedAt(Idx))) 252 ToShrink.insert(&LI); 253 254 // Remove defined value. 255 if (MOI->isDef()) { 256 if (VNInfo *VNI = LI.getVNInfoAt(Idx)) { 257 if (delegate_) 258 delegate_->LRE_WillShrinkVirtReg(LI.reg); 259 LI.removeValNo(VNI); 260 if (LI.empty()) { 261 ToShrink.remove(&LI); 262 eraseVirtReg(Reg, LIS); 263 } 264 } 265 } 266 } 267 268 if (delegate_) 269 delegate_->LRE_WillEraseInstruction(MI); 270 LIS.RemoveMachineInstrFromMaps(MI); 271 MI->eraseFromParent(); 272 } 273 274 if (ToShrink.empty()) 275 break; 276 277 // Shrink just one live interval. Then delete new dead defs. 278 LiveInterval *LI = ToShrink.back(); 279 ToShrink.pop_back(); 280 if (foldAsLoad(LI, Dead, MRI, LIS, TII)) 281 continue; 282 if (delegate_) 283 delegate_->LRE_WillShrinkVirtReg(LI->reg); 284 if (!LIS.shrinkToUses(LI, &Dead)) 285 continue; 286 287 // LI may have been separated, create new intervals. 288 LI->RenumberValues(LIS); 289 ConnectedVNInfoEqClasses ConEQ(LIS); 290 unsigned NumComp = ConEQ.Classify(LI); 291 if (NumComp <= 1) 292 continue; 293 DEBUG(dbgs() << NumComp << " components: " << *LI << '\n'); 294 SmallVector<LiveInterval*, 8> Dups(1, LI); 295 for (unsigned i = 1; i != NumComp; ++i) { 296 Dups.push_back(&createFrom(LI->reg, LIS, VRM)); 297 if (delegate_) 298 delegate_->LRE_DidCloneVirtReg(Dups.back()->reg, LI->reg); 299 } 300 ConEQ.Distribute(&Dups[0], MRI); 301 } 302 } 303 304 void LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF, 305 LiveIntervals &LIS, 306 const MachineLoopInfo &Loops) { 307 VirtRegAuxInfo VRAI(MF, LIS, Loops); 308 for (iterator I = begin(), E = end(); I != E; ++I) { 309 LiveInterval &LI = **I; 310 VRAI.CalculateRegClass(LI.reg); 311 VRAI.CalculateWeightAndHint(LI); 312 } 313 } 314