1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 5 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 8 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 9 10 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 12 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 15 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 18 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 19 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 22 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 23 24 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 25 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 26 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 27 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 28 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 29 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 30 31 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 33 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 35 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 36 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 37 38 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 39 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 40 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 41 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 42 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 43 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 44 // expected-no-diagnostics 45 #ifndef HEADER 46 #define HEADER 47 #ifndef ARRAY 48 struct St { 49 int a, b; 50 St() : a(0), b(0) {} 51 St(const St &st) : a(st.a + st.b), b(0) {} 52 ~St() {} 53 }; 54 55 volatile int g __attribute__((aligned(128))) = 1212; 56 57 template <class T> 58 struct S { 59 T f; 60 S(T a) : f(a + g) {} 61 S() : f(g) {} 62 S(const S &s, St t = St()) : f(s.f + t.a) {} 63 operator T() { return T(); } 64 ~S() {} 65 }; 66 67 68 template <typename T> 69 T tmain() { 70 S<T> test; 71 T t_var __attribute__((aligned(128))) = T(); 72 T vec[] __attribute__((aligned(128))) = {1, 2}; 73 S<T> s_arr[] __attribute__((aligned(128))) = {1, 2}; 74 S<T> var __attribute__((aligned(128))) (3); 75 #pragma omp target 76 #pragma omp teams firstprivate(t_var, vec, s_arr, var) 77 { 78 vec[0] = t_var; 79 s_arr[0] = var; 80 } 81 #pragma omp target 82 #pragma omp teams firstprivate(t_var) 83 {} 84 return T(); 85 } 86 87 int main() { 88 static int sivar; 89 #ifdef LAMBDA 90 [&]() { 91 #pragma omp target 92 #pragma omp teams firstprivate(g, sivar) 93 { 94 g = 1; 95 sivar = 2; 96 [&]() { 97 g = 2; 98 sivar = 4; 99 }(); 100 } 101 }(); 102 return 0; 103 #else 104 S<float> test; 105 int t_var = 0; 106 int vec[] = {1, 2}; 107 S<float> s_arr[] = {1, 2}; 108 S<float> var(3); 109 #pragma omp target 110 #pragma omp teams firstprivate(t_var, vec, s_arr, var, sivar) 111 { 112 vec[0] = t_var; 113 s_arr[0] = var; 114 sivar = 2; 115 } 116 #pragma omp target 117 #pragma omp teams firstprivate(t_var) 118 {} 119 return tmain<int>(); 120 #endif 121 } 122 123 124 125 126 127 128 129 130 131 132 133 134 135 #else 136 struct St { 137 int a, b; 138 St() : a(0), b(0) {} 139 St(const St &) { } 140 ~St() {} 141 void St_func(St s[2], int n, long double vla1[n]) { 142 double vla2[n][n] __attribute__((aligned(128))); 143 a = b; 144 #pragma omp target 145 #pragma omp teams firstprivate(s, vla1, vla2) 146 vla1[b] = vla2[1][n - 1] = a = b; 147 } 148 }; 149 150 void array_func(float a[3], St s[2], int n, long double vla1[n]) { 151 double vla2[n][n] __attribute__((aligned(128))); 152 #pragma omp target 153 #pragma omp teams firstprivate(a, s, vla1, vla2) 154 s[0].St_func(s, n, vla1); 155 ; 156 } 157 158 #endif 159 #endif 160 // CHECK1-LABEL: define {{[^@]+}}@main 161 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 162 // CHECK1-NEXT: entry: 163 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 164 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 165 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 166 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 1 dereferenceable(1) [[REF_TMP]]) 167 // CHECK1-NEXT: ret i32 0 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 171 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8 174 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 175 // CHECK1-NEXT: [[G1:%.*]] = alloca i32, align 128 176 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 177 // CHECK1-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8 178 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 179 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 180 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128 181 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[G1]], align 128 182 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 183 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 184 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 185 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.omp_outlined., ptr [[G1]], i64 [[TMP3]]) 186 // CHECK1-NEXT: ret void 187 // 188 // 189 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 190 // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2]] { 191 // CHECK1-NEXT: entry: 192 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 193 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 194 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 8 195 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 196 // CHECK1-NEXT: [[G1:%.*]] = alloca i32, align 128 197 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 198 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 199 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 200 // CHECK1-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8 201 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 202 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 203 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128 204 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[G1]], align 128 205 // CHECK1-NEXT: store i32 1, ptr [[G1]], align 128 206 // CHECK1-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 207 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 208 // CHECK1-NEXT: store ptr [[G1]], ptr [[TMP2]], align 8 209 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 210 // CHECK1-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP3]], align 8 211 // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr nonnull align 8 dereferenceable(16) [[REF_TMP]]) 212 // CHECK1-NEXT: ret void 213 // 214 // 215 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 216 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 217 // CHECK1-NEXT: entry: 218 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 219 // CHECK1-NEXT: ret void 220 // 221 // 222 // CHECK3-LABEL: define {{[^@]+}}@main 223 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 224 // CHECK3-NEXT: entry: 225 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 226 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 227 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 228 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 1 dereferenceable(1) [[REF_TMP]]) 229 // CHECK3-NEXT: ret i32 0 230 // 231 // 232 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 233 // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 234 // CHECK3-NEXT: entry: 235 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 236 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 237 // CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128 238 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 239 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 240 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 241 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 242 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128 243 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[G1]], align 128 244 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 245 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 246 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 247 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @.omp_outlined., ptr [[G1]], i32 [[TMP3]]) 248 // CHECK3-NEXT: ret void 249 // 250 // 251 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 252 // CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2]] { 253 // CHECK3-NEXT: entry: 254 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 255 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 256 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4 257 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 258 // CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128 259 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 260 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 261 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 262 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 263 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 264 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 265 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128 266 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[G1]], align 128 267 // CHECK3-NEXT: store i32 1, ptr [[G1]], align 128 268 // CHECK3-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 269 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 270 // CHECK3-NEXT: store ptr [[G1]], ptr [[TMP2]], align 4 271 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 272 // CHECK3-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP3]], align 4 273 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr nonnull align 4 dereferenceable(8) [[REF_TMP]]) 274 // CHECK3-NEXT: ret void 275 // 276 // 277 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 278 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 279 // CHECK3-NEXT: entry: 280 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 281 // CHECK3-NEXT: ret void 282 // 283 // 284 // CHECK9-LABEL: define {{[^@]+}}@main 285 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 286 // CHECK9-NEXT: entry: 287 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 288 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 289 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 290 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 291 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 292 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 293 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 294 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 295 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 296 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 297 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 298 // CHECK9-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i64, align 8 299 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x ptr], align 8 300 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x ptr], align 8 301 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x ptr], align 8 302 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 303 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) 304 // CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4 305 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) 306 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 307 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 308 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1 309 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 310 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 311 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 312 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 313 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 314 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 315 // CHECK9-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 316 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 317 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 318 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[TMP4]], align 8 319 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 320 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 321 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 322 // CHECK9-NEXT: store ptr null, ptr [[TMP6]], align 8 323 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 324 // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP7]], align 8 325 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 326 // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP8]], align 8 327 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 328 // CHECK9-NEXT: store ptr null, ptr [[TMP9]], align 8 329 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 330 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 8 331 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 332 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 8 333 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 334 // CHECK9-NEXT: store ptr null, ptr [[TMP12]], align 8 335 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 336 // CHECK9-NEXT: store ptr [[VAR]], ptr [[TMP13]], align 8 337 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 338 // CHECK9-NEXT: store ptr [[VAR]], ptr [[TMP14]], align 8 339 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 340 // CHECK9-NEXT: store ptr null, ptr [[TMP15]], align 8 341 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 342 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[TMP16]], align 8 343 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 344 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[TMP17]], align 8 345 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 346 // CHECK9-NEXT: store ptr null, ptr [[TMP18]], align 8 347 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 348 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 349 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 350 // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 351 // CHECK9-NEXT: store i32 1, ptr [[TMP21]], align 4 352 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 353 // CHECK9-NEXT: store i32 5, ptr [[TMP22]], align 4 354 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 355 // CHECK9-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 356 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 357 // CHECK9-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 358 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 359 // CHECK9-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 8 360 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 361 // CHECK9-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8 362 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 363 // CHECK9-NEXT: store ptr null, ptr [[TMP27]], align 8 364 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 365 // CHECK9-NEXT: store ptr null, ptr [[TMP28]], align 8 366 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 367 // CHECK9-NEXT: store i64 0, ptr [[TMP29]], align 8 368 // CHECK9-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, ptr [[KERNEL_ARGS]]) 369 // CHECK9-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 370 // CHECK9-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 371 // CHECK9: omp_offload.failed: 372 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i64 [[TMP1]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]], i64 [[TMP3]]) #[[ATTR4:[0-9]+]] 373 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 374 // CHECK9: omp_offload.cont: 375 // CHECK9-NEXT: [[TMP32:%.*]] = load i32, ptr [[T_VAR]], align 4 376 // CHECK9-NEXT: store i32 [[TMP32]], ptr [[T_VAR_CASTED1]], align 4 377 // CHECK9-NEXT: [[TMP33:%.*]] = load i64, ptr [[T_VAR_CASTED1]], align 8 378 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 379 // CHECK9-NEXT: store i64 [[TMP33]], ptr [[TMP34]], align 8 380 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 381 // CHECK9-NEXT: store i64 [[TMP33]], ptr [[TMP35]], align 8 382 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 0 383 // CHECK9-NEXT: store ptr null, ptr [[TMP36]], align 8 384 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 385 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 386 // CHECK9-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 387 // CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0 388 // CHECK9-NEXT: store i32 1, ptr [[TMP39]], align 4 389 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1 390 // CHECK9-NEXT: store i32 1, ptr [[TMP40]], align 4 391 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2 392 // CHECK9-NEXT: store ptr [[TMP37]], ptr [[TMP41]], align 8 393 // CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3 394 // CHECK9-NEXT: store ptr [[TMP38]], ptr [[TMP42]], align 8 395 // CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4 396 // CHECK9-NEXT: store ptr @.offload_sizes.2, ptr [[TMP43]], align 8 397 // CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5 398 // CHECK9-NEXT: store ptr @.offload_maptypes.3, ptr [[TMP44]], align 8 399 // CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6 400 // CHECK9-NEXT: store ptr null, ptr [[TMP45]], align 8 401 // CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7 402 // CHECK9-NEXT: store ptr null, ptr [[TMP46]], align 8 403 // CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8 404 // CHECK9-NEXT: store i64 0, ptr [[TMP47]], align 8 405 // CHECK9-NEXT: [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, ptr [[KERNEL_ARGS5]]) 406 // CHECK9-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0 407 // CHECK9-NEXT: br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 408 // CHECK9: omp_offload.failed6: 409 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP33]]) #[[ATTR4]] 410 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT7]] 411 // CHECK9: omp_offload.cont7: 412 // CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 413 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 414 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 415 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 416 // CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 417 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 418 // CHECK9: arraydestroy.body: 419 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP50]], [[OMP_OFFLOAD_CONT7]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 420 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 421 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 422 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 423 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 424 // CHECK9: arraydestroy.done8: 425 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 426 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[RETVAL]], align 4 427 // CHECK9-NEXT: ret i32 [[TMP51]] 428 // 429 // 430 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 431 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 432 // CHECK9-NEXT: entry: 433 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 434 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 435 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 436 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) 437 // CHECK9-NEXT: ret void 438 // 439 // 440 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 441 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 442 // CHECK9-NEXT: entry: 443 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 444 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 445 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 446 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 447 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 448 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 449 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 450 // CHECK9-NEXT: ret void 451 // 452 // 453 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 454 // CHECK9-SAME: (i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 455 // CHECK9-NEXT: entry: 456 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 457 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 458 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 459 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 460 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 461 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 462 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 463 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 464 // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 465 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 466 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 467 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 468 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 469 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 470 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 471 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 472 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 473 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 474 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 475 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 476 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 477 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @.omp_outlined., ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]]) 478 // CHECK9-NEXT: ret void 479 // 480 // 481 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 482 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { 483 // CHECK9-NEXT: entry: 484 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 485 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 486 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 487 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 488 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 489 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 490 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 491 // CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 492 // CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 493 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 494 // CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 495 // CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 496 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 497 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 498 // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 499 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 500 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 501 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 502 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 503 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 504 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 505 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 506 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) 507 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 508 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 509 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 510 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 511 // CHECK9: omp.arraycpy.body: 512 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 513 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 514 // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 515 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) 516 // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 517 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 518 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 519 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 520 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 521 // CHECK9: omp.arraycpy.done3: 522 // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 523 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) 524 // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] 525 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 526 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 527 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 528 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 0 529 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i64 4, i1 false) 530 // CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 531 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] 532 // CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 533 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 534 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 535 // CHECK9: arraydestroy.body: 536 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 537 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 538 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 539 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 540 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 541 // CHECK9: arraydestroy.done8: 542 // CHECK9-NEXT: ret void 543 // 544 // 545 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev 546 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 547 // CHECK9-NEXT: entry: 548 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 549 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 550 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 551 // CHECK9-NEXT: call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) 552 // CHECK9-NEXT: ret void 553 // 554 // 555 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 556 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 557 // CHECK9-NEXT: entry: 558 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 559 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 560 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 561 // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 562 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 563 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 564 // CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) 565 // CHECK9-NEXT: ret void 566 // 567 // 568 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev 569 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 570 // CHECK9-NEXT: entry: 571 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 572 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 573 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 574 // CHECK9-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 575 // CHECK9-NEXT: ret void 576 // 577 // 578 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 579 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 580 // CHECK9-NEXT: entry: 581 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 582 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 583 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 584 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 585 // CHECK9-NEXT: ret void 586 // 587 // 588 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 589 // CHECK9-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { 590 // CHECK9-NEXT: entry: 591 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 592 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 593 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 594 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 595 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 596 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 597 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..1, i64 [[TMP1]]) 598 // CHECK9-NEXT: ret void 599 // 600 // 601 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 602 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { 603 // CHECK9-NEXT: entry: 604 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 605 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 606 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 607 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 608 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 609 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 610 // CHECK9-NEXT: ret void 611 // 612 // 613 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 614 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { 615 // CHECK9-NEXT: entry: 616 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 617 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 618 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 619 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 620 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 621 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 622 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 623 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 624 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 625 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 8 626 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 8 627 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 8 628 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) 629 // CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 128 630 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 631 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 632 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 633 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 634 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 635 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) 636 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 637 // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[TMP0]], align 8 638 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 639 // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[TMP1]], align 8 640 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 641 // CHECK9-NEXT: store ptr null, ptr [[TMP2]], align 8 642 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 643 // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP3]], align 8 644 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 645 // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 8 646 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 647 // CHECK9-NEXT: store ptr null, ptr [[TMP5]], align 8 648 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 649 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP6]], align 8 650 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 651 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP7]], align 8 652 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 653 // CHECK9-NEXT: store ptr null, ptr [[TMP8]], align 8 654 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 655 // CHECK9-NEXT: store ptr [[VAR]], ptr [[TMP9]], align 8 656 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 657 // CHECK9-NEXT: store ptr [[VAR]], ptr [[TMP10]], align 8 658 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 659 // CHECK9-NEXT: store ptr null, ptr [[TMP11]], align 8 660 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 661 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 662 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 663 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 664 // CHECK9-NEXT: store i32 1, ptr [[TMP14]], align 4 665 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 666 // CHECK9-NEXT: store i32 4, ptr [[TMP15]], align 4 667 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 668 // CHECK9-NEXT: store ptr [[TMP12]], ptr [[TMP16]], align 8 669 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 670 // CHECK9-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 8 671 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 672 // CHECK9-NEXT: store ptr @.offload_sizes.5, ptr [[TMP18]], align 8 673 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 674 // CHECK9-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP19]], align 8 675 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 676 // CHECK9-NEXT: store ptr null, ptr [[TMP20]], align 8 677 // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 678 // CHECK9-NEXT: store ptr null, ptr [[TMP21]], align 8 679 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 680 // CHECK9-NEXT: store i64 0, ptr [[TMP22]], align 8 681 // CHECK9-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, ptr [[KERNEL_ARGS]]) 682 // CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 683 // CHECK9-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 684 // CHECK9: omp_offload.failed: 685 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) #[[ATTR4]] 686 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 687 // CHECK9: omp_offload.cont: 688 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 689 // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[TMP25]], align 8 690 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 691 // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[TMP26]], align 8 692 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 693 // CHECK9-NEXT: store ptr null, ptr [[TMP27]], align 8 694 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 695 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 696 // CHECK9-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 697 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0 698 // CHECK9-NEXT: store i32 1, ptr [[TMP30]], align 4 699 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1 700 // CHECK9-NEXT: store i32 1, ptr [[TMP31]], align 4 701 // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2 702 // CHECK9-NEXT: store ptr [[TMP28]], ptr [[TMP32]], align 8 703 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3 704 // CHECK9-NEXT: store ptr [[TMP29]], ptr [[TMP33]], align 8 705 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4 706 // CHECK9-NEXT: store ptr @.offload_sizes.8, ptr [[TMP34]], align 8 707 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5 708 // CHECK9-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP35]], align 8 709 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6 710 // CHECK9-NEXT: store ptr null, ptr [[TMP36]], align 8 711 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7 712 // CHECK9-NEXT: store ptr null, ptr [[TMP37]], align 8 713 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8 714 // CHECK9-NEXT: store i64 0, ptr [[TMP38]], align 8 715 // CHECK9-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, ptr [[KERNEL_ARGS4]]) 716 // CHECK9-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 717 // CHECK9-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] 718 // CHECK9: omp_offload.failed5: 719 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(ptr [[T_VAR]]) #[[ATTR4]] 720 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT6]] 721 // CHECK9: omp_offload.cont6: 722 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 723 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 724 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 725 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 726 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 727 // CHECK9: arraydestroy.body: 728 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP41]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 729 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 730 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 731 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 732 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 733 // CHECK9: arraydestroy.done7: 734 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 735 // CHECK9-NEXT: [[TMP42:%.*]] = load i32, ptr [[RETVAL]], align 4 736 // CHECK9-NEXT: ret i32 [[TMP42]] 737 // 738 // 739 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 740 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 741 // CHECK9-NEXT: entry: 742 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 743 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 744 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 745 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 746 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 747 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 748 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 749 // CHECK9-NEXT: ret void 750 // 751 // 752 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 753 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 754 // CHECK9-NEXT: entry: 755 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 756 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 757 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 758 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 759 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 760 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 761 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 762 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 763 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 764 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 765 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 766 // CHECK9-NEXT: ret void 767 // 768 // 769 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev 770 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 771 // CHECK9-NEXT: entry: 772 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 773 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 774 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 775 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 776 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 777 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 778 // CHECK9-NEXT: store i32 0, ptr [[B]], align 4 779 // CHECK9-NEXT: ret void 780 // 781 // 782 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 783 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 784 // CHECK9-NEXT: entry: 785 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 786 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 787 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 788 // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 789 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 790 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 791 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 792 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 793 // CHECK9-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 794 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 795 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 796 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 797 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 798 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 799 // CHECK9-NEXT: ret void 800 // 801 // 802 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev 803 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 804 // CHECK9-NEXT: entry: 805 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 806 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 807 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 808 // CHECK9-NEXT: ret void 809 // 810 // 811 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 812 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 813 // CHECK9-NEXT: entry: 814 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 815 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 816 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 817 // CHECK9-NEXT: ret void 818 // 819 // 820 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 821 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 822 // CHECK9-NEXT: entry: 823 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 824 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 825 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 826 // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) 827 // CHECK9-NEXT: ret void 828 // 829 // 830 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 831 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 832 // CHECK9-NEXT: entry: 833 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 834 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 835 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 836 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 837 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 838 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 839 // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 840 // CHECK9-NEXT: ret void 841 // 842 // 843 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 844 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 845 // CHECK9-NEXT: entry: 846 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 847 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 848 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 849 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 850 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 851 // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 852 // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 853 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 854 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 855 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 856 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 857 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 858 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 859 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP0]], align 128 860 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 128 861 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @.omp_outlined..4, ptr [[TMP1]], ptr [[T_VAR1]], ptr [[TMP2]], ptr [[TMP3]]) 862 // CHECK9-NEXT: ret void 863 // 864 // 865 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 866 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 867 // CHECK9-NEXT: entry: 868 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 869 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 870 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 871 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 872 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 873 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 874 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 875 // CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 876 // CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 877 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 878 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 879 // CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 880 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 881 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 882 // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 883 // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 884 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 885 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 886 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 887 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 888 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 889 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 890 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 128 891 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 128 892 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC2]], ptr align 128 [[TMP0]], i64 8, i1 false) 893 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 894 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 895 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 896 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 897 // CHECK9: omp.arraycpy.body: 898 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 899 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 900 // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 901 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) 902 // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 903 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 904 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 905 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 906 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 907 // CHECK9: omp.arraycpy.done4: 908 // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 909 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR5]], ptr nonnull align 4 dereferenceable(4) [[TMP3]], ptr [[AGG_TMP6]]) 910 // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 911 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR1]], align 128 912 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 913 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 128 914 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 915 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX7]], ptr align 128 [[VAR5]], i64 4, i1 false) 916 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 917 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 918 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 919 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 920 // CHECK9: arraydestroy.body: 921 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 922 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 923 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 924 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 925 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 926 // CHECK9: arraydestroy.done9: 927 // CHECK9-NEXT: ret void 928 // 929 // 930 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 931 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 932 // CHECK9-NEXT: entry: 933 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 934 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 935 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 936 // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 937 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 938 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 939 // CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) 940 // CHECK9-NEXT: ret void 941 // 942 // 943 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 944 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 945 // CHECK9-NEXT: entry: 946 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 947 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 948 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 949 // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 950 // CHECK9-NEXT: ret void 951 // 952 // 953 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 954 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 955 // CHECK9-NEXT: entry: 956 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 957 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 958 // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 959 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 960 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128 961 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR1]], align 128 962 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..7, ptr [[T_VAR1]]) 963 // CHECK9-NEXT: ret void 964 // 965 // 966 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 967 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 968 // CHECK9-NEXT: entry: 969 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 970 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 971 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 972 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 973 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 974 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 975 // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 976 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 977 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128 978 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR1]], align 128 979 // CHECK9-NEXT: ret void 980 // 981 // 982 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 983 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 984 // CHECK9-NEXT: entry: 985 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 986 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 987 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 988 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 989 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 990 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 991 // CHECK9-NEXT: ret void 992 // 993 // 994 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 995 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 996 // CHECK9-NEXT: entry: 997 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 998 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 999 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1000 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1001 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1002 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1003 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1004 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 1005 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1006 // CHECK9-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1007 // CHECK9-NEXT: ret void 1008 // 1009 // 1010 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1011 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1012 // CHECK9-NEXT: entry: 1013 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1014 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 1015 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1016 // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 1017 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1018 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1019 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 1020 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 1021 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 1022 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1023 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1024 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1025 // CHECK9-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1026 // CHECK9-NEXT: ret void 1027 // 1028 // 1029 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1030 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1031 // CHECK9-NEXT: entry: 1032 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1033 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1034 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1035 // CHECK9-NEXT: ret void 1036 // 1037 // 1038 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1039 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] { 1040 // CHECK9-NEXT: entry: 1041 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1042 // CHECK9-NEXT: ret void 1043 // 1044 // 1045 // CHECK11-LABEL: define {{[^@]+}}@main 1046 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 1047 // CHECK11-NEXT: entry: 1048 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1049 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1050 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1051 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1052 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1053 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 1054 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1055 // CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1056 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 1057 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 1058 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 1059 // CHECK11-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 1060 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x ptr], align 4 1061 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x ptr], align 4 1062 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x ptr], align 4 1063 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 1064 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) 1065 // CHECK11-NEXT: store i32 0, ptr [[T_VAR]], align 4 1066 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false) 1067 // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1068 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 1069 // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i32 1 1070 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 1071 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 1072 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 1073 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1074 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1075 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 1076 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 1077 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1078 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1079 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 4 1080 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1081 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 1082 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1083 // CHECK11-NEXT: store ptr null, ptr [[TMP6]], align 4 1084 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1085 // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP7]], align 4 1086 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1087 // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP8]], align 4 1088 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1089 // CHECK11-NEXT: store ptr null, ptr [[TMP9]], align 4 1090 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1091 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 4 1092 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1093 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 4 1094 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1095 // CHECK11-NEXT: store ptr null, ptr [[TMP12]], align 4 1096 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1097 // CHECK11-NEXT: store ptr [[VAR]], ptr [[TMP13]], align 4 1098 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1099 // CHECK11-NEXT: store ptr [[VAR]], ptr [[TMP14]], align 4 1100 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1101 // CHECK11-NEXT: store ptr null, ptr [[TMP15]], align 4 1102 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1103 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[TMP16]], align 4 1104 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1105 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[TMP17]], align 4 1106 // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1107 // CHECK11-NEXT: store ptr null, ptr [[TMP18]], align 4 1108 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1109 // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1110 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1111 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1112 // CHECK11-NEXT: store i32 1, ptr [[TMP21]], align 4 1113 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1114 // CHECK11-NEXT: store i32 5, ptr [[TMP22]], align 4 1115 // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1116 // CHECK11-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 1117 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1118 // CHECK11-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 1119 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1120 // CHECK11-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 4 1121 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1122 // CHECK11-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 4 1123 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1124 // CHECK11-NEXT: store ptr null, ptr [[TMP27]], align 4 1125 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1126 // CHECK11-NEXT: store ptr null, ptr [[TMP28]], align 4 1127 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1128 // CHECK11-NEXT: store i64 0, ptr [[TMP29]], align 8 1129 // CHECK11-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, ptr [[KERNEL_ARGS]]) 1130 // CHECK11-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 1131 // CHECK11-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1132 // CHECK11: omp_offload.failed: 1133 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i32 [[TMP1]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]], i32 [[TMP3]]) #[[ATTR4:[0-9]+]] 1134 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1135 // CHECK11: omp_offload.cont: 1136 // CHECK11-NEXT: [[TMP32:%.*]] = load i32, ptr [[T_VAR]], align 4 1137 // CHECK11-NEXT: store i32 [[TMP32]], ptr [[T_VAR_CASTED1]], align 4 1138 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, ptr [[T_VAR_CASTED1]], align 4 1139 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1140 // CHECK11-NEXT: store i32 [[TMP33]], ptr [[TMP34]], align 4 1141 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1142 // CHECK11-NEXT: store i32 [[TMP33]], ptr [[TMP35]], align 4 1143 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 1144 // CHECK11-NEXT: store ptr null, ptr [[TMP36]], align 4 1145 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1146 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1147 // CHECK11-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1148 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0 1149 // CHECK11-NEXT: store i32 1, ptr [[TMP39]], align 4 1150 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1 1151 // CHECK11-NEXT: store i32 1, ptr [[TMP40]], align 4 1152 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2 1153 // CHECK11-NEXT: store ptr [[TMP37]], ptr [[TMP41]], align 4 1154 // CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3 1155 // CHECK11-NEXT: store ptr [[TMP38]], ptr [[TMP42]], align 4 1156 // CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4 1157 // CHECK11-NEXT: store ptr @.offload_sizes.2, ptr [[TMP43]], align 4 1158 // CHECK11-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5 1159 // CHECK11-NEXT: store ptr @.offload_maptypes.3, ptr [[TMP44]], align 4 1160 // CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6 1161 // CHECK11-NEXT: store ptr null, ptr [[TMP45]], align 4 1162 // CHECK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7 1163 // CHECK11-NEXT: store ptr null, ptr [[TMP46]], align 4 1164 // CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8 1165 // CHECK11-NEXT: store i64 0, ptr [[TMP47]], align 8 1166 // CHECK11-NEXT: [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, ptr [[KERNEL_ARGS5]]) 1167 // CHECK11-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0 1168 // CHECK11-NEXT: br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 1169 // CHECK11: omp_offload.failed6: 1170 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP33]]) #[[ATTR4]] 1171 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT7]] 1172 // CHECK11: omp_offload.cont7: 1173 // CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1174 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 1175 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1176 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1177 // CHECK11-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1178 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1179 // CHECK11: arraydestroy.body: 1180 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP50]], [[OMP_OFFLOAD_CONT7]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1181 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1182 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1183 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1184 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1185 // CHECK11: arraydestroy.done8: 1186 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1187 // CHECK11-NEXT: [[TMP51:%.*]] = load i32, ptr [[RETVAL]], align 4 1188 // CHECK11-NEXT: ret i32 [[TMP51]] 1189 // 1190 // 1191 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1192 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1193 // CHECK11-NEXT: entry: 1194 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1195 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1196 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1197 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) 1198 // CHECK11-NEXT: ret void 1199 // 1200 // 1201 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1202 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1203 // CHECK11-NEXT: entry: 1204 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1205 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1206 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1207 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1208 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1209 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1210 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1211 // CHECK11-NEXT: ret void 1212 // 1213 // 1214 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 1215 // CHECK11-SAME: (i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 1216 // CHECK11-NEXT: entry: 1217 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1218 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1219 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1220 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1221 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1222 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1223 // CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1224 // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1225 // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1226 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1227 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1228 // CHECK11-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1229 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1230 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1231 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1232 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1233 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1234 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1235 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1236 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 1237 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1238 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @.omp_outlined., ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]]) 1239 // CHECK11-NEXT: ret void 1240 // 1241 // 1242 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 1243 // CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] { 1244 // CHECK11-NEXT: entry: 1245 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1246 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1247 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1248 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1249 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1250 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1251 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1252 // CHECK11-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1253 // CHECK11-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1254 // CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1255 // CHECK11-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1256 // CHECK11-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1257 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1258 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1259 // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1260 // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1261 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1262 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1263 // CHECK11-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1264 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1265 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1266 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1267 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 1268 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1269 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1270 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1271 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1272 // CHECK11: omp.arraycpy.body: 1273 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1274 // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1275 // CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1276 // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) 1277 // CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 1278 // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1279 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1280 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1281 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1282 // CHECK11: omp.arraycpy.done3: 1283 // CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1284 // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) 1285 // CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] 1286 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1287 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 1288 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 1289 // CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1290 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i32 4, i1 false) 1291 // CHECK11-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 1292 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] 1293 // CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1294 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 1295 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1296 // CHECK11: arraydestroy.body: 1297 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1298 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1299 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1300 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 1301 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1302 // CHECK11: arraydestroy.done8: 1303 // CHECK11-NEXT: ret void 1304 // 1305 // 1306 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1307 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1308 // CHECK11-NEXT: entry: 1309 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1310 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1311 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1312 // CHECK11-NEXT: call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) 1313 // CHECK11-NEXT: ret void 1314 // 1315 // 1316 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1317 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1318 // CHECK11-NEXT: entry: 1319 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1320 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1321 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1322 // CHECK11-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1323 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1324 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1325 // CHECK11-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) 1326 // CHECK11-NEXT: ret void 1327 // 1328 // 1329 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1330 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1331 // CHECK11-NEXT: entry: 1332 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1333 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1334 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1335 // CHECK11-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 1336 // CHECK11-NEXT: ret void 1337 // 1338 // 1339 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1340 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1341 // CHECK11-NEXT: entry: 1342 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1343 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1344 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1345 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1346 // CHECK11-NEXT: ret void 1347 // 1348 // 1349 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 1350 // CHECK11-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] { 1351 // CHECK11-NEXT: entry: 1352 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1353 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1354 // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1355 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1356 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1357 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1358 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..1, i32 [[TMP1]]) 1359 // CHECK11-NEXT: ret void 1360 // 1361 // 1362 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 1363 // CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { 1364 // CHECK11-NEXT: entry: 1365 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1366 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1367 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1368 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1369 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1370 // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1371 // CHECK11-NEXT: ret void 1372 // 1373 // 1374 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1375 // CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { 1376 // CHECK11-NEXT: entry: 1377 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1378 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1379 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 1380 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 1381 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 1382 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 1383 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 1384 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 1385 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 1386 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x ptr], align 4 1387 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x ptr], align 4 1388 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x ptr], align 4 1389 // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) 1390 // CHECK11-NEXT: store i32 0, ptr [[T_VAR]], align 128 1391 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1392 // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1393 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 1394 // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1 1395 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 1396 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 1397 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1398 // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[TMP0]], align 4 1399 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1400 // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[TMP1]], align 4 1401 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1402 // CHECK11-NEXT: store ptr null, ptr [[TMP2]], align 4 1403 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1404 // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP3]], align 4 1405 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1406 // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 4 1407 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1408 // CHECK11-NEXT: store ptr null, ptr [[TMP5]], align 4 1409 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1410 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP6]], align 4 1411 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1412 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP7]], align 4 1413 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1414 // CHECK11-NEXT: store ptr null, ptr [[TMP8]], align 4 1415 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1416 // CHECK11-NEXT: store ptr [[VAR]], ptr [[TMP9]], align 4 1417 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1418 // CHECK11-NEXT: store ptr [[VAR]], ptr [[TMP10]], align 4 1419 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1420 // CHECK11-NEXT: store ptr null, ptr [[TMP11]], align 4 1421 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1422 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1423 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1424 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1425 // CHECK11-NEXT: store i32 1, ptr [[TMP14]], align 4 1426 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1427 // CHECK11-NEXT: store i32 4, ptr [[TMP15]], align 4 1428 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1429 // CHECK11-NEXT: store ptr [[TMP12]], ptr [[TMP16]], align 4 1430 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1431 // CHECK11-NEXT: store ptr [[TMP13]], ptr [[TMP17]], align 4 1432 // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1433 // CHECK11-NEXT: store ptr @.offload_sizes.5, ptr [[TMP18]], align 4 1434 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1435 // CHECK11-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP19]], align 4 1436 // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1437 // CHECK11-NEXT: store ptr null, ptr [[TMP20]], align 4 1438 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1439 // CHECK11-NEXT: store ptr null, ptr [[TMP21]], align 4 1440 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1441 // CHECK11-NEXT: store i64 0, ptr [[TMP22]], align 8 1442 // CHECK11-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, ptr [[KERNEL_ARGS]]) 1443 // CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 1444 // CHECK11-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1445 // CHECK11: omp_offload.failed: 1446 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) #[[ATTR4]] 1447 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1448 // CHECK11: omp_offload.cont: 1449 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 1450 // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[TMP25]], align 4 1451 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 1452 // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[TMP26]], align 4 1453 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 1454 // CHECK11-NEXT: store ptr null, ptr [[TMP27]], align 4 1455 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 1456 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 1457 // CHECK11-NEXT: [[KERNEL_ARGS4:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1458 // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 0 1459 // CHECK11-NEXT: store i32 1, ptr [[TMP30]], align 4 1460 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 1 1461 // CHECK11-NEXT: store i32 1, ptr [[TMP31]], align 4 1462 // CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 2 1463 // CHECK11-NEXT: store ptr [[TMP28]], ptr [[TMP32]], align 4 1464 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 3 1465 // CHECK11-NEXT: store ptr [[TMP29]], ptr [[TMP33]], align 4 1466 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 4 1467 // CHECK11-NEXT: store ptr @.offload_sizes.8, ptr [[TMP34]], align 4 1468 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 5 1469 // CHECK11-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP35]], align 4 1470 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 6 1471 // CHECK11-NEXT: store ptr null, ptr [[TMP36]], align 4 1472 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 7 1473 // CHECK11-NEXT: store ptr null, ptr [[TMP37]], align 4 1474 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS4]], i32 0, i32 8 1475 // CHECK11-NEXT: store i64 0, ptr [[TMP38]], align 8 1476 // CHECK11-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, ptr [[KERNEL_ARGS4]]) 1477 // CHECK11-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 1478 // CHECK11-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] 1479 // CHECK11: omp_offload.failed5: 1480 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(ptr [[T_VAR]]) #[[ATTR4]] 1481 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] 1482 // CHECK11: omp_offload.cont6: 1483 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 1484 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1485 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1486 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1487 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1488 // CHECK11: arraydestroy.body: 1489 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP41]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1490 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1491 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1492 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1493 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1494 // CHECK11: arraydestroy.done7: 1495 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1496 // CHECK11-NEXT: [[TMP42:%.*]] = load i32, ptr [[RETVAL]], align 4 1497 // CHECK11-NEXT: ret i32 [[TMP42]] 1498 // 1499 // 1500 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1501 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1502 // CHECK11-NEXT: entry: 1503 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1504 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1505 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1506 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1507 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 1508 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1509 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 1510 // CHECK11-NEXT: ret void 1511 // 1512 // 1513 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1514 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1515 // CHECK11-NEXT: entry: 1516 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1517 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1518 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1519 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1520 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1521 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1522 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1523 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 1524 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1525 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1526 // CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 4 1527 // CHECK11-NEXT: ret void 1528 // 1529 // 1530 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1531 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1532 // CHECK11-NEXT: entry: 1533 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1534 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1535 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1536 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 1537 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 1538 // CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 1539 // CHECK11-NEXT: store i32 0, ptr [[B]], align 4 1540 // CHECK11-NEXT: ret void 1541 // 1542 // 1543 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1544 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1545 // CHECK11-NEXT: entry: 1546 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1547 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1548 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1549 // CHECK11-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1550 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1551 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1552 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1553 // CHECK11-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 1554 // CHECK11-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 1555 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1556 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1557 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1558 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1559 // CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 4 1560 // CHECK11-NEXT: ret void 1561 // 1562 // 1563 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1564 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1565 // CHECK11-NEXT: entry: 1566 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1567 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1568 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1569 // CHECK11-NEXT: ret void 1570 // 1571 // 1572 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1573 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1574 // CHECK11-NEXT: entry: 1575 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1576 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1577 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1578 // CHECK11-NEXT: ret void 1579 // 1580 // 1581 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1582 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1583 // CHECK11-NEXT: entry: 1584 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1585 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1586 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1587 // CHECK11-NEXT: call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) 1588 // CHECK11-NEXT: ret void 1589 // 1590 // 1591 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1592 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1593 // CHECK11-NEXT: entry: 1594 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1595 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1596 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1597 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1598 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1599 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1600 // CHECK11-NEXT: call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 1601 // CHECK11-NEXT: ret void 1602 // 1603 // 1604 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 1605 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1606 // CHECK11-NEXT: entry: 1607 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 1608 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1609 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1610 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1611 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1612 // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1613 // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1614 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1615 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1616 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 1617 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1618 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1619 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1620 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP0]], align 128 1621 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 128 1622 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @.omp_outlined..4, ptr [[TMP1]], ptr [[T_VAR1]], ptr [[TMP2]], ptr [[TMP3]]) 1623 // CHECK11-NEXT: ret void 1624 // 1625 // 1626 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 1627 // CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1628 // CHECK11-NEXT: entry: 1629 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1630 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1631 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1632 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 1633 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1634 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1635 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1636 // CHECK11-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 1637 // CHECK11-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 1638 // CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1639 // CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 1640 // CHECK11-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1641 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1642 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1643 // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1644 // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1645 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1646 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1647 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1648 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 1649 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1650 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1651 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 128 1652 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 128 1653 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC2]], ptr align 128 [[TMP0]], i32 8, i1 false) 1654 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1655 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1656 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] 1657 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1658 // CHECK11: omp.arraycpy.body: 1659 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1660 // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1661 // CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1662 // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) 1663 // CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 1664 // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1665 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1666 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] 1667 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1668 // CHECK11: omp.arraycpy.done4: 1669 // CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1670 // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR5]], ptr nonnull align 4 dereferenceable(4) [[TMP3]], ptr [[AGG_TMP6]]) 1671 // CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 1672 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR1]], align 128 1673 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 0 1674 // CHECK11-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 128 1675 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1676 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX7]], ptr align 128 [[VAR5]], i32 4, i1 false) 1677 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 1678 // CHECK11-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 1679 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i32 2 1680 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1681 // CHECK11: arraydestroy.body: 1682 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1683 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1684 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1685 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 1686 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 1687 // CHECK11: arraydestroy.done9: 1688 // CHECK11-NEXT: ret void 1689 // 1690 // 1691 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1692 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1693 // CHECK11-NEXT: entry: 1694 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1695 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1696 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1697 // CHECK11-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1698 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1699 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1700 // CHECK11-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) 1701 // CHECK11-NEXT: ret void 1702 // 1703 // 1704 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1705 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1706 // CHECK11-NEXT: entry: 1707 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1708 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1709 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1710 // CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1711 // CHECK11-NEXT: ret void 1712 // 1713 // 1714 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 1715 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1716 // CHECK11-NEXT: entry: 1717 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 1718 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1719 // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1720 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 1721 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128 1722 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR1]], align 128 1723 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @.omp_outlined..7, ptr [[T_VAR1]]) 1724 // CHECK11-NEXT: ret void 1725 // 1726 // 1727 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 1728 // CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1729 // CHECK11-NEXT: entry: 1730 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1731 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1732 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 1733 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1734 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1735 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1736 // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1737 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 1738 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 128 1739 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR1]], align 128 1740 // CHECK11-NEXT: ret void 1741 // 1742 // 1743 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1744 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1745 // CHECK11-NEXT: entry: 1746 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1747 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1748 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1749 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1750 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 1751 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1752 // CHECK11-NEXT: ret void 1753 // 1754 // 1755 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1756 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1757 // CHECK11-NEXT: entry: 1758 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1759 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1760 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1761 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1762 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1763 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1764 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1765 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 1766 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1767 // CHECK11-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1768 // CHECK11-NEXT: ret void 1769 // 1770 // 1771 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1772 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1773 // CHECK11-NEXT: entry: 1774 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1775 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1776 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1777 // CHECK11-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1778 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1779 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1780 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1781 // CHECK11-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 1782 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 1783 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1784 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1785 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1786 // CHECK11-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1787 // CHECK11-NEXT: ret void 1788 // 1789 // 1790 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1791 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1792 // CHECK11-NEXT: entry: 1793 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1794 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1795 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1796 // CHECK11-NEXT: ret void 1797 // 1798 // 1799 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1800 // CHECK11-SAME: () #[[ATTR6:[0-9]+]] { 1801 // CHECK11-NEXT: entry: 1802 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 1803 // CHECK11-NEXT: ret void 1804 // 1805 // 1806 // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg 1807 // CHECK17-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i32 signext [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 1808 // CHECK17-NEXT: entry: 1809 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1810 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 1811 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1812 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 1813 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 1814 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1815 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1816 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1817 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x ptr], align 8 1818 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x ptr], align 8 1819 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x ptr], align 8 1820 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 8 1821 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1822 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 1823 // CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1824 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 1825 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1826 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1827 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 1828 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 1829 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 1830 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 1831 // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave() 1832 // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 1833 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 1834 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 1835 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8 1836 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 1837 // CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1838 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8 1839 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 1840 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[N_ADDR]], align 4 1841 // CHECK17-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4 1842 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[N_CASTED]], align 8 1843 // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 1844 // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 1845 // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 64, i1 false) 1846 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1847 // CHECK17-NEXT: store ptr [[TMP8]], ptr [[TMP15]], align 8 1848 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1849 // CHECK17-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8 1850 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1851 // CHECK17-NEXT: store ptr null, ptr [[TMP17]], align 8 1852 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1853 // CHECK17-NEXT: store ptr [[TMP9]], ptr [[TMP18]], align 8 1854 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1855 // CHECK17-NEXT: store ptr [[TMP9]], ptr [[TMP19]], align 8 1856 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1857 // CHECK17-NEXT: store ptr null, ptr [[TMP20]], align 8 1858 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1859 // CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP21]], align 8 1860 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1861 // CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP22]], align 8 1862 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1863 // CHECK17-NEXT: store ptr null, ptr [[TMP23]], align 8 1864 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1865 // CHECK17-NEXT: store ptr [[TMP10]], ptr [[TMP24]], align 8 1866 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1867 // CHECK17-NEXT: store ptr [[TMP10]], ptr [[TMP25]], align 8 1868 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1869 // CHECK17-NEXT: store ptr null, ptr [[TMP26]], align 8 1870 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1871 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP27]], align 8 1872 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1873 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP28]], align 8 1874 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1875 // CHECK17-NEXT: store ptr null, ptr [[TMP29]], align 8 1876 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 1877 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP30]], align 8 1878 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 1879 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP31]], align 8 1880 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 1881 // CHECK17-NEXT: store ptr null, ptr [[TMP32]], align 8 1882 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 1883 // CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP33]], align 8 1884 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6 1885 // CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP34]], align 8 1886 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 6 1887 // CHECK17-NEXT: store i64 [[TMP14]], ptr [[TMP35]], align 8 1888 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 1889 // CHECK17-NEXT: store ptr null, ptr [[TMP36]], align 8 1890 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 1891 // CHECK17-NEXT: store i64 [[TMP12]], ptr [[TMP37]], align 8 1892 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7 1893 // CHECK17-NEXT: store i64 [[TMP12]], ptr [[TMP38]], align 8 1894 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 1895 // CHECK17-NEXT: store ptr null, ptr [[TMP39]], align 8 1896 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1897 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1898 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [8 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1899 // CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1900 // CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1901 // CHECK17-NEXT: store i32 1, ptr [[TMP43]], align 4 1902 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1903 // CHECK17-NEXT: store i32 8, ptr [[TMP44]], align 4 1904 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1905 // CHECK17-NEXT: store ptr [[TMP40]], ptr [[TMP45]], align 8 1906 // CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1907 // CHECK17-NEXT: store ptr [[TMP41]], ptr [[TMP46]], align 8 1908 // CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1909 // CHECK17-NEXT: store ptr [[TMP42]], ptr [[TMP47]], align 8 1910 // CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1911 // CHECK17-NEXT: store ptr @.offload_maptypes, ptr [[TMP48]], align 8 1912 // CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1913 // CHECK17-NEXT: store ptr null, ptr [[TMP49]], align 8 1914 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1915 // CHECK17-NEXT: store ptr null, ptr [[TMP50]], align 8 1916 // CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1917 // CHECK17-NEXT: store i64 0, ptr [[TMP51]], align 8 1918 // CHECK17-NEXT: [[TMP52:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, ptr [[KERNEL_ARGS]]) 1919 // CHECK17-NEXT: [[TMP53:%.*]] = icmp ne i32 [[TMP52]], 0 1920 // CHECK17-NEXT: br i1 [[TMP53]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1921 // CHECK17: omp_offload.failed: 1922 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(ptr [[TMP8]], ptr [[TMP9]], i64 [[TMP1]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 1923 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 1924 // CHECK17: omp_offload.cont: 1925 // CHECK17-NEXT: [[TMP54:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 1926 // CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP54]]) 1927 // CHECK17-NEXT: ret void 1928 // 1929 // 1930 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152 1931 // CHECK17-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 1932 // CHECK17-NEXT: entry: 1933 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1934 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 1935 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1936 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 1937 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 1938 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 1939 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 8 1940 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1941 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1942 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 1943 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1944 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 1945 // CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8 1946 // CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8 1947 // CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8 1948 // CHECK17-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 1949 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1950 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 1951 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 1952 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 1953 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[S_ADDR]], align 8 1954 // CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 1955 // CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1956 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 8, ptr @.omp_outlined., ptr [[TMP4]], ptr [[N_ADDR]], i64 [[TMP0]], ptr [[TMP5]], ptr [[TMP6]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) 1957 // CHECK17-NEXT: ret void 1958 // 1959 // 1960 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 1961 // CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[S:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { 1962 // CHECK17-NEXT: entry: 1963 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1964 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1965 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 1966 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 1967 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1968 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 1969 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1970 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 1971 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 1972 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 8 1973 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 1974 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1975 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1976 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1977 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1978 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 1979 // CHECK17-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 1980 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1981 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 1982 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1983 // CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8 1984 // CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8 1985 // CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8 1986 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8 1987 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1988 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 1989 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 1990 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 1991 // CHECK17-NEXT: [[TMP5:%.*]] = call ptr @llvm.stacksave() 1992 // CHECK17-NEXT: store ptr [[TMP5]], ptr [[SAVED_STACK]], align 8 1993 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 1994 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 1995 // CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 1996 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 1997 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 1998 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 1999 // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP8]], i1 false) 2000 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8 2001 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i64 0 2002 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 8 2003 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 4 2004 // CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 2005 // CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPg(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 signext [[TMP11]], ptr [[TMP12]]) 2006 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 2007 // CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) 2008 // CHECK17-NEXT: ret void 2009 // 2010 // 2011 // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg 2012 // CHECK17-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 signext [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 2013 // CHECK17-NEXT: entry: 2014 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2015 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 2016 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2017 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 2018 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 2019 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2020 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 2021 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 2022 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x ptr], align 8 2023 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x ptr], align 8 2024 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x ptr], align 8 2025 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 2026 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2027 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 2028 // CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2029 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 2030 // CHECK17-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2031 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2032 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 2033 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 2034 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 2035 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 2036 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 2037 // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave() 2038 // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 2039 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 2040 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 2041 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8 2042 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 2043 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 1 2044 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4 2045 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0 2046 // CHECK17-NEXT: store i32 [[TMP8]], ptr [[A]], align 4 2047 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8 2048 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 2049 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[N_ADDR]], align 4 2050 // CHECK17-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4 2051 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[N_CASTED]], align 8 2052 // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 2053 // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 2054 // CHECK17-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 2055 // CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0 2056 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[B2]], i32 1 2057 // CHECK17-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP15]] to i64 2058 // CHECK17-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[A3]] to i64 2059 // CHECK17-NEXT: [[TMP18:%.*]] = sub i64 [[TMP16]], [[TMP17]] 2060 // CHECK17-NEXT: [[TMP19:%.*]] = sdiv exact i64 [[TMP18]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) 2061 // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.2, i64 80, i1 false) 2062 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2063 // CHECK17-NEXT: store ptr [[TMP9]], ptr [[TMP20]], align 8 2064 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2065 // CHECK17-NEXT: store ptr [[TMP9]], ptr [[TMP21]], align 8 2066 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2067 // CHECK17-NEXT: store ptr null, ptr [[TMP22]], align 8 2068 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2069 // CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP23]], align 8 2070 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2071 // CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP24]], align 8 2072 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2073 // CHECK17-NEXT: store ptr null, ptr [[TMP25]], align 8 2074 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2075 // CHECK17-NEXT: store ptr [[TMP10]], ptr [[TMP26]], align 8 2076 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2077 // CHECK17-NEXT: store ptr [[TMP10]], ptr [[TMP27]], align 8 2078 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2079 // CHECK17-NEXT: store ptr null, ptr [[TMP28]], align 8 2080 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2081 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP29]], align 8 2082 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2083 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP30]], align 8 2084 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2085 // CHECK17-NEXT: store ptr null, ptr [[TMP31]], align 8 2086 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2087 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP32]], align 8 2088 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2089 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP33]], align 8 2090 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 2091 // CHECK17-NEXT: store ptr null, ptr [[TMP34]], align 8 2092 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 2093 // CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP35]], align 8 2094 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 2095 // CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP36]], align 8 2096 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 5 2097 // CHECK17-NEXT: store i64 [[TMP14]], ptr [[TMP37]], align 8 2098 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 2099 // CHECK17-NEXT: store ptr null, ptr [[TMP38]], align 8 2100 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 2101 // CHECK17-NEXT: store ptr [[THIS1]], ptr [[TMP39]], align 8 2102 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6 2103 // CHECK17-NEXT: store ptr [[A3]], ptr [[TMP40]], align 8 2104 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 6 2105 // CHECK17-NEXT: store i64 [[TMP19]], ptr [[TMP41]], align 8 2106 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 2107 // CHECK17-NEXT: store ptr null, ptr [[TMP42]], align 8 2108 // CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 2109 // CHECK17-NEXT: store ptr [[THIS1]], ptr [[TMP43]], align 8 2110 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7 2111 // CHECK17-NEXT: store ptr [[B2]], ptr [[TMP44]], align 8 2112 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 2113 // CHECK17-NEXT: store ptr null, ptr [[TMP45]], align 8 2114 // CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 2115 // CHECK17-NEXT: store ptr [[THIS1]], ptr [[TMP46]], align 8 2116 // CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8 2117 // CHECK17-NEXT: store ptr [[A3]], ptr [[TMP47]], align 8 2118 // CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 2119 // CHECK17-NEXT: store ptr null, ptr [[TMP48]], align 8 2120 // CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 2121 // CHECK17-NEXT: store i64 [[TMP12]], ptr [[TMP49]], align 8 2122 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 9 2123 // CHECK17-NEXT: store i64 [[TMP12]], ptr [[TMP50]], align 8 2124 // CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9 2125 // CHECK17-NEXT: store ptr null, ptr [[TMP51]], align 8 2126 // CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2127 // CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2128 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2129 // CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2130 // CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2131 // CHECK17-NEXT: store i32 1, ptr [[TMP55]], align 4 2132 // CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2133 // CHECK17-NEXT: store i32 10, ptr [[TMP56]], align 4 2134 // CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2135 // CHECK17-NEXT: store ptr [[TMP52]], ptr [[TMP57]], align 8 2136 // CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2137 // CHECK17-NEXT: store ptr [[TMP53]], ptr [[TMP58]], align 8 2138 // CHECK17-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2139 // CHECK17-NEXT: store ptr [[TMP54]], ptr [[TMP59]], align 8 2140 // CHECK17-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2141 // CHECK17-NEXT: store ptr @.offload_maptypes.3, ptr [[TMP60]], align 8 2142 // CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2143 // CHECK17-NEXT: store ptr null, ptr [[TMP61]], align 8 2144 // CHECK17-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2145 // CHECK17-NEXT: store ptr null, ptr [[TMP62]], align 8 2146 // CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2147 // CHECK17-NEXT: store i64 0, ptr [[TMP63]], align 8 2148 // CHECK17-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, ptr [[KERNEL_ARGS]]) 2149 // CHECK17-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 2150 // CHECK17-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2151 // CHECK17: omp_offload.failed: 2152 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(ptr [[TMP9]], i64 [[TMP1]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], ptr [[THIS1]], i64 [[TMP12]]) #[[ATTR4]] 2153 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 2154 // CHECK17: omp_offload.cont: 2155 // CHECK17-NEXT: [[TMP66:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 2156 // CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP66]]) 2157 // CHECK17-NEXT: ret void 2158 // 2159 // 2160 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144 2161 // CHECK17-SAME: (ptr [[S:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], ptr [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { 2162 // CHECK17-NEXT: entry: 2163 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 2164 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2165 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 2166 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 2167 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 2168 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 8 2169 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2170 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 2171 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 2172 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 2173 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 2174 // CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8 2175 // CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8 2176 // CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8 2177 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2178 // CHECK17-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 2179 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 2180 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 2181 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 2182 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 2183 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2184 // CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 2185 // CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[S_ADDR]], align 8 2186 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 8, ptr @.omp_outlined..1, i64 [[TMP0]], ptr [[TMP5]], ptr [[TMP4]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]], ptr [[N_ADDR]], ptr [[TMP6]]) 2187 // CHECK17-NEXT: ret void 2188 // 2189 // 2190 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 2191 // CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], ptr [[S:%.*]]) #[[ATTR2]] { 2192 // CHECK17-NEXT: entry: 2193 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2194 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2195 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2196 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 2197 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2198 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 2199 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 2200 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 8 2201 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 2202 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 2203 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 2204 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2205 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 2206 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2207 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2208 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 2209 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 2210 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2211 // CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8 2212 // CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8 2213 // CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8 2214 // CHECK17-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 2215 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 2216 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 2217 // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2218 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 2219 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 2220 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 2221 // CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[N_ADDR]], align 8 2222 // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave() 2223 // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 2224 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 2225 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128 2226 // CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 2227 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 2228 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 2229 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8 2230 // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP9]], i1 false) 2231 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP1]], i32 0, i32 1 2232 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4 2233 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 0 2234 // CHECK17-NEXT: store i32 [[TMP10]], ptr [[A]], align 4 2235 // CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double 2236 // CHECK17-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP3]] 2237 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[VLA7]], i64 [[TMP11]] 2238 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP5]], align 4 2239 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP12]], 1 2240 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 2241 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i64 [[IDXPROM]] 2242 // CHECK17-NEXT: store double [[CONV]], ptr [[ARRAYIDX8]], align 8 2243 // CHECK17-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128 2244 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 2245 // CHECK17-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 1 2246 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[B10]], align 4 2247 // CHECK17-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP14]] to i64 2248 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ptr [[TMP13]], i64 [[IDXPROM11]] 2249 // CHECK17-NEXT: store ppc_fp128 [[CONV9]], ptr [[ARRAYIDX12]], align 16 2250 // CHECK17-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 2251 // CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) 2252 // CHECK17-NEXT: ret void 2253 // 2254 // 2255 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2256 // CHECK17-SAME: () #[[ATTR5:[0-9]+]] { 2257 // CHECK17-NEXT: entry: 2258 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 2259 // CHECK17-NEXT: ret void 2260 // 2261 // 2262 // CHECK19-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe 2263 // CHECK19-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 2264 // CHECK19-NEXT: entry: 2265 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 2266 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2267 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2268 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 4 2269 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2270 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2271 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2272 // CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 2273 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x ptr], align 4 2274 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x ptr], align 4 2275 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x ptr], align 4 2276 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 4 2277 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 2278 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2279 // CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2280 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 2281 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2282 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 2283 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 2284 // CHECK19-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 2285 // CHECK19-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 4 2286 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 2287 // CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 2288 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 2289 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 2290 // CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 4 2291 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2292 // CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 2293 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 4 2294 // CHECK19-NEXT: store i32 [[TMP8]], ptr [[N_CASTED]], align 4 2295 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_CASTED]], align 4 2296 // CHECK19-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 2297 // CHECK19-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 2298 // CHECK19-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 2299 // CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes, i32 64, i1 false) 2300 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2301 // CHECK19-NEXT: store ptr [[TMP5]], ptr [[TMP13]], align 4 2302 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2303 // CHECK19-NEXT: store ptr [[TMP5]], ptr [[TMP14]], align 4 2304 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2305 // CHECK19-NEXT: store ptr null, ptr [[TMP15]], align 4 2306 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2307 // CHECK19-NEXT: store ptr [[TMP6]], ptr [[TMP16]], align 4 2308 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2309 // CHECK19-NEXT: store ptr [[TMP6]], ptr [[TMP17]], align 4 2310 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2311 // CHECK19-NEXT: store ptr null, ptr [[TMP18]], align 4 2312 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2313 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[TMP19]], align 4 2314 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2315 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[TMP20]], align 4 2316 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2317 // CHECK19-NEXT: store ptr null, ptr [[TMP21]], align 4 2318 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2319 // CHECK19-NEXT: store ptr [[TMP7]], ptr [[TMP22]], align 4 2320 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2321 // CHECK19-NEXT: store ptr [[TMP7]], ptr [[TMP23]], align 4 2322 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2323 // CHECK19-NEXT: store ptr null, ptr [[TMP24]], align 4 2324 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2325 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP25]], align 4 2326 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2327 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP26]], align 4 2328 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2329 // CHECK19-NEXT: store ptr null, ptr [[TMP27]], align 4 2330 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 2331 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[TMP28]], align 4 2332 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 2333 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[TMP29]], align 4 2334 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 2335 // CHECK19-NEXT: store ptr null, ptr [[TMP30]], align 4 2336 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 2337 // CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP31]], align 4 2338 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6 2339 // CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP32]], align 4 2340 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 6 2341 // CHECK19-NEXT: store i64 [[TMP12]], ptr [[TMP33]], align 4 2342 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 2343 // CHECK19-NEXT: store ptr null, ptr [[TMP34]], align 4 2344 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 2345 // CHECK19-NEXT: store i32 [[TMP9]], ptr [[TMP35]], align 4 2346 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7 2347 // CHECK19-NEXT: store i32 [[TMP9]], ptr [[TMP36]], align 4 2348 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 2349 // CHECK19-NEXT: store ptr null, ptr [[TMP37]], align 4 2350 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2351 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2352 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [8 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2353 // CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2354 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2355 // CHECK19-NEXT: store i32 1, ptr [[TMP41]], align 4 2356 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2357 // CHECK19-NEXT: store i32 8, ptr [[TMP42]], align 4 2358 // CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2359 // CHECK19-NEXT: store ptr [[TMP38]], ptr [[TMP43]], align 4 2360 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2361 // CHECK19-NEXT: store ptr [[TMP39]], ptr [[TMP44]], align 4 2362 // CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2363 // CHECK19-NEXT: store ptr [[TMP40]], ptr [[TMP45]], align 4 2364 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2365 // CHECK19-NEXT: store ptr @.offload_maptypes, ptr [[TMP46]], align 4 2366 // CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2367 // CHECK19-NEXT: store ptr null, ptr [[TMP47]], align 4 2368 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2369 // CHECK19-NEXT: store ptr null, ptr [[TMP48]], align 4 2370 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2371 // CHECK19-NEXT: store i64 0, ptr [[TMP49]], align 8 2372 // CHECK19-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, ptr [[KERNEL_ARGS]]) 2373 // CHECK19-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 2374 // CHECK19-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2375 // CHECK19: omp_offload.failed: 2376 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(ptr [[TMP5]], ptr [[TMP6]], i32 [[TMP0]], ptr [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], ptr [[VLA]], i32 [[TMP9]]) #[[ATTR4:[0-9]+]] 2377 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 2378 // CHECK19: omp_offload.cont: 2379 // CHECK19-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2380 // CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP52]]) 2381 // CHECK19-NEXT: ret void 2382 // 2383 // 2384 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152 2385 // CHECK19-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i32 [[VLA:%.*]], ptr [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], ptr nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 2386 // CHECK19-NEXT: entry: 2387 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 2388 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2389 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2390 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 4 2391 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 2392 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 2393 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 4 2394 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2395 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 2396 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2397 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2398 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 2399 // CHECK19-NEXT: store i32 [[VLA2]], ptr [[VLA_ADDR3]], align 4 2400 // CHECK19-NEXT: store i32 [[VLA4]], ptr [[VLA_ADDR5]], align 4 2401 // CHECK19-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 4 2402 // CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2403 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2404 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR3]], align 4 2405 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR5]], align 4 2406 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 4 2407 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2408 // CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 2409 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[A_ADDR]], align 4 2410 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 8, ptr @.omp_outlined., ptr [[TMP4]], ptr [[N_ADDR]], i32 [[TMP0]], ptr [[TMP5]], ptr [[TMP6]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) 2411 // CHECK19-NEXT: ret void 2412 // 2413 // 2414 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 2415 // CHECK19-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[S:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[A:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], ptr nonnull align 4 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { 2416 // CHECK19-NEXT: entry: 2417 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2418 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2419 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2420 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 4 2421 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2422 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 4 2423 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 2424 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 2425 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 2426 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 4 2427 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2428 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2429 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2430 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2431 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2432 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2433 // CHECK19-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4 2434 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2435 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 2436 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 2437 // CHECK19-NEXT: store i32 [[VLA2]], ptr [[VLA_ADDR3]], align 4 2438 // CHECK19-NEXT: store i32 [[VLA4]], ptr [[VLA_ADDR5]], align 4 2439 // CHECK19-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 4 2440 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 4 2441 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2442 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR3]], align 4 2443 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR5]], align 4 2444 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 4 2445 // CHECK19-NEXT: [[TMP5:%.*]] = call ptr @llvm.stacksave() 2446 // CHECK19-NEXT: store ptr [[TMP5]], ptr [[SAVED_STACK]], align 4 2447 // CHECK19-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 2448 // CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128 2449 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR0]], align 4 2450 // CHECK19-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 2451 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 2452 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8 2453 // CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i32 [[TMP8]], i1 false) 2454 // CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2455 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i32 0 2456 // CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2457 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 4 2458 // CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 2459 // CHECK19-NEXT: call void @_ZN2St7St_funcEPS_iPe(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 [[TMP11]], ptr [[TMP12]]) 2460 // CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2461 // CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP13]]) 2462 // CHECK19-NEXT: ret void 2463 // 2464 // 2465 // CHECK19-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe 2466 // CHECK19-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 2467 // CHECK19-NEXT: entry: 2468 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2469 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2470 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2471 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 4 2472 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2473 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2474 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2475 // CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 2476 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x ptr], align 4 2477 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x ptr], align 4 2478 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x ptr], align 4 2479 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 2480 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2481 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2482 // CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2483 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 2484 // CHECK19-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2485 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2486 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 2487 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 2488 // CHECK19-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 2489 // CHECK19-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 4 2490 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 2491 // CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 2492 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 2493 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 2494 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 1 2495 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 2496 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0 2497 // CHECK19-NEXT: store i32 [[TMP5]], ptr [[A]], align 4 2498 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2499 // CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 2500 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 4 2501 // CHECK19-NEXT: store i32 [[TMP8]], ptr [[N_CASTED]], align 4 2502 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_CASTED]], align 4 2503 // CHECK19-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 2504 // CHECK19-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 2505 // CHECK19-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 2506 // CHECK19-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 2507 // CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0 2508 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[B2]], i32 1 2509 // CHECK19-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64 2510 // CHECK19-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[A3]] to i64 2511 // CHECK19-NEXT: [[TMP16:%.*]] = sub i64 [[TMP14]], [[TMP15]] 2512 // CHECK19-NEXT: [[TMP17:%.*]] = sdiv exact i64 [[TMP16]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) 2513 // CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.2, i32 80, i1 false) 2514 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2515 // CHECK19-NEXT: store ptr [[TMP6]], ptr [[TMP18]], align 4 2516 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2517 // CHECK19-NEXT: store ptr [[TMP6]], ptr [[TMP19]], align 4 2518 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2519 // CHECK19-NEXT: store ptr null, ptr [[TMP20]], align 4 2520 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2521 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[TMP21]], align 4 2522 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2523 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[TMP22]], align 4 2524 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2525 // CHECK19-NEXT: store ptr null, ptr [[TMP23]], align 4 2526 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2527 // CHECK19-NEXT: store ptr [[TMP7]], ptr [[TMP24]], align 4 2528 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2529 // CHECK19-NEXT: store ptr [[TMP7]], ptr [[TMP25]], align 4 2530 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2531 // CHECK19-NEXT: store ptr null, ptr [[TMP26]], align 4 2532 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2533 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP27]], align 4 2534 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2535 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP28]], align 4 2536 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2537 // CHECK19-NEXT: store ptr null, ptr [[TMP29]], align 4 2538 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2539 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[TMP30]], align 4 2540 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2541 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[TMP31]], align 4 2542 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2543 // CHECK19-NEXT: store ptr null, ptr [[TMP32]], align 4 2544 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 2545 // CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP33]], align 4 2546 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 2547 // CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP34]], align 4 2548 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 5 2549 // CHECK19-NEXT: store i64 [[TMP12]], ptr [[TMP35]], align 4 2550 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 2551 // CHECK19-NEXT: store ptr null, ptr [[TMP36]], align 4 2552 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 2553 // CHECK19-NEXT: store ptr [[THIS1]], ptr [[TMP37]], align 4 2554 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6 2555 // CHECK19-NEXT: store ptr [[A3]], ptr [[TMP38]], align 4 2556 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 6 2557 // CHECK19-NEXT: store i64 [[TMP17]], ptr [[TMP39]], align 4 2558 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 2559 // CHECK19-NEXT: store ptr null, ptr [[TMP40]], align 4 2560 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 2561 // CHECK19-NEXT: store ptr [[THIS1]], ptr [[TMP41]], align 4 2562 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7 2563 // CHECK19-NEXT: store ptr [[B2]], ptr [[TMP42]], align 4 2564 // CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 2565 // CHECK19-NEXT: store ptr null, ptr [[TMP43]], align 4 2566 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 2567 // CHECK19-NEXT: store ptr [[THIS1]], ptr [[TMP44]], align 4 2568 // CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8 2569 // CHECK19-NEXT: store ptr [[A3]], ptr [[TMP45]], align 4 2570 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 2571 // CHECK19-NEXT: store ptr null, ptr [[TMP46]], align 4 2572 // CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 2573 // CHECK19-NEXT: store i32 [[TMP9]], ptr [[TMP47]], align 4 2574 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 9 2575 // CHECK19-NEXT: store i32 [[TMP9]], ptr [[TMP48]], align 4 2576 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 9 2577 // CHECK19-NEXT: store ptr null, ptr [[TMP49]], align 4 2578 // CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2579 // CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2580 // CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2581 // CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2582 // CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2583 // CHECK19-NEXT: store i32 1, ptr [[TMP53]], align 4 2584 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2585 // CHECK19-NEXT: store i32 10, ptr [[TMP54]], align 4 2586 // CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2587 // CHECK19-NEXT: store ptr [[TMP50]], ptr [[TMP55]], align 4 2588 // CHECK19-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2589 // CHECK19-NEXT: store ptr [[TMP51]], ptr [[TMP56]], align 4 2590 // CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2591 // CHECK19-NEXT: store ptr [[TMP52]], ptr [[TMP57]], align 4 2592 // CHECK19-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2593 // CHECK19-NEXT: store ptr @.offload_maptypes.3, ptr [[TMP58]], align 4 2594 // CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2595 // CHECK19-NEXT: store ptr null, ptr [[TMP59]], align 4 2596 // CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2597 // CHECK19-NEXT: store ptr null, ptr [[TMP60]], align 4 2598 // CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2599 // CHECK19-NEXT: store i64 0, ptr [[TMP61]], align 8 2600 // CHECK19-NEXT: [[TMP62:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, ptr [[KERNEL_ARGS]]) 2601 // CHECK19-NEXT: [[TMP63:%.*]] = icmp ne i32 [[TMP62]], 0 2602 // CHECK19-NEXT: br i1 [[TMP63]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2603 // CHECK19: omp_offload.failed: 2604 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(ptr [[TMP6]], i32 [[TMP0]], ptr [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], ptr [[VLA]], ptr [[THIS1]], i32 [[TMP9]]) #[[ATTR4]] 2605 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 2606 // CHECK19: omp_offload.cont: 2607 // CHECK19-NEXT: [[TMP64:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2608 // CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP64]]) 2609 // CHECK19-NEXT: ret void 2610 // 2611 // 2612 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144 2613 // CHECK19-SAME: (ptr [[S:%.*]], i32 [[VLA:%.*]], ptr [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], ptr nonnull align 4 dereferenceable(8) [[VLA26:%.*]], ptr [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] { 2614 // CHECK19-NEXT: entry: 2615 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2616 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2617 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 4 2618 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 2619 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 2620 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 4 2621 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2622 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2623 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2624 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2625 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 2626 // CHECK19-NEXT: store i32 [[VLA2]], ptr [[VLA_ADDR3]], align 4 2627 // CHECK19-NEXT: store i32 [[VLA4]], ptr [[VLA_ADDR5]], align 4 2628 // CHECK19-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 4 2629 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2630 // CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2631 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2632 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR3]], align 4 2633 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR5]], align 4 2634 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 4 2635 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2636 // CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 2637 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2638 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 8, ptr @.omp_outlined..1, i32 [[TMP0]], ptr [[TMP5]], ptr [[TMP4]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]], ptr [[N_ADDR]], ptr [[TMP6]]) 2639 // CHECK19-NEXT: ret void 2640 // 2641 // 2642 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 2643 // CHECK19-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[THIS:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], ptr nonnull align 4 dereferenceable(8) [[VLA26:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], ptr [[S:%.*]]) #[[ATTR2]] { 2644 // CHECK19-NEXT: entry: 2645 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2646 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2647 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2648 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 4 2649 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2650 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 2651 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 2652 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 4 2653 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 4 2654 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2655 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2656 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2657 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2658 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2659 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2660 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2661 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 2662 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2663 // CHECK19-NEXT: store i32 [[VLA2]], ptr [[VLA_ADDR3]], align 4 2664 // CHECK19-NEXT: store i32 [[VLA4]], ptr [[VLA_ADDR5]], align 4 2665 // CHECK19-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 4 2666 // CHECK19-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4 2667 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2668 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2669 // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2670 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR3]], align 4 2671 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR5]], align 4 2672 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 4 2673 // CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[N_ADDR]], align 4 2674 // CHECK19-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave() 2675 // CHECK19-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 4 2676 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 2677 // CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128 2678 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR0]], align 4 2679 // CHECK19-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 2680 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 2681 // CHECK19-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8 2682 // CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i32 [[TMP9]], i1 false) 2683 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP1]], i32 0, i32 1 2684 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4 2685 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 0 2686 // CHECK19-NEXT: store i32 [[TMP10]], ptr [[A]], align 4 2687 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double 2688 // CHECK19-NEXT: [[TMP11:%.*]] = mul nsw i32 1, [[TMP3]] 2689 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[VLA7]], i32 [[TMP11]] 2690 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP5]], align 4 2691 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP12]], 1 2692 // CHECK19-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i32 [[SUB]] 2693 // CHECK19-NEXT: store double [[CONV]], ptr [[ARRAYIDX8]], align 8 2694 // CHECK19-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80 2695 // CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 2696 // CHECK19-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 1 2697 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[B10]], align 4 2698 // CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, ptr [[TMP13]], i32 [[TMP14]] 2699 // CHECK19-NEXT: store x86_fp80 [[CONV9]], ptr [[ARRAYIDX11]], align 4 2700 // CHECK19-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2701 // CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP15]]) 2702 // CHECK19-NEXT: ret void 2703 // 2704 // 2705 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2706 // CHECK19-SAME: () #[[ATTR5:[0-9]+]] { 2707 // CHECK19-NEXT: entry: 2708 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 2709 // CHECK19-NEXT: ret void 2710 // 2711