1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 5 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK2 6 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 8 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 12 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 15 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 18 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 19 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 20 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 22 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 23 24 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 25 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 26 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 27 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 28 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 29 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 30 31 // RUN: %clang_cc1 -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 33 // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK18 34 // RUN: %clang_cc1 -DARRAY -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 35 // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 36 // RUN: %clang_cc1 -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK20 37 38 // RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 39 // RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 40 // RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 41 // RUN: %clang_cc1 -DARRAY -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 42 // RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 43 // RUN: %clang_cc1 -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 44 // expected-no-diagnostics 45 #ifndef HEADER 46 #define HEADER 47 #ifndef ARRAY 48 struct St { 49 int a, b; 50 St() : a(0), b(0) {} 51 St(const St &st) : a(st.a + st.b), b(0) {} 52 ~St() {} 53 }; 54 55 volatile int g __attribute__((aligned(128))) = 1212; 56 57 template <class T> 58 struct S { 59 T f; 60 S(T a) : f(a + g) {} 61 S() : f(g) {} 62 S(const S &s, St t = St()) : f(s.f + t.a) {} 63 operator T() { return T(); } 64 ~S() {} 65 }; 66 67 68 template <typename T> 69 T tmain() { 70 S<T> test; 71 T t_var __attribute__((aligned(128))) = T(); 72 T vec[] __attribute__((aligned(128))) = {1, 2}; 73 S<T> s_arr[] __attribute__((aligned(128))) = {1, 2}; 74 S<T> var __attribute__((aligned(128))) (3); 75 #pragma omp target 76 #pragma omp teams firstprivate(t_var, vec, s_arr, var) 77 { 78 vec[0] = t_var; 79 s_arr[0] = var; 80 } 81 #pragma omp target 82 #pragma omp teams firstprivate(t_var) 83 {} 84 return T(); 85 } 86 87 int main() { 88 static int sivar; 89 #ifdef LAMBDA 90 [&]() { 91 #pragma omp target 92 #pragma omp teams firstprivate(g, sivar) 93 { 94 g = 1; 95 sivar = 2; 96 [&]() { 97 g = 2; 98 sivar = 4; 99 }(); 100 } 101 }(); 102 return 0; 103 #else 104 S<float> test; 105 int t_var = 0; 106 int vec[] = {1, 2}; 107 S<float> s_arr[] = {1, 2}; 108 S<float> var(3); 109 #pragma omp target 110 #pragma omp teams firstprivate(t_var, vec, s_arr, var, sivar) 111 { 112 vec[0] = t_var; 113 s_arr[0] = var; 114 sivar = 2; 115 } 116 #pragma omp target 117 #pragma omp teams firstprivate(t_var) 118 {} 119 return tmain<int>(); 120 #endif 121 } 122 123 124 125 126 127 128 129 130 131 132 133 134 135 #else 136 struct St { 137 int a, b; 138 St() : a(0), b(0) {} 139 St(const St &) { } 140 ~St() {} 141 void St_func(St s[2], int n, long double vla1[n]) { 142 double vla2[n][n] __attribute__((aligned(128))); 143 a = b; 144 #pragma omp target 145 #pragma omp teams firstprivate(s, vla1, vla2) 146 vla1[b] = vla2[1][n - 1] = a = b; 147 } 148 }; 149 150 void array_func(float a[3], St s[2], int n, long double vla1[n]) { 151 double vla2[n][n] __attribute__((aligned(128))); 152 #pragma omp target 153 #pragma omp teams firstprivate(a, s, vla1, vla2) 154 s[0].St_func(s, n, vla1); 155 ; 156 } 157 158 #endif 159 #endif 160 // CHECK1-LABEL: define {{[^@]+}}@main 161 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 162 // CHECK1-NEXT: entry: 163 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 164 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 165 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 166 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 167 // CHECK1-NEXT: ret i32 0 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 171 // CHECK1-SAME: (i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 174 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 175 // CHECK1-NEXT: [[G1:%.*]] = alloca i32, align 128 176 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 177 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 178 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 179 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 180 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 181 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 182 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 183 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 184 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 185 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 186 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 187 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i64 [[TMP3]]) 188 // CHECK1-NEXT: ret void 189 // 190 // 191 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 192 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2]] { 193 // CHECK1-NEXT: entry: 194 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 195 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 196 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 197 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 198 // CHECK1-NEXT: [[G1:%.*]] = alloca i32, align 128 199 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 200 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 201 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 202 // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 203 // CHECK1-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 204 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 205 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 206 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 207 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 208 // CHECK1-NEXT: store i32 1, i32* [[G1]], align 128 209 // CHECK1-NEXT: store i32 2, i32* [[CONV]], align 8 210 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 211 // CHECK1-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8 212 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 213 // CHECK1-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8 214 // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) 215 // CHECK1-NEXT: ret void 216 // 217 // 218 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 219 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 220 // CHECK1-NEXT: entry: 221 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 222 // CHECK1-NEXT: ret void 223 // 224 // 225 // CHECK2-LABEL: define {{[^@]+}}@main 226 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 227 // CHECK2-NEXT: entry: 228 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 229 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 230 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 231 // CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 232 // CHECK2-NEXT: ret i32 0 233 // 234 // 235 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 236 // CHECK2-SAME: (i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 237 // CHECK2-NEXT: entry: 238 // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 239 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 240 // CHECK2-NEXT: [[G1:%.*]] = alloca i32, align 128 241 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 242 // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 243 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 244 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 245 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 246 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 247 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 248 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 249 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 250 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 251 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 252 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i64 [[TMP3]]) 253 // CHECK2-NEXT: ret void 254 // 255 // 256 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 257 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2]] { 258 // CHECK2-NEXT: entry: 259 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 260 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 261 // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 262 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 263 // CHECK2-NEXT: [[G1:%.*]] = alloca i32, align 128 264 // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 265 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 266 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 267 // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 268 // CHECK2-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 269 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 270 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 271 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 272 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 273 // CHECK2-NEXT: store i32 1, i32* [[G1]], align 128 274 // CHECK2-NEXT: store i32 2, i32* [[CONV]], align 8 275 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 276 // CHECK2-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8 277 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 278 // CHECK2-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8 279 // CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) 280 // CHECK2-NEXT: ret void 281 // 282 // 283 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 284 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] { 285 // CHECK2-NEXT: entry: 286 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 287 // CHECK2-NEXT: ret void 288 // 289 // 290 // CHECK3-LABEL: define {{[^@]+}}@main 291 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 292 // CHECK3-NEXT: entry: 293 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 294 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 295 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 296 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 297 // CHECK3-NEXT: ret i32 0 298 // 299 // 300 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 301 // CHECK3-SAME: (i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 302 // CHECK3-NEXT: entry: 303 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 304 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 305 // CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128 306 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 307 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 308 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 309 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4 310 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 311 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 312 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 313 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 314 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 315 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i32 [[TMP3]]) 316 // CHECK3-NEXT: ret void 317 // 318 // 319 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 320 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2]] { 321 // CHECK3-NEXT: entry: 322 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 323 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 324 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 325 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 326 // CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128 327 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 328 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 329 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 330 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 331 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 332 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4 333 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 334 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 335 // CHECK3-NEXT: store i32 1, i32* [[G1]], align 128 336 // CHECK3-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 337 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 338 // CHECK3-NEXT: store i32* [[G1]], i32** [[TMP2]], align 4 339 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 340 // CHECK3-NEXT: store i32* [[SIVAR_ADDR]], i32** [[TMP3]], align 4 341 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(8) [[REF_TMP]]) 342 // CHECK3-NEXT: ret void 343 // 344 // 345 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 346 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 347 // CHECK3-NEXT: entry: 348 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 349 // CHECK3-NEXT: ret void 350 // 351 // 352 // CHECK4-LABEL: define {{[^@]+}}@main 353 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 354 // CHECK4-NEXT: entry: 355 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 356 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 357 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 358 // CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]]) 359 // CHECK4-NEXT: ret i32 0 360 // 361 // 362 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 363 // CHECK4-SAME: (i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 364 // CHECK4-NEXT: entry: 365 // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 366 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 367 // CHECK4-NEXT: [[G1:%.*]] = alloca i32, align 128 368 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 369 // CHECK4-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 370 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 371 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4 372 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 373 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 374 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 375 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[SIVAR_CASTED]], align 4 376 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 377 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[G1]], i32 [[TMP3]]) 378 // CHECK4-NEXT: ret void 379 // 380 // 381 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 382 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2]] { 383 // CHECK4-NEXT: entry: 384 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 385 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 386 // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 387 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 388 // CHECK4-NEXT: [[G1:%.*]] = alloca i32, align 128 389 // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 390 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 391 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 392 // CHECK4-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 393 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 394 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4 395 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 396 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 397 // CHECK4-NEXT: store i32 1, i32* [[G1]], align 128 398 // CHECK4-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 399 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 400 // CHECK4-NEXT: store i32* [[G1]], i32** [[TMP2]], align 4 401 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 402 // CHECK4-NEXT: store i32* [[SIVAR_ADDR]], i32** [[TMP3]], align 4 403 // CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(8) [[REF_TMP]]) 404 // CHECK4-NEXT: ret void 405 // 406 // 407 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 408 // CHECK4-SAME: () #[[ATTR4:[0-9]+]] { 409 // CHECK4-NEXT: entry: 410 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 411 // CHECK4-NEXT: ret void 412 // 413 // 414 // CHECK9-LABEL: define {{[^@]+}}@main 415 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 416 // CHECK9-NEXT: entry: 417 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 418 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 419 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 420 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 421 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 422 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 423 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 424 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 425 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 426 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 427 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 428 // CHECK9-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 429 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 430 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 431 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 432 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 433 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 434 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 435 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 436 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 437 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 438 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 439 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 440 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 441 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 442 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 443 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 444 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 445 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 446 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 447 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 448 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 449 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 450 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 451 // CHECK9-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 452 // CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 453 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 454 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 455 // CHECK9-NEXT: store i64 [[TMP2]], i64* [[TMP8]], align 8 456 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 457 // CHECK9-NEXT: store i8* null, i8** [[TMP9]], align 8 458 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 459 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** 460 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 8 461 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 462 // CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 463 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 464 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 465 // CHECK9-NEXT: store i8* null, i8** [[TMP14]], align 8 466 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 467 // CHECK9-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** 468 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 8 469 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 470 // CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** 471 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 472 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 473 // CHECK9-NEXT: store i8* null, i8** [[TMP19]], align 8 474 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 475 // CHECK9-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** 476 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 8 477 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 478 // CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** 479 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 8 480 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 481 // CHECK9-NEXT: store i8* null, i8** [[TMP24]], align 8 482 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 483 // CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 484 // CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP26]], align 8 485 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 486 // CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 487 // CHECK9-NEXT: store i64 [[TMP4]], i64* [[TMP28]], align 8 488 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 489 // CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 490 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 491 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 492 // CHECK9-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 493 // CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 494 // CHECK9-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 495 // CHECK9: omp_offload.failed: 496 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i64 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) #[[ATTR4:[0-9]+]] 497 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 498 // CHECK9: omp_offload.cont: 499 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 500 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* 501 // CHECK9-NEXT: store i32 [[TMP34]], i32* [[CONV3]], align 4 502 // CHECK9-NEXT: [[TMP35:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 503 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 504 // CHECK9-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 505 // CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP37]], align 8 506 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 507 // CHECK9-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* 508 // CHECK9-NEXT: store i64 [[TMP35]], i64* [[TMP39]], align 8 509 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 510 // CHECK9-NEXT: store i8* null, i8** [[TMP40]], align 8 511 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 512 // CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 513 // CHECK9-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 514 // CHECK9-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 515 // CHECK9-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 516 // CHECK9: omp_offload.failed7: 517 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP35]]) #[[ATTR4]] 518 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT8]] 519 // CHECK9: omp_offload.cont8: 520 // CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 521 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 522 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 523 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 524 // CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 525 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 526 // CHECK9: arraydestroy.body: 527 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT8]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 528 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 529 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 530 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 531 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 532 // CHECK9: arraydestroy.done9: 533 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 534 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 535 // CHECK9-NEXT: ret i32 [[TMP46]] 536 // 537 // 538 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 539 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 540 // CHECK9-NEXT: entry: 541 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 542 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 543 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 544 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 545 // CHECK9-NEXT: ret void 546 // 547 // 548 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 549 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 550 // CHECK9-NEXT: entry: 551 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 552 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 553 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 554 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 555 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 556 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 557 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 558 // CHECK9-NEXT: ret void 559 // 560 // 561 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 562 // CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 563 // CHECK9-NEXT: entry: 564 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 565 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 566 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 567 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 568 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 569 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 570 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 571 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 572 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 573 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 574 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 575 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 576 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 577 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 578 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 579 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 580 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 581 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 582 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 583 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 584 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 585 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 586 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 587 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 588 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 589 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 590 // CHECK9-NEXT: ret void 591 // 592 // 593 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 594 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { 595 // CHECK9-NEXT: entry: 596 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 597 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 598 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 599 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 600 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 601 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 602 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 603 // CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 604 // CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 605 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 606 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 607 // CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 608 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 609 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 610 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 611 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 612 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 613 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 614 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 615 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 616 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 617 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 618 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 619 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 620 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 621 // CHECK9-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 622 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 623 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 624 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 625 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 626 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 627 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 628 // CHECK9: omp.arraycpy.body: 629 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 630 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 631 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 632 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 633 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 634 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 635 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 636 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 637 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 638 // CHECK9: omp.arraycpy.done4: 639 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 640 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 641 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 642 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 643 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 644 // CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 645 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 646 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 647 // CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 648 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) 649 // CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 8 650 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 651 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 652 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 653 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 654 // CHECK9: arraydestroy.body: 655 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 656 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 657 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 658 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 659 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 660 // CHECK9: arraydestroy.done9: 661 // CHECK9-NEXT: ret void 662 // 663 // 664 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev 665 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 666 // CHECK9-NEXT: entry: 667 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 668 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 669 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 670 // CHECK9-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 671 // CHECK9-NEXT: ret void 672 // 673 // 674 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 675 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 676 // CHECK9-NEXT: entry: 677 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 678 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 679 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 680 // CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 681 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 682 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 683 // CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 684 // CHECK9-NEXT: ret void 685 // 686 // 687 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev 688 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 689 // CHECK9-NEXT: entry: 690 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 691 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 692 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 693 // CHECK9-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 694 // CHECK9-NEXT: ret void 695 // 696 // 697 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 698 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 699 // CHECK9-NEXT: entry: 700 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 701 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 702 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 703 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 704 // CHECK9-NEXT: ret void 705 // 706 // 707 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 708 // CHECK9-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { 709 // CHECK9-NEXT: entry: 710 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 711 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 712 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 713 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 714 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 715 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 716 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 717 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 718 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 719 // CHECK9-NEXT: ret void 720 // 721 // 722 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 723 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { 724 // CHECK9-NEXT: entry: 725 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 726 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 727 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 728 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 729 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 730 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 731 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 732 // CHECK9-NEXT: ret void 733 // 734 // 735 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 736 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { 737 // CHECK9-NEXT: entry: 738 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 739 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 740 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 741 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 742 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 743 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 744 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 745 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 746 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 747 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 748 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 749 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 750 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 751 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 128 752 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 753 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 754 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 755 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 756 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 757 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 758 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) 759 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 760 // CHECK9-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 761 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8 762 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 763 // CHECK9-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 764 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8 765 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 766 // CHECK9-NEXT: store i8* null, i8** [[TMP5]], align 8 767 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 768 // CHECK9-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 769 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 8 770 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 771 // CHECK9-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** 772 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 8 773 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 774 // CHECK9-NEXT: store i8* null, i8** [[TMP10]], align 8 775 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 776 // CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** 777 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 8 778 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 779 // CHECK9-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** 780 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 8 781 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 782 // CHECK9-NEXT: store i8* null, i8** [[TMP15]], align 8 783 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 784 // CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** 785 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 8 786 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 787 // CHECK9-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** 788 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 8 789 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 790 // CHECK9-NEXT: store i8* null, i8** [[TMP20]], align 8 791 // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 792 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 793 // CHECK9-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 794 // CHECK9-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 795 // CHECK9-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 796 // CHECK9: omp_offload.failed: 797 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] 798 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 799 // CHECK9: omp_offload.cont: 800 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 801 // CHECK9-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** 802 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 8 803 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 804 // CHECK9-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** 805 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 8 806 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 807 // CHECK9-NEXT: store i8* null, i8** [[TMP29]], align 8 808 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 809 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 810 // CHECK9-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 811 // CHECK9-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 812 // CHECK9-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] 813 // CHECK9: omp_offload.failed4: 814 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] 815 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT5]] 816 // CHECK9: omp_offload.cont5: 817 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 818 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 819 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 820 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 821 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 822 // CHECK9: arraydestroy.body: 823 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 824 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 825 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 826 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 827 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 828 // CHECK9: arraydestroy.done6: 829 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 830 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 831 // CHECK9-NEXT: ret i32 [[TMP35]] 832 // 833 // 834 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 835 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 836 // CHECK9-NEXT: entry: 837 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 838 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 839 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 840 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 841 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 842 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 843 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 844 // CHECK9-NEXT: ret void 845 // 846 // 847 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 848 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 849 // CHECK9-NEXT: entry: 850 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 851 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 852 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 853 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 854 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 855 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 856 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 857 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 858 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 859 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 860 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 861 // CHECK9-NEXT: ret void 862 // 863 // 864 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev 865 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 866 // CHECK9-NEXT: entry: 867 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 868 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 869 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 870 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 871 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 872 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 873 // CHECK9-NEXT: store i32 0, i32* [[B]], align 4 874 // CHECK9-NEXT: ret void 875 // 876 // 877 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 878 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 879 // CHECK9-NEXT: entry: 880 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 881 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 882 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 883 // CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 884 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 885 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 886 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 887 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 888 // CHECK9-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 889 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 890 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 891 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 892 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 893 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 894 // CHECK9-NEXT: ret void 895 // 896 // 897 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev 898 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 899 // CHECK9-NEXT: entry: 900 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 901 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 902 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 903 // CHECK9-NEXT: ret void 904 // 905 // 906 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 907 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 908 // CHECK9-NEXT: entry: 909 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 910 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 911 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 912 // CHECK9-NEXT: ret void 913 // 914 // 915 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 916 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 917 // CHECK9-NEXT: entry: 918 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 919 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 920 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 921 // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 922 // CHECK9-NEXT: ret void 923 // 924 // 925 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 926 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 927 // CHECK9-NEXT: entry: 928 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 929 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 930 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 931 // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 932 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 933 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 934 // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 935 // CHECK9-NEXT: ret void 936 // 937 // 938 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 939 // CHECK9-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 940 // CHECK9-NEXT: entry: 941 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 942 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 943 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 944 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 945 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 946 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 947 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 948 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 949 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 950 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 951 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 952 // CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 953 // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 954 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 955 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 956 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) 957 // CHECK9-NEXT: ret void 958 // 959 // 960 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 961 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 962 // CHECK9-NEXT: entry: 963 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 964 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 965 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 966 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 967 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 968 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 969 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 970 // CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 971 // CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 972 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 973 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 974 // CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 975 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 976 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 977 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 978 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 979 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 980 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 981 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 982 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 983 // CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 984 // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 985 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 986 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 987 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 988 // CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 989 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) 990 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 991 // CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 992 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 993 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 994 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 995 // CHECK9: omp.arraycpy.body: 996 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 997 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 998 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 999 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1000 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 1001 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1002 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1003 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 1004 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1005 // CHECK9: omp.arraycpy.done4: 1006 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1007 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 1008 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 1009 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 1010 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 1011 // CHECK9-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 1012 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 1013 // CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 1014 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 1015 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) 1016 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 1017 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1018 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 1019 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1020 // CHECK9: arraydestroy.body: 1021 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1022 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1023 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1024 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 1025 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 1026 // CHECK9: arraydestroy.done9: 1027 // CHECK9-NEXT: ret void 1028 // 1029 // 1030 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1031 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1032 // CHECK9-NEXT: entry: 1033 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1034 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1035 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1036 // CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1037 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1038 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1039 // CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1040 // CHECK9-NEXT: ret void 1041 // 1042 // 1043 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1044 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1045 // CHECK9-NEXT: entry: 1046 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1047 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1048 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1049 // CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1050 // CHECK9-NEXT: ret void 1051 // 1052 // 1053 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 1054 // CHECK9-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1055 // CHECK9-NEXT: entry: 1056 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1057 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1058 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1059 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1060 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 1061 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 1062 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) 1063 // CHECK9-NEXT: ret void 1064 // 1065 // 1066 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 1067 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1068 // CHECK9-NEXT: entry: 1069 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1070 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1071 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1072 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1073 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1074 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1075 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1076 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1077 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 1078 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 1079 // CHECK9-NEXT: ret void 1080 // 1081 // 1082 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1083 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1084 // CHECK9-NEXT: entry: 1085 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1086 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1087 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1088 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1089 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 1090 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1091 // CHECK9-NEXT: ret void 1092 // 1093 // 1094 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1095 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1096 // CHECK9-NEXT: entry: 1097 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1098 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1099 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1100 // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1101 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1102 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1103 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1104 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 1105 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1106 // CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1107 // CHECK9-NEXT: ret void 1108 // 1109 // 1110 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1111 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1112 // CHECK9-NEXT: entry: 1113 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1114 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1115 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1116 // CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1117 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1118 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1119 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1120 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1121 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1122 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1123 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1124 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1125 // CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1126 // CHECK9-NEXT: ret void 1127 // 1128 // 1129 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1130 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1131 // CHECK9-NEXT: entry: 1132 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1133 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1134 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1135 // CHECK9-NEXT: ret void 1136 // 1137 // 1138 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1139 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] { 1140 // CHECK9-NEXT: entry: 1141 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1142 // CHECK9-NEXT: ret void 1143 // 1144 // 1145 // CHECK10-LABEL: define {{[^@]+}}@main 1146 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 1147 // CHECK10-NEXT: entry: 1148 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1149 // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1150 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1151 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1152 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1153 // CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 1154 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1155 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1156 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1157 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1158 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1159 // CHECK10-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 1160 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 1161 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 1162 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 1163 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 1164 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 1165 // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 1166 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1167 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 1168 // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 1169 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 1170 // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 1171 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 1172 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 1173 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 1174 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1175 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 1176 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1177 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1178 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1179 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 1180 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1181 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1182 // CHECK10-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1183 // CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 1184 // CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1185 // CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1186 // CHECK10-NEXT: store i64 [[TMP2]], i64* [[TMP8]], align 8 1187 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1188 // CHECK10-NEXT: store i8* null, i8** [[TMP9]], align 8 1189 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1190 // CHECK10-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** 1191 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 8 1192 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1193 // CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 1194 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 1195 // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1196 // CHECK10-NEXT: store i8* null, i8** [[TMP14]], align 8 1197 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1198 // CHECK10-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** 1199 // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 8 1200 // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1201 // CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** 1202 // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 8 1203 // CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1204 // CHECK10-NEXT: store i8* null, i8** [[TMP19]], align 8 1205 // CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1206 // CHECK10-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** 1207 // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 8 1208 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1209 // CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** 1210 // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 8 1211 // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1212 // CHECK10-NEXT: store i8* null, i8** [[TMP24]], align 8 1213 // CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1214 // CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 1215 // CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP26]], align 8 1216 // CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1217 // CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 1218 // CHECK10-NEXT: store i64 [[TMP4]], i64* [[TMP28]], align 8 1219 // CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1220 // CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 1221 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1222 // CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1223 // CHECK10-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1224 // CHECK10-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1225 // CHECK10-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1226 // CHECK10: omp_offload.failed: 1227 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i64 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) #[[ATTR4:[0-9]+]] 1228 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1229 // CHECK10: omp_offload.cont: 1230 // CHECK10-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 1231 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* 1232 // CHECK10-NEXT: store i32 [[TMP34]], i32* [[CONV3]], align 4 1233 // CHECK10-NEXT: [[TMP35:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 1234 // CHECK10-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 1235 // CHECK10-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 1236 // CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP37]], align 8 1237 // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 1238 // CHECK10-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* 1239 // CHECK10-NEXT: store i64 [[TMP35]], i64* [[TMP39]], align 8 1240 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 1241 // CHECK10-NEXT: store i8* null, i8** [[TMP40]], align 8 1242 // CHECK10-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 1243 // CHECK10-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 1244 // CHECK10-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1245 // CHECK10-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 1246 // CHECK10-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 1247 // CHECK10: omp_offload.failed7: 1248 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP35]]) #[[ATTR4]] 1249 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT8]] 1250 // CHECK10: omp_offload.cont8: 1251 // CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 1252 // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1253 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1254 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1255 // CHECK10-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1256 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1257 // CHECK10: arraydestroy.body: 1258 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT8]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1259 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1260 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1261 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1262 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 1263 // CHECK10: arraydestroy.done9: 1264 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1265 // CHECK10-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 1266 // CHECK10-NEXT: ret i32 [[TMP46]] 1267 // 1268 // 1269 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1270 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1271 // CHECK10-NEXT: entry: 1272 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1273 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1274 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1275 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1276 // CHECK10-NEXT: ret void 1277 // 1278 // 1279 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1280 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1281 // CHECK10-NEXT: entry: 1282 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1283 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1284 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1285 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1286 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1287 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1288 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1289 // CHECK10-NEXT: ret void 1290 // 1291 // 1292 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 1293 // CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 1294 // CHECK10-NEXT: entry: 1295 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1296 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1297 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1298 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1299 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1300 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1301 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 1302 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1303 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1304 // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1305 // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1306 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1307 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1308 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1309 // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1310 // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1311 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1312 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 1313 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1314 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 1315 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1316 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV1]], align 8 1317 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 1318 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 1319 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 1320 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i64 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i64 [[TMP6]]) 1321 // CHECK10-NEXT: ret void 1322 // 1323 // 1324 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 1325 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { 1326 // CHECK10-NEXT: entry: 1327 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1328 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1329 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1330 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1331 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 1332 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 1333 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 1334 // CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1335 // CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 1336 // CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1337 // CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1338 // CHECK10-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1339 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1340 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1341 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1342 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1343 // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1344 // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 1345 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 1346 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1347 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1348 // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 1349 // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 1350 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 1351 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1352 // CHECK10-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1353 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 1354 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 1355 // CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1356 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 1357 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 1358 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1359 // CHECK10: omp.arraycpy.body: 1360 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1361 // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1362 // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1363 // CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1364 // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 1365 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1366 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1367 // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1368 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1369 // CHECK10: omp.arraycpy.done4: 1370 // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1371 // CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 1372 // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 1373 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 1374 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 1375 // CHECK10-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 1376 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 1377 // CHECK10-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 1378 // CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 1379 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) 1380 // CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 8 1381 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 1382 // CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 1383 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 1384 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1385 // CHECK10: arraydestroy.body: 1386 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1387 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1388 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1389 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 1390 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 1391 // CHECK10: arraydestroy.done9: 1392 // CHECK10-NEXT: ret void 1393 // 1394 // 1395 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1396 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1397 // CHECK10-NEXT: entry: 1398 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1399 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1400 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1401 // CHECK10-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 1402 // CHECK10-NEXT: ret void 1403 // 1404 // 1405 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1406 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1407 // CHECK10-NEXT: entry: 1408 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1409 // CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1410 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1411 // CHECK10-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1412 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1413 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1414 // CHECK10-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1415 // CHECK10-NEXT: ret void 1416 // 1417 // 1418 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1419 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1420 // CHECK10-NEXT: entry: 1421 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1422 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1423 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1424 // CHECK10-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 1425 // CHECK10-NEXT: ret void 1426 // 1427 // 1428 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1429 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1430 // CHECK10-NEXT: entry: 1431 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1432 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1433 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1434 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1435 // CHECK10-NEXT: ret void 1436 // 1437 // 1438 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 1439 // CHECK10-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { 1440 // CHECK10-NEXT: entry: 1441 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1442 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 1443 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1444 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1445 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 1446 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 1447 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1448 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 1449 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1450 // CHECK10-NEXT: ret void 1451 // 1452 // 1453 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 1454 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { 1455 // CHECK10-NEXT: entry: 1456 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1457 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1458 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1459 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1460 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1461 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 1462 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 1463 // CHECK10-NEXT: ret void 1464 // 1465 // 1466 // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1467 // CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { 1468 // CHECK10-NEXT: entry: 1469 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1470 // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1471 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 1472 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 1473 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 1474 // CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 1475 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1476 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1477 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1478 // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 8 1479 // CHECK10-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 8 1480 // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 8 1481 // CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 1482 // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 128 1483 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1484 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1485 // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1486 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 1487 // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1488 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 1489 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) 1490 // CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1491 // CHECK10-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 1492 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 8 1493 // CHECK10-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1494 // CHECK10-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 1495 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 8 1496 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1497 // CHECK10-NEXT: store i8* null, i8** [[TMP5]], align 8 1498 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1499 // CHECK10-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 1500 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 8 1501 // CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1502 // CHECK10-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** 1503 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 8 1504 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1505 // CHECK10-NEXT: store i8* null, i8** [[TMP10]], align 8 1506 // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1507 // CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** 1508 // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 8 1509 // CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1510 // CHECK10-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** 1511 // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 8 1512 // CHECK10-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1513 // CHECK10-NEXT: store i8* null, i8** [[TMP15]], align 8 1514 // CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1515 // CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** 1516 // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 8 1517 // CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1518 // CHECK10-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** 1519 // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 8 1520 // CHECK10-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1521 // CHECK10-NEXT: store i8* null, i8** [[TMP20]], align 8 1522 // CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1523 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1524 // CHECK10-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1525 // CHECK10-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 1526 // CHECK10-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1527 // CHECK10: omp_offload.failed: 1528 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] 1529 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] 1530 // CHECK10: omp_offload.cont: 1531 // CHECK10-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 1532 // CHECK10-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** 1533 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 8 1534 // CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 1535 // CHECK10-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** 1536 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 8 1537 // CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i64 0, i64 0 1538 // CHECK10-NEXT: store i8* null, i8** [[TMP29]], align 8 1539 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 1540 // CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 1541 // CHECK10-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1542 // CHECK10-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1543 // CHECK10-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] 1544 // CHECK10: omp_offload.failed4: 1545 // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] 1546 // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT5]] 1547 // CHECK10: omp_offload.cont5: 1548 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 1549 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1550 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1551 // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1552 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1553 // CHECK10: arraydestroy.body: 1554 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1555 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1556 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1557 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1558 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1559 // CHECK10: arraydestroy.done6: 1560 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1561 // CHECK10-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 1562 // CHECK10-NEXT: ret i32 [[TMP35]] 1563 // 1564 // 1565 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1566 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1567 // CHECK10-NEXT: entry: 1568 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1569 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1570 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1571 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1572 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 1573 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1574 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 1575 // CHECK10-NEXT: ret void 1576 // 1577 // 1578 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1579 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1580 // CHECK10-NEXT: entry: 1581 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1582 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1583 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1584 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1585 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1586 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1587 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1588 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 1589 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1590 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1591 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 1592 // CHECK10-NEXT: ret void 1593 // 1594 // 1595 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1596 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1597 // CHECK10-NEXT: entry: 1598 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1599 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1600 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1601 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 1602 // CHECK10-NEXT: store i32 0, i32* [[A]], align 4 1603 // CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 1604 // CHECK10-NEXT: store i32 0, i32* [[B]], align 4 1605 // CHECK10-NEXT: ret void 1606 // 1607 // 1608 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1609 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1610 // CHECK10-NEXT: entry: 1611 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1612 // CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1613 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1614 // CHECK10-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1615 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1616 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1617 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1618 // CHECK10-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 1619 // CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 1620 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1621 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1622 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1623 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1624 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 1625 // CHECK10-NEXT: ret void 1626 // 1627 // 1628 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1629 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1630 // CHECK10-NEXT: entry: 1631 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1632 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1633 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1634 // CHECK10-NEXT: ret void 1635 // 1636 // 1637 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1638 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1639 // CHECK10-NEXT: entry: 1640 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1641 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1642 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1643 // CHECK10-NEXT: ret void 1644 // 1645 // 1646 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1647 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1648 // CHECK10-NEXT: entry: 1649 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1650 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1651 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1652 // CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1653 // CHECK10-NEXT: ret void 1654 // 1655 // 1656 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1657 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1658 // CHECK10-NEXT: entry: 1659 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1660 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1661 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1662 // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1663 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1664 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1665 // CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 1666 // CHECK10-NEXT: ret void 1667 // 1668 // 1669 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 1670 // CHECK10-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1671 // CHECK10-NEXT: entry: 1672 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1673 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1674 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1675 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1676 // CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1677 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1678 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1679 // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1680 // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1681 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1682 // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1683 // CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1684 // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1685 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 1686 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 1687 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) 1688 // CHECK10-NEXT: ret void 1689 // 1690 // 1691 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 1692 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1693 // CHECK10-NEXT: entry: 1694 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1695 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1696 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1697 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1698 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1699 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1700 // CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1701 // CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 1702 // CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 1703 // CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1704 // CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 1705 // CHECK10-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1706 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1707 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1708 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1709 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1710 // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1711 // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1712 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1713 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1714 // CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1715 // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1716 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 1717 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 1718 // CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1719 // CHECK10-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1720 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) 1721 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1722 // CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 1723 // CHECK10-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1724 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 1725 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1726 // CHECK10: omp.arraycpy.body: 1727 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1728 // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1729 // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1730 // CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1731 // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 1732 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1733 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1734 // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 1735 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1736 // CHECK10: omp.arraycpy.done4: 1737 // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1738 // CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 1739 // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 1740 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 1741 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 1742 // CHECK10-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 1743 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 1744 // CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 1745 // CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 1746 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) 1747 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 1748 // CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1749 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 1750 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1751 // CHECK10: arraydestroy.body: 1752 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1753 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1754 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1755 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 1756 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 1757 // CHECK10: arraydestroy.done9: 1758 // CHECK10-NEXT: ret void 1759 // 1760 // 1761 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1762 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1763 // CHECK10-NEXT: entry: 1764 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1765 // CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1766 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1767 // CHECK10-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1768 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1769 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1770 // CHECK10-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1771 // CHECK10-NEXT: ret void 1772 // 1773 // 1774 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1775 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1776 // CHECK10-NEXT: entry: 1777 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1778 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1779 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1780 // CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1781 // CHECK10-NEXT: ret void 1782 // 1783 // 1784 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 1785 // CHECK10-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1786 // CHECK10-NEXT: entry: 1787 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1788 // CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1789 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1790 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1791 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 1792 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 1793 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) 1794 // CHECK10-NEXT: ret void 1795 // 1796 // 1797 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 1798 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1799 // CHECK10-NEXT: entry: 1800 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1801 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1802 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1803 // CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1804 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1805 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1806 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1807 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1808 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 1809 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 1810 // CHECK10-NEXT: ret void 1811 // 1812 // 1813 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1814 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1815 // CHECK10-NEXT: entry: 1816 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1817 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1818 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1819 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1820 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 1821 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1822 // CHECK10-NEXT: ret void 1823 // 1824 // 1825 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1826 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1827 // CHECK10-NEXT: entry: 1828 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1829 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1830 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1831 // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1832 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1833 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1834 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1835 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 1836 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1837 // CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1838 // CHECK10-NEXT: ret void 1839 // 1840 // 1841 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1842 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1843 // CHECK10-NEXT: entry: 1844 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1845 // CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1846 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1847 // CHECK10-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1848 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1849 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1850 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1851 // CHECK10-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1852 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1853 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1854 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1855 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1856 // CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1857 // CHECK10-NEXT: ret void 1858 // 1859 // 1860 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1861 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1862 // CHECK10-NEXT: entry: 1863 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1864 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1865 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1866 // CHECK10-NEXT: ret void 1867 // 1868 // 1869 // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1870 // CHECK10-SAME: () #[[ATTR6:[0-9]+]] { 1871 // CHECK10-NEXT: entry: 1872 // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) 1873 // CHECK10-NEXT: ret void 1874 // 1875 // 1876 // CHECK11-LABEL: define {{[^@]+}}@main 1877 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 1878 // CHECK11-NEXT: entry: 1879 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1880 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1881 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1882 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1883 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1884 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 1885 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1886 // CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1887 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1888 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1889 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1890 // CHECK11-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 1891 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4 1892 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4 1893 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4 1894 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 1895 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 1896 // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 1897 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1898 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) 1899 // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1900 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 1901 // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 1902 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 1903 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 1904 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 1905 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 1906 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 1907 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1908 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[SIVAR_CASTED]], align 4 1909 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1910 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1911 // CHECK11-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 1912 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 1913 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1914 // CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 1915 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[TMP8]], align 4 1916 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1917 // CHECK11-NEXT: store i8* null, i8** [[TMP9]], align 4 1918 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1919 // CHECK11-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** 1920 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 4 1921 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1922 // CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 1923 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 1924 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1925 // CHECK11-NEXT: store i8* null, i8** [[TMP14]], align 4 1926 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1927 // CHECK11-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** 1928 // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 4 1929 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1930 // CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** 1931 // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 1932 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1933 // CHECK11-NEXT: store i8* null, i8** [[TMP19]], align 4 1934 // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1935 // CHECK11-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** 1936 // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 4 1937 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1938 // CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** 1939 // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 4 1940 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1941 // CHECK11-NEXT: store i8* null, i8** [[TMP24]], align 4 1942 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1943 // CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 1944 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP26]], align 4 1945 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1946 // CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 1947 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[TMP28]], align 4 1948 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1949 // CHECK11-NEXT: store i8* null, i8** [[TMP29]], align 4 1950 // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1951 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1952 // CHECK11-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1953 // CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1954 // CHECK11-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1955 // CHECK11: omp_offload.failed: 1956 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i32 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32 [[TMP4]]) #[[ATTR4:[0-9]+]] 1957 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1958 // CHECK11: omp_offload.cont: 1959 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 1960 // CHECK11-NEXT: store i32 [[TMP34]], i32* [[T_VAR_CASTED1]], align 4 1961 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[T_VAR_CASTED1]], align 4 1962 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1963 // CHECK11-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* 1964 // CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP37]], align 4 1965 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1966 // CHECK11-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 1967 // CHECK11-NEXT: store i32 [[TMP35]], i32* [[TMP39]], align 4 1968 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 1969 // CHECK11-NEXT: store i8* null, i8** [[TMP40]], align 4 1970 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1971 // CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1972 // CHECK11-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1973 // CHECK11-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 1974 // CHECK11-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] 1975 // CHECK11: omp_offload.failed5: 1976 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP35]]) #[[ATTR4]] 1977 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT6]] 1978 // CHECK11: omp_offload.cont6: 1979 // CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1980 // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 1981 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1982 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 1983 // CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1984 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1985 // CHECK11: arraydestroy.body: 1986 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1987 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1988 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1989 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1990 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1991 // CHECK11: arraydestroy.done7: 1992 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1993 // CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 1994 // CHECK11-NEXT: ret i32 [[TMP46]] 1995 // 1996 // 1997 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1998 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1999 // CHECK11-NEXT: entry: 2000 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2001 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2002 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2003 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2004 // CHECK11-NEXT: ret void 2005 // 2006 // 2007 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2008 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2009 // CHECK11-NEXT: entry: 2010 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2011 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2012 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2013 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2014 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2015 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2016 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2017 // CHECK11-NEXT: ret void 2018 // 2019 // 2020 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 2021 // CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 2022 // CHECK11-NEXT: entry: 2023 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2024 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2025 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2026 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2027 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2028 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2029 // CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2030 // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2031 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2032 // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2033 // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2034 // CHECK11-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2035 // CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2036 // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2037 // CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2038 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2039 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 2040 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2041 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2042 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 2043 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2044 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 2045 // CHECK11-NEXT: ret void 2046 // 2047 // 2048 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 2049 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] { 2050 // CHECK11-NEXT: entry: 2051 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2052 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2053 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2054 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2055 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2056 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2057 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2058 // CHECK11-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 2059 // CHECK11-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 2060 // CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2061 // CHECK11-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2062 // CHECK11-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 2063 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2064 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2065 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2066 // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2067 // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2068 // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2069 // CHECK11-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2070 // CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2071 // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2072 // CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2073 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 2074 // CHECK11-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2075 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 2076 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2077 // CHECK11-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 2078 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2079 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 2080 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2081 // CHECK11: omp.arraycpy.body: 2082 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2083 // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2084 // CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2085 // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2086 // CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 2087 // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2088 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2089 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2090 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 2091 // CHECK11: omp.arraycpy.done3: 2092 // CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 2093 // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 2094 // CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] 2095 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2096 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 0 2097 // CHECK11-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 2098 // CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2099 // CHECK11-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* 2100 // CHECK11-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 2101 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 4, i1 false) 2102 // CHECK11-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 2103 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] 2104 // CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2105 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 2106 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2107 // CHECK11: arraydestroy.body: 2108 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2109 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2110 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2111 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 2112 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 2113 // CHECK11: arraydestroy.done8: 2114 // CHECK11-NEXT: ret void 2115 // 2116 // 2117 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2118 // CHECK11-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2119 // CHECK11-NEXT: entry: 2120 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2121 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2122 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2123 // CHECK11-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 2124 // CHECK11-NEXT: ret void 2125 // 2126 // 2127 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2128 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2129 // CHECK11-NEXT: entry: 2130 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2131 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2132 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2133 // CHECK11-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2134 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2135 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2136 // CHECK11-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2137 // CHECK11-NEXT: ret void 2138 // 2139 // 2140 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2141 // CHECK11-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2142 // CHECK11-NEXT: entry: 2143 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2144 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2145 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2146 // CHECK11-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 2147 // CHECK11-NEXT: ret void 2148 // 2149 // 2150 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2151 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2152 // CHECK11-NEXT: entry: 2153 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2154 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2155 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2156 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2157 // CHECK11-NEXT: ret void 2158 // 2159 // 2160 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 2161 // CHECK11-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] { 2162 // CHECK11-NEXT: entry: 2163 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2164 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2165 // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2166 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2167 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 2168 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2169 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2170 // CHECK11-NEXT: ret void 2171 // 2172 // 2173 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 2174 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { 2175 // CHECK11-NEXT: entry: 2176 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2177 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2178 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2179 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2180 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2181 // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2182 // CHECK11-NEXT: ret void 2183 // 2184 // 2185 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2186 // CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { 2187 // CHECK11-NEXT: entry: 2188 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2189 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2190 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 2191 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 2192 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 2193 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 2194 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2195 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2196 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2197 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 2198 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 2199 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 2200 // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2201 // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 128 2202 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2203 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2204 // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2205 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2206 // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2207 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2208 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 2209 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2210 // CHECK11-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 2211 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4 2212 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2213 // CHECK11-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 2214 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4 2215 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2216 // CHECK11-NEXT: store i8* null, i8** [[TMP5]], align 4 2217 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2218 // CHECK11-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 2219 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 4 2220 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2221 // CHECK11-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** 2222 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 4 2223 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2224 // CHECK11-NEXT: store i8* null, i8** [[TMP10]], align 4 2225 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2226 // CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** 2227 // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 4 2228 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2229 // CHECK11-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** 2230 // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 4 2231 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2232 // CHECK11-NEXT: store i8* null, i8** [[TMP15]], align 4 2233 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2234 // CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** 2235 // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 4 2236 // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2237 // CHECK11-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** 2238 // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 4 2239 // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2240 // CHECK11-NEXT: store i8* null, i8** [[TMP20]], align 4 2241 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2242 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2243 // CHECK11-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2244 // CHECK11-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 2245 // CHECK11-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2246 // CHECK11: omp_offload.failed: 2247 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] 2248 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 2249 // CHECK11: omp_offload.cont: 2250 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 2251 // CHECK11-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** 2252 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 4 2253 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 2254 // CHECK11-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** 2255 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 4 2256 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 2257 // CHECK11-NEXT: store i8* null, i8** [[TMP29]], align 4 2258 // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 2259 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 2260 // CHECK11-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2261 // CHECK11-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 2262 // CHECK11-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] 2263 // CHECK11: omp_offload.failed4: 2264 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] 2265 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT5]] 2266 // CHECK11: omp_offload.cont5: 2267 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 2268 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2269 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2270 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2271 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2272 // CHECK11: arraydestroy.body: 2273 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2274 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2275 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2276 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2277 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 2278 // CHECK11: arraydestroy.done6: 2279 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2280 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 2281 // CHECK11-NEXT: ret i32 [[TMP35]] 2282 // 2283 // 2284 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2285 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2286 // CHECK11-NEXT: entry: 2287 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2288 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2289 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2290 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2291 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 2292 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2293 // CHECK11-NEXT: store float [[CONV]], float* [[F]], align 4 2294 // CHECK11-NEXT: ret void 2295 // 2296 // 2297 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2298 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2299 // CHECK11-NEXT: entry: 2300 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2301 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2302 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2303 // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2304 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2305 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2306 // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2307 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 2308 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2309 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2310 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 2311 // CHECK11-NEXT: ret void 2312 // 2313 // 2314 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StC2Ev 2315 // CHECK11-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2316 // CHECK11-NEXT: entry: 2317 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2318 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2319 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2320 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 2321 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 2322 // CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 2323 // CHECK11-NEXT: store i32 0, i32* [[B]], align 4 2324 // CHECK11-NEXT: ret void 2325 // 2326 // 2327 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 2328 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2329 // CHECK11-NEXT: entry: 2330 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2331 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2332 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2333 // CHECK11-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2334 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2335 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2336 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2337 // CHECK11-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 2338 // CHECK11-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 2339 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2340 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2341 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 2342 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 2343 // CHECK11-NEXT: store float [[ADD]], float* [[F]], align 4 2344 // CHECK11-NEXT: ret void 2345 // 2346 // 2347 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StD2Ev 2348 // CHECK11-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2349 // CHECK11-NEXT: entry: 2350 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2351 // CHECK11-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2352 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2353 // CHECK11-NEXT: ret void 2354 // 2355 // 2356 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2357 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2358 // CHECK11-NEXT: entry: 2359 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2360 // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2361 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2362 // CHECK11-NEXT: ret void 2363 // 2364 // 2365 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2366 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2367 // CHECK11-NEXT: entry: 2368 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2369 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2370 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2371 // CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 2372 // CHECK11-NEXT: ret void 2373 // 2374 // 2375 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2376 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2377 // CHECK11-NEXT: entry: 2378 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2379 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2380 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2381 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2382 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2383 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2384 // CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 2385 // CHECK11-NEXT: ret void 2386 // 2387 // 2388 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 2389 // CHECK11-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 2390 // CHECK11-NEXT: entry: 2391 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 2392 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2393 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 2394 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 2395 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 2396 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 2397 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2398 // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2399 // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 2400 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 2401 // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2402 // CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2403 // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 2404 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 2405 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 2406 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) 2407 // CHECK11-NEXT: ret void 2408 // 2409 // 2410 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 2411 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 2412 // CHECK11-NEXT: entry: 2413 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2414 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2415 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2416 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 2417 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 2418 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 2419 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 2420 // CHECK11-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 2421 // CHECK11-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 2422 // CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2423 // CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 2424 // CHECK11-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 2425 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2426 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2427 // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2428 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 2429 // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2430 // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 2431 // CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2432 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 2433 // CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 2434 // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 2435 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 2436 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 2437 // CHECK11-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 2438 // CHECK11-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2439 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i32 8, i1 false) 2440 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2441 // CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 2442 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2443 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 2444 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2445 // CHECK11: omp.arraycpy.body: 2446 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2447 // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2448 // CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2449 // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2450 // CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 2451 // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2452 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2453 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 2454 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2455 // CHECK11: omp.arraycpy.done4: 2456 // CHECK11-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 2457 // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 2458 // CHECK11-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 2459 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 2460 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 2461 // CHECK11-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 2462 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2463 // CHECK11-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 2464 // CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 2465 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 4, i1 false) 2466 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 2467 // CHECK11-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2468 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 2469 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2470 // CHECK11: arraydestroy.body: 2471 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2472 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2473 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2474 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 2475 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 2476 // CHECK11: arraydestroy.done9: 2477 // CHECK11-NEXT: ret void 2478 // 2479 // 2480 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 2481 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2482 // CHECK11-NEXT: entry: 2483 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2484 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 2485 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2486 // CHECK11-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 2487 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2488 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 2489 // CHECK11-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2490 // CHECK11-NEXT: ret void 2491 // 2492 // 2493 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2494 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2495 // CHECK11-NEXT: entry: 2496 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2497 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2498 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2499 // CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2500 // CHECK11-NEXT: ret void 2501 // 2502 // 2503 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 2504 // CHECK11-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 2505 // CHECK11-NEXT: entry: 2506 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 2507 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 2508 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 2509 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 2510 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 2511 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 2512 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) 2513 // CHECK11-NEXT: ret void 2514 // 2515 // 2516 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 2517 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 2518 // CHECK11-NEXT: entry: 2519 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2520 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2521 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 2522 // CHECK11-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 2523 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2524 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2525 // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 2526 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 2527 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 2528 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 2529 // CHECK11-NEXT: ret void 2530 // 2531 // 2532 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2533 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2534 // CHECK11-NEXT: entry: 2535 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2536 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2537 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2538 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2539 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 2540 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2541 // CHECK11-NEXT: ret void 2542 // 2543 // 2544 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2545 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2546 // CHECK11-NEXT: entry: 2547 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2548 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2549 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2550 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2551 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2552 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2553 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2554 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 2555 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2556 // CHECK11-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2557 // CHECK11-NEXT: ret void 2558 // 2559 // 2560 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 2561 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2562 // CHECK11-NEXT: entry: 2563 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2564 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 2565 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2566 // CHECK11-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 2567 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2568 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2569 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 2570 // CHECK11-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 2571 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 2572 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2573 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2574 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 2575 // CHECK11-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2576 // CHECK11-NEXT: ret void 2577 // 2578 // 2579 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2580 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2581 // CHECK11-NEXT: entry: 2582 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 2583 // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 2584 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 2585 // CHECK11-NEXT: ret void 2586 // 2587 // 2588 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2589 // CHECK11-SAME: () #[[ATTR6:[0-9]+]] { 2590 // CHECK11-NEXT: entry: 2591 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 2592 // CHECK11-NEXT: ret void 2593 // 2594 // 2595 // CHECK12-LABEL: define {{[^@]+}}@main 2596 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 2597 // CHECK12-NEXT: entry: 2598 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2599 // CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2600 // CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2601 // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2602 // CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2603 // CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 2604 // CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2605 // CHECK12-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2606 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2607 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2608 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2609 // CHECK12-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 2610 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x i8*], align 4 2611 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x i8*], align 4 2612 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x i8*], align 4 2613 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 2614 // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 2615 // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 2616 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2617 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) 2618 // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2619 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 2620 // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 2621 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 2622 // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 2623 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 2624 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 2625 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2626 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 2627 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[SIVAR_CASTED]], align 4 2628 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2629 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2630 // CHECK12-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 2631 // CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 2632 // CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2633 // CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 2634 // CHECK12-NEXT: store i32 [[TMP2]], i32* [[TMP8]], align 4 2635 // CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2636 // CHECK12-NEXT: store i8* null, i8** [[TMP9]], align 4 2637 // CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2638 // CHECK12-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to [2 x i32]** 2639 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP11]], align 4 2640 // CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2641 // CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** 2642 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 2643 // CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2644 // CHECK12-NEXT: store i8* null, i8** [[TMP14]], align 4 2645 // CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2646 // CHECK12-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [2 x %struct.S]** 2647 // CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP16]], align 4 2648 // CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2649 // CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S]** 2650 // CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP18]], align 4 2651 // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2652 // CHECK12-NEXT: store i8* null, i8** [[TMP19]], align 4 2653 // CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2654 // CHECK12-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.S** 2655 // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP21]], align 4 2656 // CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2657 // CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S** 2658 // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[TMP23]], align 4 2659 // CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2660 // CHECK12-NEXT: store i8* null, i8** [[TMP24]], align 4 2661 // CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2662 // CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 2663 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP26]], align 4 2664 // CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2665 // CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 2666 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[TMP28]], align 4 2667 // CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2668 // CHECK12-NEXT: store i8* null, i8** [[TMP29]], align 4 2669 // CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2670 // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2671 // CHECK12-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, i32 5, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2672 // CHECK12-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 2673 // CHECK12-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2674 // CHECK12: omp_offload.failed: 2675 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i32 [[TMP2]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32 [[TMP4]]) #[[ATTR4:[0-9]+]] 2676 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2677 // CHECK12: omp_offload.cont: 2678 // CHECK12-NEXT: [[TMP34:%.*]] = load i32, i32* [[T_VAR]], align 4 2679 // CHECK12-NEXT: store i32 [[TMP34]], i32* [[T_VAR_CASTED1]], align 4 2680 // CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[T_VAR_CASTED1]], align 4 2681 // CHECK12-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 2682 // CHECK12-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* 2683 // CHECK12-NEXT: store i32 [[TMP35]], i32* [[TMP37]], align 4 2684 // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 2685 // CHECK12-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 2686 // CHECK12-NEXT: store i32 [[TMP35]], i32* [[TMP39]], align 4 2687 // CHECK12-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 2688 // CHECK12-NEXT: store i8* null, i8** [[TMP40]], align 4 2689 // CHECK12-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 2690 // CHECK12-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 2691 // CHECK12-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, i32 1, i8** [[TMP41]], i8** [[TMP42]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2692 // CHECK12-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 2693 // CHECK12-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] 2694 // CHECK12: omp_offload.failed5: 2695 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP35]]) #[[ATTR4]] 2696 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT6]] 2697 // CHECK12: omp_offload.cont6: 2698 // CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 2699 // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2700 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2701 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2702 // CHECK12-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2703 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2704 // CHECK12: arraydestroy.body: 2705 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP45]], [[OMP_OFFLOAD_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2706 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2707 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2708 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2709 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 2710 // CHECK12: arraydestroy.done7: 2711 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2712 // CHECK12-NEXT: [[TMP46:%.*]] = load i32, i32* [[RETVAL]], align 4 2713 // CHECK12-NEXT: ret i32 [[TMP46]] 2714 // 2715 // 2716 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2717 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2718 // CHECK12-NEXT: entry: 2719 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2720 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2721 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2722 // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2723 // CHECK12-NEXT: ret void 2724 // 2725 // 2726 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2727 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2728 // CHECK12-NEXT: entry: 2729 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2730 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2731 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2732 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2733 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2734 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2735 // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2736 // CHECK12-NEXT: ret void 2737 // 2738 // 2739 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 2740 // CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 2741 // CHECK12-NEXT: entry: 2742 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2743 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2744 // CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2745 // CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2746 // CHECK12-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2747 // CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2748 // CHECK12-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 2749 // CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2750 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2751 // CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2752 // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2753 // CHECK12-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2754 // CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2755 // CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2756 // CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2757 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2758 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[T_VAR_CASTED]], align 4 2759 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2760 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 2761 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[SIVAR_CASTED]], align 4 2762 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 2763 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[TMP0]], i32 [[TMP4]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP2]], i32 [[TMP6]]) 2764 // CHECK12-NEXT: ret void 2765 // 2766 // 2767 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 2768 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] { 2769 // CHECK12-NEXT: entry: 2770 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2771 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2772 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 2773 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2774 // CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 2775 // CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 2776 // CHECK12-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 2777 // CHECK12-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 2778 // CHECK12-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 2779 // CHECK12-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2780 // CHECK12-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2781 // CHECK12-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 2782 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2783 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2784 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 2785 // CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2786 // CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2787 // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 2788 // CHECK12-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 2789 // CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 2790 // CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 2791 // CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 2792 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 2793 // CHECK12-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2794 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 2795 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2796 // CHECK12-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 2797 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 2798 // CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 2799 // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2800 // CHECK12: omp.arraycpy.body: 2801 // CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2802 // CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2803 // CHECK12-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2804 // CHECK12-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2805 // CHECK12-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 2806 // CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2807 // CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2808 // CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2809 // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 2810 // CHECK12: omp.arraycpy.done3: 2811 // CHECK12-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 2812 // CHECK12-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 2813 // CHECK12-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] 2814 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2815 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 0 2816 // CHECK12-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 2817 // CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2818 // CHECK12-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* 2819 // CHECK12-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 2820 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 4, i1 false) 2821 // CHECK12-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 2822 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] 2823 // CHECK12-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 2824 // CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 2825 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2826 // CHECK12: arraydestroy.body: 2827 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2828 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2829 // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2830 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 2831 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 2832 // CHECK12: arraydestroy.done8: 2833 // CHECK12-NEXT: ret void 2834 // 2835 // 2836 // CHECK12-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2837 // CHECK12-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2838 // CHECK12-NEXT: entry: 2839 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2840 // CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2841 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2842 // CHECK12-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 2843 // CHECK12-NEXT: ret void 2844 // 2845 // 2846 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2847 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2848 // CHECK12-NEXT: entry: 2849 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2850 // CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 2851 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2852 // CHECK12-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 2853 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2854 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 2855 // CHECK12-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2856 // CHECK12-NEXT: ret void 2857 // 2858 // 2859 // CHECK12-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2860 // CHECK12-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2861 // CHECK12-NEXT: entry: 2862 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 2863 // CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 2864 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 2865 // CHECK12-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 2866 // CHECK12-NEXT: ret void 2867 // 2868 // 2869 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2870 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2871 // CHECK12-NEXT: entry: 2872 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 2873 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 2874 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 2875 // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2876 // CHECK12-NEXT: ret void 2877 // 2878 // 2879 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 2880 // CHECK12-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] { 2881 // CHECK12-NEXT: entry: 2882 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2883 // CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 2884 // CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2885 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 2886 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[T_VAR_CASTED]], align 4 2887 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 2888 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2889 // CHECK12-NEXT: ret void 2890 // 2891 // 2892 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 2893 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { 2894 // CHECK12-NEXT: entry: 2895 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2896 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2897 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 2898 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2899 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2900 // CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 2901 // CHECK12-NEXT: ret void 2902 // 2903 // 2904 // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2905 // CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { 2906 // CHECK12-NEXT: entry: 2907 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2908 // CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2909 // CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 2910 // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 2911 // CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 2912 // CHECK12-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 2913 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2914 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2915 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2916 // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS1:%.*]] = alloca [1 x i8*], align 4 2917 // CHECK12-NEXT: [[DOTOFFLOAD_PTRS2:%.*]] = alloca [1 x i8*], align 4 2918 // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS3:%.*]] = alloca [1 x i8*], align 4 2919 // CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2920 // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 128 2921 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2922 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 2923 // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2924 // CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2925 // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 2926 // CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2927 // CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 2928 // CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2929 // CHECK12-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32** 2930 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[TMP2]], align 4 2931 // CHECK12-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2932 // CHECK12-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32** 2933 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[TMP4]], align 4 2934 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2935 // CHECK12-NEXT: store i8* null, i8** [[TMP5]], align 4 2936 // CHECK12-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2937 // CHECK12-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to [2 x i32]** 2938 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP7]], align 4 2939 // CHECK12-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2940 // CHECK12-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to [2 x i32]** 2941 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP9]], align 4 2942 // CHECK12-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2943 // CHECK12-NEXT: store i8* null, i8** [[TMP10]], align 4 2944 // CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2945 // CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to [2 x %struct.S.0]** 2946 // CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP12]], align 4 2947 // CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2948 // CHECK12-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to [2 x %struct.S.0]** 2949 // CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP14]], align 4 2950 // CHECK12-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2951 // CHECK12-NEXT: store i8* null, i8** [[TMP15]], align 4 2952 // CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2953 // CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to %struct.S.0** 2954 // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP17]], align 4 2955 // CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2956 // CHECK12-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to %struct.S.0** 2957 // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP19]], align 4 2958 // CHECK12-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2959 // CHECK12-NEXT: store i8* null, i8** [[TMP20]], align 4 2960 // CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2961 // CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2962 // CHECK12-NEXT: [[TMP23:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, i32 4, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2963 // CHECK12-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0 2964 // CHECK12-NEXT: br i1 [[TMP24]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2965 // CHECK12: omp_offload.failed: 2966 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) #[[ATTR4]] 2967 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] 2968 // CHECK12: omp_offload.cont: 2969 // CHECK12-NEXT: [[TMP25:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 2970 // CHECK12-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32** 2971 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[TMP26]], align 4 2972 // CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 2973 // CHECK12-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32** 2974 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[TMP28]], align 4 2975 // CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS3]], i32 0, i32 0 2976 // CHECK12-NEXT: store i8* null, i8** [[TMP29]], align 4 2977 // CHECK12-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 2978 // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 2979 // CHECK12-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, i32 1, i8** [[TMP30]], i8** [[TMP31]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2980 // CHECK12-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 2981 // CHECK12-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED4:%.*]], label [[OMP_OFFLOAD_CONT5:%.*]] 2982 // CHECK12: omp_offload.failed4: 2983 // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32* [[T_VAR]]) #[[ATTR4]] 2984 // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT5]] 2985 // CHECK12: omp_offload.cont5: 2986 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 2987 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2988 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2989 // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 2990 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2991 // CHECK12: arraydestroy.body: 2992 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP34]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2993 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 2994 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2995 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2996 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 2997 // CHECK12: arraydestroy.done6: 2998 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2999 // CHECK12-NEXT: [[TMP35:%.*]] = load i32, i32* [[RETVAL]], align 4 3000 // CHECK12-NEXT: ret i32 [[TMP35]] 3001 // 3002 // 3003 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3004 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3005 // CHECK12-NEXT: entry: 3006 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3007 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3008 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3009 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3010 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 3011 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3012 // CHECK12-NEXT: store float [[CONV]], float* [[F]], align 4 3013 // CHECK12-NEXT: ret void 3014 // 3015 // 3016 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3017 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3018 // CHECK12-NEXT: entry: 3019 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3020 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3021 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3022 // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3023 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3024 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3025 // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3026 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 3027 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3028 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3029 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 3030 // CHECK12-NEXT: ret void 3031 // 3032 // 3033 // CHECK12-LABEL: define {{[^@]+}}@_ZN2StC2Ev 3034 // CHECK12-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3035 // CHECK12-NEXT: entry: 3036 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 3037 // CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 3038 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 3039 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 3040 // CHECK12-NEXT: store i32 0, i32* [[A]], align 4 3041 // CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 3042 // CHECK12-NEXT: store i32 0, i32* [[B]], align 4 3043 // CHECK12-NEXT: ret void 3044 // 3045 // 3046 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 3047 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3048 // CHECK12-NEXT: entry: 3049 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3050 // CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 3051 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3052 // CHECK12-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 3053 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3054 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3055 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 3056 // CHECK12-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 3057 // CHECK12-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 3058 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 3059 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3060 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 3061 // CHECK12-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 3062 // CHECK12-NEXT: store float [[ADD]], float* [[F]], align 4 3063 // CHECK12-NEXT: ret void 3064 // 3065 // 3066 // CHECK12-LABEL: define {{[^@]+}}@_ZN2StD2Ev 3067 // CHECK12-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3068 // CHECK12-NEXT: entry: 3069 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 3070 // CHECK12-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 3071 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 3072 // CHECK12-NEXT: ret void 3073 // 3074 // 3075 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3076 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3077 // CHECK12-NEXT: entry: 3078 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 3079 // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 3080 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 3081 // CHECK12-NEXT: ret void 3082 // 3083 // 3084 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3085 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3086 // CHECK12-NEXT: entry: 3087 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3088 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3089 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3090 // CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3091 // CHECK12-NEXT: ret void 3092 // 3093 // 3094 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3095 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3096 // CHECK12-NEXT: entry: 3097 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3098 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3099 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3100 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3101 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3102 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3103 // CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 3104 // CHECK12-NEXT: ret void 3105 // 3106 // 3107 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 3108 // CHECK12-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 3109 // CHECK12-NEXT: entry: 3110 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 3111 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3112 // CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 3113 // CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 3114 // CHECK12-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 3115 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 3116 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3117 // CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3118 // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 3119 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 3120 // CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3121 // CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3122 // CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 3123 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 128 3124 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 3125 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), [2 x i32]* [[TMP1]], i32* [[T_VAR1]], [2 x %struct.S.0]* [[TMP2]], %struct.S.0* [[TMP3]]) 3126 // CHECK12-NEXT: ret void 3127 // 3128 // 3129 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 3130 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 3131 // CHECK12-NEXT: entry: 3132 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3133 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3134 // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 3135 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 3136 // CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 3137 // CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 3138 // CHECK12-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 3139 // CHECK12-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 3140 // CHECK12-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 3141 // CHECK12-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3142 // CHECK12-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 3143 // CHECK12-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3144 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3145 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3146 // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 3147 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 3148 // CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3149 // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 3150 // CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 3151 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 3152 // CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 3153 // CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 3154 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 3155 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 3156 // CHECK12-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 3157 // CHECK12-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 3158 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i32 8, i1 false) 3159 // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3160 // CHECK12-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 3161 // CHECK12-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 3162 // CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 3163 // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3164 // CHECK12: omp.arraycpy.body: 3165 // CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3166 // CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3167 // CHECK12-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3168 // CHECK12-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 3169 // CHECK12-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 3170 // CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3171 // CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3172 // CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 3173 // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3174 // CHECK12: omp.arraycpy.done4: 3175 // CHECK12-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3176 // CHECK12-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 3177 // CHECK12-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 3178 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 3179 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 3180 // CHECK12-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 3181 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3182 // CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 3183 // CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 3184 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 4, i1 false) 3185 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 3186 // CHECK12-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3187 // CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 3188 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3189 // CHECK12: arraydestroy.body: 3190 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3191 // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 3192 // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 3193 // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 3194 // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 3195 // CHECK12: arraydestroy.done9: 3196 // CHECK12-NEXT: ret void 3197 // 3198 // 3199 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 3200 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3201 // CHECK12-NEXT: entry: 3202 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3203 // CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 3204 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3205 // CHECK12-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 3206 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3207 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 3208 // CHECK12-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 3209 // CHECK12-NEXT: ret void 3210 // 3211 // 3212 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3213 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3214 // CHECK12-NEXT: entry: 3215 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3216 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3217 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3218 // CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 3219 // CHECK12-NEXT: ret void 3220 // 3221 // 3222 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 3223 // CHECK12-SAME: (i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 3224 // CHECK12-NEXT: entry: 3225 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 3226 // CHECK12-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 3227 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 3228 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 3229 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 3230 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 3231 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[T_VAR1]]) 3232 // CHECK12-NEXT: ret void 3233 // 3234 // 3235 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 3236 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 3237 // CHECK12-NEXT: entry: 3238 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3239 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3240 // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 3241 // CHECK12-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 3242 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3243 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3244 // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 3245 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 3246 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 3247 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 3248 // CHECK12-NEXT: ret void 3249 // 3250 // 3251 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3252 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3253 // CHECK12-NEXT: entry: 3254 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3255 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3256 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3257 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3258 // CHECK12-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 3259 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3260 // CHECK12-NEXT: ret void 3261 // 3262 // 3263 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3264 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3265 // CHECK12-NEXT: entry: 3266 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3267 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3268 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3269 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3270 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3271 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3272 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3273 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 3274 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3275 // CHECK12-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3276 // CHECK12-NEXT: ret void 3277 // 3278 // 3279 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 3280 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3281 // CHECK12-NEXT: entry: 3282 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3283 // CHECK12-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 3284 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3285 // CHECK12-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 3286 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3287 // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3288 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 3289 // CHECK12-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 3290 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 3291 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 3292 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3293 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 3294 // CHECK12-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3295 // CHECK12-NEXT: ret void 3296 // 3297 // 3298 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3299 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3300 // CHECK12-NEXT: entry: 3301 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 3302 // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 3303 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 3304 // CHECK12-NEXT: ret void 3305 // 3306 // 3307 // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3308 // CHECK12-SAME: () #[[ATTR6:[0-9]+]] { 3309 // CHECK12-NEXT: entry: 3310 // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) 3311 // CHECK12-NEXT: ret void 3312 // 3313 // 3314 // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg 3315 // CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 3316 // CHECK17-NEXT: entry: 3317 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3318 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 3319 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3320 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 3321 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3322 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3323 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3324 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 3325 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 8 3326 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 8 3327 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 8 3328 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 8 3329 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3330 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 3331 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3332 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 3333 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3334 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 3335 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3336 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 3337 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3338 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 3339 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 3340 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 3341 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 3342 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 3343 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 3344 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 3345 // CHECK17-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 3346 // CHECK17-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 3347 // CHECK17-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 3348 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 3349 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 3350 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 3351 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 3352 // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 3353 // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 3354 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3355 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** 3356 // CHECK17-NEXT: store float* [[TMP8]], float** [[TMP16]], align 8 3357 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3358 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to float** 3359 // CHECK17-NEXT: store float* [[TMP8]], float** [[TMP18]], align 8 3360 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3361 // CHECK17-NEXT: store i64 0, i64* [[TMP19]], align 8 3362 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3363 // CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 3364 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3365 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** 3366 // CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP22]], align 8 3367 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3368 // CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to %struct.St** 3369 // CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP24]], align 8 3370 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 3371 // CHECK17-NEXT: store i64 0, i64* [[TMP25]], align 8 3372 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3373 // CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 3374 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3375 // CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 3376 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP28]], align 8 3377 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3378 // CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 3379 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP30]], align 8 3380 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 3381 // CHECK17-NEXT: store i64 8, i64* [[TMP31]], align 8 3382 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3383 // CHECK17-NEXT: store i8* null, i8** [[TMP32]], align 8 3384 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3385 // CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to ppc_fp128** 3386 // CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP34]], align 8 3387 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3388 // CHECK17-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to ppc_fp128** 3389 // CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP36]], align 8 3390 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3391 // CHECK17-NEXT: store i64 0, i64* [[TMP37]], align 8 3392 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 3393 // CHECK17-NEXT: store i8* null, i8** [[TMP38]], align 8 3394 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3395 // CHECK17-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i64* 3396 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP40]], align 8 3397 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3398 // CHECK17-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64* 3399 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP42]], align 8 3400 // CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3401 // CHECK17-NEXT: store i64 8, i64* [[TMP43]], align 8 3402 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 3403 // CHECK17-NEXT: store i8* null, i8** [[TMP44]], align 8 3404 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 3405 // CHECK17-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* 3406 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP46]], align 8 3407 // CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 3408 // CHECK17-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* 3409 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP48]], align 8 3410 // CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 3411 // CHECK17-NEXT: store i64 8, i64* [[TMP49]], align 8 3412 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 3413 // CHECK17-NEXT: store i8* null, i8** [[TMP50]], align 8 3414 // CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 3415 // CHECK17-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** 3416 // CHECK17-NEXT: store double* [[VLA]], double** [[TMP52]], align 8 3417 // CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 3418 // CHECK17-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** 3419 // CHECK17-NEXT: store double* [[VLA]], double** [[TMP54]], align 8 3420 // CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 3421 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP55]], align 8 3422 // CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 3423 // CHECK17-NEXT: store i8* null, i8** [[TMP56]], align 8 3424 // CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 3425 // CHECK17-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64* 3426 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP58]], align 8 3427 // CHECK17-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 3428 // CHECK17-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i64* 3429 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP60]], align 8 3430 // CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3431 // CHECK17-NEXT: store i64 4, i64* [[TMP61]], align 8 3432 // CHECK17-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 3433 // CHECK17-NEXT: store i8* null, i8** [[TMP62]], align 8 3434 // CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3435 // CHECK17-NEXT: [[TMP64:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3436 // CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3437 // CHECK17-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, i32 8, i8** [[TMP63]], i8** [[TMP64]], i64* [[TMP65]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3438 // CHECK17-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 3439 // CHECK17-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3440 // CHECK17: omp_offload.failed: 3441 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(float* [[TMP8]], %struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 3442 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 3443 // CHECK17: omp_offload.cont: 3444 // CHECK17-NEXT: [[TMP68:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3445 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP68]]) 3446 // CHECK17-NEXT: ret void 3447 // 3448 // 3449 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152 3450 // CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 3451 // CHECK17-NEXT: entry: 3452 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3453 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 3454 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3455 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 3456 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 3457 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 3458 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 3459 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 3460 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3461 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 3462 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3463 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 3464 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 3465 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 3466 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 3467 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 3468 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3469 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 3470 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 3471 // CHECK17-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 3472 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 3473 // CHECK17-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 3474 // CHECK17-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 3475 // CHECK17-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 8 3476 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, ppc_fp128*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[CONV]], i64 [[TMP0]], ppc_fp128* [[TMP5]], float* [[TMP6]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]]) 3477 // CHECK17-NEXT: ret void 3478 // 3479 // 3480 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 3481 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { 3482 // CHECK17-NEXT: entry: 3483 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3484 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3485 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 3486 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 3487 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3488 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 3489 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3490 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 3491 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 3492 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 3493 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3494 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3495 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3496 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3497 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3498 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 3499 // CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 3500 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3501 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 3502 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3503 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 3504 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 3505 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 3506 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 3507 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3508 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 3509 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 3510 // CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 3511 // CHECK17-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() 3512 // CHECK17-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8 3513 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 3514 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 3515 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 3516 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 3517 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 3518 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 3519 // CHECK17-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* 3520 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* 3521 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false) 3522 // CHECK17-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 3523 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0 3524 // CHECK17-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 3525 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 3526 // CHECK17-NEXT: [[TMP14:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 3527 // CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 signext [[TMP13]], ppc_fp128* [[TMP14]]) 3528 // CHECK17-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3529 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 3530 // CHECK17-NEXT: ret void 3531 // 3532 // 3533 // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg 3534 // CHECK17-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 3535 // CHECK17-NEXT: entry: 3536 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 3537 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 3538 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3539 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 3540 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3541 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3542 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3543 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 3544 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 8 3545 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 8 3546 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 8 3547 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 3548 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 3549 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 3550 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3551 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 3552 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 3553 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3554 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 3555 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3556 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 3557 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3558 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 3559 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 3560 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 3561 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 3562 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 3563 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 3564 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 3565 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 3566 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 3567 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 3568 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 3569 // CHECK17-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 3570 // CHECK17-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 3571 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 3572 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 3573 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 3574 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 3575 // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 3576 // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 3577 // CHECK17-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 3578 // CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 3579 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr i32, i32* [[B2]], i32 1 3580 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i32* [[A3]] to i8* 3581 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i32* [[TMP15]] to i8* 3582 // CHECK17-NEXT: [[TMP18:%.*]] = ptrtoint i8* [[TMP17]] to i64 3583 // CHECK17-NEXT: [[TMP19:%.*]] = ptrtoint i8* [[TMP16]] to i64 3584 // CHECK17-NEXT: [[TMP20:%.*]] = sub i64 [[TMP18]], [[TMP19]] 3585 // CHECK17-NEXT: [[TMP21:%.*]] = sdiv exact i64 [[TMP20]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) 3586 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3587 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** 3588 // CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP23]], align 8 3589 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3590 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.St** 3591 // CHECK17-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP25]], align 8 3592 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3593 // CHECK17-NEXT: store i64 0, i64* [[TMP26]], align 8 3594 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3595 // CHECK17-NEXT: store i8* null, i8** [[TMP27]], align 8 3596 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3597 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 3598 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP29]], align 8 3599 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3600 // CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 3601 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP31]], align 8 3602 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 3603 // CHECK17-NEXT: store i64 8, i64* [[TMP32]], align 8 3604 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3605 // CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 3606 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3607 // CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to ppc_fp128** 3608 // CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP35]], align 8 3609 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3610 // CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to ppc_fp128** 3611 // CHECK17-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP37]], align 8 3612 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 3613 // CHECK17-NEXT: store i64 0, i64* [[TMP38]], align 8 3614 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3615 // CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 3616 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3617 // CHECK17-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* 3618 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP41]], align 8 3619 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3620 // CHECK17-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* 3621 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP43]], align 8 3622 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3623 // CHECK17-NEXT: store i64 8, i64* [[TMP44]], align 8 3624 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 3625 // CHECK17-NEXT: store i8* null, i8** [[TMP45]], align 8 3626 // CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3627 // CHECK17-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i64* 3628 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP47]], align 8 3629 // CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3630 // CHECK17-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i64* 3631 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP49]], align 8 3632 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3633 // CHECK17-NEXT: store i64 8, i64* [[TMP50]], align 8 3634 // CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 3635 // CHECK17-NEXT: store i8* null, i8** [[TMP51]], align 8 3636 // CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 3637 // CHECK17-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** 3638 // CHECK17-NEXT: store double* [[VLA]], double** [[TMP53]], align 8 3639 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 3640 // CHECK17-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double** 3641 // CHECK17-NEXT: store double* [[VLA]], double** [[TMP55]], align 8 3642 // CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 3643 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP56]], align 8 3644 // CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 3645 // CHECK17-NEXT: store i8* null, i8** [[TMP57]], align 8 3646 // CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 3647 // CHECK17-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to %struct.St** 3648 // CHECK17-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP59]], align 8 3649 // CHECK17-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 3650 // CHECK17-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32** 3651 // CHECK17-NEXT: store i32* [[A3]], i32** [[TMP61]], align 8 3652 // CHECK17-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 3653 // CHECK17-NEXT: store i64 [[TMP21]], i64* [[TMP62]], align 8 3654 // CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 3655 // CHECK17-NEXT: store i8* null, i8** [[TMP63]], align 8 3656 // CHECK17-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 3657 // CHECK17-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to %struct.St** 3658 // CHECK17-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP65]], align 8 3659 // CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 3660 // CHECK17-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32** 3661 // CHECK17-NEXT: store i32* [[B2]], i32** [[TMP67]], align 8 3662 // CHECK17-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3663 // CHECK17-NEXT: store i64 4, i64* [[TMP68]], align 8 3664 // CHECK17-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 3665 // CHECK17-NEXT: store i8* null, i8** [[TMP69]], align 8 3666 // CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 3667 // CHECK17-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to %struct.St** 3668 // CHECK17-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP71]], align 8 3669 // CHECK17-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 3670 // CHECK17-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32** 3671 // CHECK17-NEXT: store i32* [[A3]], i32** [[TMP73]], align 8 3672 // CHECK17-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 3673 // CHECK17-NEXT: store i64 4, i64* [[TMP74]], align 8 3674 // CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 3675 // CHECK17-NEXT: store i8* null, i8** [[TMP75]], align 8 3676 // CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 3677 // CHECK17-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* 3678 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP77]], align 8 3679 // CHECK17-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 3680 // CHECK17-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* 3681 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP79]], align 8 3682 // CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 3683 // CHECK17-NEXT: store i64 4, i64* [[TMP80]], align 8 3684 // CHECK17-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9 3685 // CHECK17-NEXT: store i8* null, i8** [[TMP81]], align 8 3686 // CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3687 // CHECK17-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3688 // CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3689 // CHECK17-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, i32 10, i8** [[TMP82]], i8** [[TMP83]], i64* [[TMP84]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3690 // CHECK17-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 3691 // CHECK17-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3692 // CHECK17: omp_offload.failed: 3693 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(%struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], %struct.St* [[THIS1]], i64 [[TMP12]]) #[[ATTR4]] 3694 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 3695 // CHECK17: omp_offload.cont: 3696 // CHECK17-NEXT: [[TMP87:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3697 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP87]]) 3698 // CHECK17-NEXT: ret void 3699 // 3700 // 3701 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144 3702 // CHECK17-SAME: (%struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { 3703 // CHECK17-NEXT: entry: 3704 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 3705 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3706 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 3707 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 3708 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 3709 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 3710 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 3711 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 3712 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 3713 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3714 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 3715 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 3716 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 3717 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 3718 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 3719 // CHECK17-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 3720 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3721 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 3722 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 3723 // CHECK17-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 3724 // CHECK17-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 3725 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 3726 // CHECK17-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 3727 // CHECK17-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 3728 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, ppc_fp128*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP0]], ppc_fp128* [[TMP5]], %struct.St* [[TMP4]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]], i32* [[CONV]], %struct.St* [[TMP6]]) 3729 // CHECK17-NEXT: ret void 3730 // 3731 // 3732 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 3733 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { 3734 // CHECK17-NEXT: entry: 3735 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3736 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3737 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3738 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 3739 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 3740 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 3741 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 3742 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 3743 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 3744 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 3745 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3746 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3747 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3748 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3749 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3750 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3751 // CHECK17-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 3752 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 3753 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 3754 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 3755 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 3756 // CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 3757 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 3758 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3759 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 3760 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 3761 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 3762 // CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 3763 // CHECK17-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8 3764 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 3765 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 3766 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 3767 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128 3768 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 3769 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 3770 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 3771 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8 3772 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* 3773 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* 3774 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 [[TMP9]], i1 false) 3775 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 3776 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 3777 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 3778 // CHECK17-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 3779 // CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 3780 // CHECK17-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP3]] 3781 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i64 [[TMP13]] 3782 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 3783 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 3784 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 3785 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] 3786 // CHECK17-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 3787 // CHECK17-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128 3788 // CHECK17-NEXT: [[TMP15:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 3789 // CHECK17-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 3790 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 3791 // CHECK17-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 3792 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP15]], i64 [[IDXPROM11]] 3793 // CHECK17-NEXT: store ppc_fp128 [[CONV9]], ppc_fp128* [[ARRAYIDX12]], align 16 3794 // CHECK17-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3795 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) 3796 // CHECK17-NEXT: ret void 3797 // 3798 // 3799 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3800 // CHECK17-SAME: () #[[ATTR5:[0-9]+]] { 3801 // CHECK17-NEXT: entry: 3802 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 3803 // CHECK17-NEXT: ret void 3804 // 3805 // 3806 // CHECK18-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg 3807 // CHECK18-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 3808 // CHECK18-NEXT: entry: 3809 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3810 // CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 3811 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3812 // CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 3813 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3814 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3815 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3816 // CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 3817 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 8 3818 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 8 3819 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 8 3820 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 8 3821 // CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3822 // CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 3823 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3824 // CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 3825 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3826 // CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 3827 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3828 // CHECK18-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 3829 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3830 // CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 3831 // CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 3832 // CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 3833 // CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 3834 // CHECK18-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 3835 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 3836 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 3837 // CHECK18-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 3838 // CHECK18-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 3839 // CHECK18-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 3840 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 3841 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 3842 // CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 3843 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 3844 // CHECK18-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 3845 // CHECK18-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 3846 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3847 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** 3848 // CHECK18-NEXT: store float* [[TMP8]], float** [[TMP16]], align 8 3849 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3850 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to float** 3851 // CHECK18-NEXT: store float* [[TMP8]], float** [[TMP18]], align 8 3852 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3853 // CHECK18-NEXT: store i64 0, i64* [[TMP19]], align 8 3854 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3855 // CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 3856 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3857 // CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** 3858 // CHECK18-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP22]], align 8 3859 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3860 // CHECK18-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to %struct.St** 3861 // CHECK18-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP24]], align 8 3862 // CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 3863 // CHECK18-NEXT: store i64 0, i64* [[TMP25]], align 8 3864 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3865 // CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 3866 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3867 // CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 3868 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP28]], align 8 3869 // CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3870 // CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 3871 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP30]], align 8 3872 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 3873 // CHECK18-NEXT: store i64 8, i64* [[TMP31]], align 8 3874 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3875 // CHECK18-NEXT: store i8* null, i8** [[TMP32]], align 8 3876 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3877 // CHECK18-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to ppc_fp128** 3878 // CHECK18-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP34]], align 8 3879 // CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3880 // CHECK18-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to ppc_fp128** 3881 // CHECK18-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP36]], align 8 3882 // CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3883 // CHECK18-NEXT: store i64 0, i64* [[TMP37]], align 8 3884 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 3885 // CHECK18-NEXT: store i8* null, i8** [[TMP38]], align 8 3886 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3887 // CHECK18-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i64* 3888 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP40]], align 8 3889 // CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3890 // CHECK18-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i64* 3891 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP42]], align 8 3892 // CHECK18-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3893 // CHECK18-NEXT: store i64 8, i64* [[TMP43]], align 8 3894 // CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 3895 // CHECK18-NEXT: store i8* null, i8** [[TMP44]], align 8 3896 // CHECK18-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 3897 // CHECK18-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* 3898 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP46]], align 8 3899 // CHECK18-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 3900 // CHECK18-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* 3901 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP48]], align 8 3902 // CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 3903 // CHECK18-NEXT: store i64 8, i64* [[TMP49]], align 8 3904 // CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 3905 // CHECK18-NEXT: store i8* null, i8** [[TMP50]], align 8 3906 // CHECK18-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 3907 // CHECK18-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** 3908 // CHECK18-NEXT: store double* [[VLA]], double** [[TMP52]], align 8 3909 // CHECK18-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 3910 // CHECK18-NEXT: [[TMP54:%.*]] = bitcast i8** [[TMP53]] to double** 3911 // CHECK18-NEXT: store double* [[VLA]], double** [[TMP54]], align 8 3912 // CHECK18-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 3913 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP55]], align 8 3914 // CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 3915 // CHECK18-NEXT: store i8* null, i8** [[TMP56]], align 8 3916 // CHECK18-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 3917 // CHECK18-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i64* 3918 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP58]], align 8 3919 // CHECK18-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 3920 // CHECK18-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i64* 3921 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP60]], align 8 3922 // CHECK18-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3923 // CHECK18-NEXT: store i64 4, i64* [[TMP61]], align 8 3924 // CHECK18-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 3925 // CHECK18-NEXT: store i8* null, i8** [[TMP62]], align 8 3926 // CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3927 // CHECK18-NEXT: [[TMP64:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3928 // CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3929 // CHECK18-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, i32 8, i8** [[TMP63]], i8** [[TMP64]], i64* [[TMP65]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3930 // CHECK18-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 3931 // CHECK18-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3932 // CHECK18: omp_offload.failed: 3933 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(float* [[TMP8]], %struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 3934 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 3935 // CHECK18: omp_offload.cont: 3936 // CHECK18-NEXT: [[TMP68:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3937 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP68]]) 3938 // CHECK18-NEXT: ret void 3939 // 3940 // 3941 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152 3942 // CHECK18-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 3943 // CHECK18-NEXT: entry: 3944 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3945 // CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 3946 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3947 // CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 3948 // CHECK18-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 3949 // CHECK18-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 3950 // CHECK18-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 3951 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 3952 // CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3953 // CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 3954 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3955 // CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 3956 // CHECK18-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 3957 // CHECK18-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 3958 // CHECK18-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 3959 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 3960 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3961 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 3962 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 3963 // CHECK18-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 3964 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 3965 // CHECK18-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 3966 // CHECK18-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 3967 // CHECK18-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 8 3968 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, ppc_fp128*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[CONV]], i64 [[TMP0]], ppc_fp128* [[TMP5]], float* [[TMP6]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]]) 3969 // CHECK18-NEXT: ret void 3970 // 3971 // 3972 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. 3973 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { 3974 // CHECK18-NEXT: entry: 3975 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3976 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3977 // CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 3978 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 3979 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3980 // CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 3981 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3982 // CHECK18-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 3983 // CHECK18-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 3984 // CHECK18-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 3985 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3986 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3987 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3988 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3989 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3990 // CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 3991 // CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 3992 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3993 // CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 3994 // CHECK18-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3995 // CHECK18-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 3996 // CHECK18-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 3997 // CHECK18-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 3998 // CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 3999 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4000 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 4001 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 4002 // CHECK18-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 4003 // CHECK18-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() 4004 // CHECK18-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8 4005 // CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4006 // CHECK18-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 4007 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 4008 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 4009 // CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4010 // CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 4011 // CHECK18-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* 4012 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* 4013 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false) 4014 // CHECK18-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4015 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0 4016 // CHECK18-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4017 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 4018 // CHECK18-NEXT: [[TMP14:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4019 // CHECK18-NEXT: call void @_ZN2St7St_funcEPS_iPg(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 signext [[TMP13]], ppc_fp128* [[TMP14]]) 4020 // CHECK18-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4021 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 4022 // CHECK18-NEXT: ret void 4023 // 4024 // 4025 // CHECK18-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg 4026 // CHECK18-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 signext [[N:%.*]], ppc_fp128* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 4027 // CHECK18-NEXT: entry: 4028 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 4029 // CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4030 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4031 // CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4032 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4033 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4034 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 4035 // CHECK18-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 4036 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 8 4037 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 8 4038 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 8 4039 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 4040 // CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 4041 // CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4042 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4043 // CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 4044 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 4045 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4046 // CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 4047 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4048 // CHECK18-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 4049 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4050 // CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 4051 // CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 4052 // CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 4053 // CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 4054 // CHECK18-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 4055 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 4056 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 4057 // CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 4058 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 4059 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 4060 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 4061 // CHECK18-NEXT: [[TMP9:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4062 // CHECK18-NEXT: [[TMP10:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4063 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[N_ADDR]], align 4 4064 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 4065 // CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 4066 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[N_CASTED]], align 8 4067 // CHECK18-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 4068 // CHECK18-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 4069 // CHECK18-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 4070 // CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 4071 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr i32, i32* [[B2]], i32 1 4072 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i32* [[A3]] to i8* 4073 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i32* [[TMP15]] to i8* 4074 // CHECK18-NEXT: [[TMP18:%.*]] = ptrtoint i8* [[TMP17]] to i64 4075 // CHECK18-NEXT: [[TMP19:%.*]] = ptrtoint i8* [[TMP16]] to i64 4076 // CHECK18-NEXT: [[TMP20:%.*]] = sub i64 [[TMP18]], [[TMP19]] 4077 // CHECK18-NEXT: [[TMP21:%.*]] = sdiv exact i64 [[TMP20]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) 4078 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4079 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** 4080 // CHECK18-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP23]], align 8 4081 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4082 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.St** 4083 // CHECK18-NEXT: store %struct.St* [[TMP9]], %struct.St** [[TMP25]], align 8 4084 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4085 // CHECK18-NEXT: store i64 0, i64* [[TMP26]], align 8 4086 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4087 // CHECK18-NEXT: store i8* null, i8** [[TMP27]], align 8 4088 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4089 // CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 4090 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP29]], align 8 4091 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4092 // CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 4093 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP31]], align 8 4094 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 4095 // CHECK18-NEXT: store i64 8, i64* [[TMP32]], align 8 4096 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4097 // CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 4098 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4099 // CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to ppc_fp128** 4100 // CHECK18-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP35]], align 8 4101 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4102 // CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to ppc_fp128** 4103 // CHECK18-NEXT: store ppc_fp128* [[TMP10]], ppc_fp128** [[TMP37]], align 8 4104 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 4105 // CHECK18-NEXT: store i64 0, i64* [[TMP38]], align 8 4106 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4107 // CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 4108 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4109 // CHECK18-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* 4110 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP41]], align 8 4111 // CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4112 // CHECK18-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* 4113 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP43]], align 8 4114 // CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 4115 // CHECK18-NEXT: store i64 8, i64* [[TMP44]], align 8 4116 // CHECK18-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4117 // CHECK18-NEXT: store i8* null, i8** [[TMP45]], align 8 4118 // CHECK18-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4119 // CHECK18-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i64* 4120 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP47]], align 8 4121 // CHECK18-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4122 // CHECK18-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i64* 4123 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP49]], align 8 4124 // CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4125 // CHECK18-NEXT: store i64 8, i64* [[TMP50]], align 8 4126 // CHECK18-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 4127 // CHECK18-NEXT: store i8* null, i8** [[TMP51]], align 8 4128 // CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4129 // CHECK18-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** 4130 // CHECK18-NEXT: store double* [[VLA]], double** [[TMP53]], align 8 4131 // CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4132 // CHECK18-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to double** 4133 // CHECK18-NEXT: store double* [[VLA]], double** [[TMP55]], align 8 4134 // CHECK18-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 4135 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP56]], align 8 4136 // CHECK18-NEXT: [[TMP57:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 4137 // CHECK18-NEXT: store i8* null, i8** [[TMP57]], align 8 4138 // CHECK18-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 4139 // CHECK18-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to %struct.St** 4140 // CHECK18-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP59]], align 8 4141 // CHECK18-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 4142 // CHECK18-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32** 4143 // CHECK18-NEXT: store i32* [[A3]], i32** [[TMP61]], align 8 4144 // CHECK18-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 4145 // CHECK18-NEXT: store i64 [[TMP21]], i64* [[TMP62]], align 8 4146 // CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 4147 // CHECK18-NEXT: store i8* null, i8** [[TMP63]], align 8 4148 // CHECK18-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 4149 // CHECK18-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to %struct.St** 4150 // CHECK18-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP65]], align 8 4151 // CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 4152 // CHECK18-NEXT: [[TMP67:%.*]] = bitcast i8** [[TMP66]] to i32** 4153 // CHECK18-NEXT: store i32* [[B2]], i32** [[TMP67]], align 8 4154 // CHECK18-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 4155 // CHECK18-NEXT: store i64 4, i64* [[TMP68]], align 8 4156 // CHECK18-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 4157 // CHECK18-NEXT: store i8* null, i8** [[TMP69]], align 8 4158 // CHECK18-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 4159 // CHECK18-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to %struct.St** 4160 // CHECK18-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP71]], align 8 4161 // CHECK18-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 4162 // CHECK18-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to i32** 4163 // CHECK18-NEXT: store i32* [[A3]], i32** [[TMP73]], align 8 4164 // CHECK18-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 4165 // CHECK18-NEXT: store i64 4, i64* [[TMP74]], align 8 4166 // CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 4167 // CHECK18-NEXT: store i8* null, i8** [[TMP75]], align 8 4168 // CHECK18-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 4169 // CHECK18-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* 4170 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP77]], align 8 4171 // CHECK18-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 4172 // CHECK18-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* 4173 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP79]], align 8 4174 // CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 4175 // CHECK18-NEXT: store i64 4, i64* [[TMP80]], align 8 4176 // CHECK18-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9 4177 // CHECK18-NEXT: store i8* null, i8** [[TMP81]], align 8 4178 // CHECK18-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4179 // CHECK18-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4180 // CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4181 // CHECK18-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, i32 10, i8** [[TMP82]], i8** [[TMP83]], i64* [[TMP84]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4182 // CHECK18-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 4183 // CHECK18-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4184 // CHECK18: omp_offload.failed: 4185 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(%struct.St* [[TMP9]], i64 [[TMP1]], ppc_fp128* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], %struct.St* [[THIS1]], i64 [[TMP12]]) #[[ATTR4]] 4186 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 4187 // CHECK18: omp_offload.cont: 4188 // CHECK18-NEXT: [[TMP87:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4189 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP87]]) 4190 // CHECK18-NEXT: ret void 4191 // 4192 // 4193 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144 4194 // CHECK18-SAME: (%struct.St* [[S:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { 4195 // CHECK18-NEXT: entry: 4196 // CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4197 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4198 // CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4199 // CHECK18-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 4200 // CHECK18-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 4201 // CHECK18-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 4202 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 4203 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 4204 // CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4205 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4206 // CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 4207 // CHECK18-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 4208 // CHECK18-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 4209 // CHECK18-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 4210 // CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 4211 // CHECK18-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 4212 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4213 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 4214 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 4215 // CHECK18-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 4216 // CHECK18-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 4217 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 4218 // CHECK18-NEXT: [[TMP5:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4219 // CHECK18-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4220 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, ppc_fp128*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP0]], ppc_fp128* [[TMP5]], %struct.St* [[TMP4]], i64 [[TMP1]], i64 [[TMP2]], double* [[TMP3]], i32* [[CONV]], %struct.St* [[TMP6]]) 4221 // CHECK18-NEXT: ret void 4222 // 4223 // 4224 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 4225 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ppc_fp128* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { 4226 // CHECK18-NEXT: entry: 4227 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4228 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4229 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4230 // CHECK18-NEXT: [[VLA1_ADDR:%.*]] = alloca ppc_fp128*, align 8 4231 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 4232 // CHECK18-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 4233 // CHECK18-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 4234 // CHECK18-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 4235 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 4236 // CHECK18-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4237 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4238 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4239 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 4240 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4241 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4242 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4243 // CHECK18-NEXT: store ppc_fp128* [[VLA1]], ppc_fp128** [[VLA1_ADDR]], align 8 4244 // CHECK18-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 4245 // CHECK18-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 4246 // CHECK18-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 4247 // CHECK18-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 4248 // CHECK18-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 4249 // CHECK18-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4250 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4251 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 4252 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 4253 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 4254 // CHECK18-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 4255 // CHECK18-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8 4256 // CHECK18-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 4257 // CHECK18-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 4258 // CHECK18-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4259 // CHECK18-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128 4260 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 4261 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 4262 // CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4263 // CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8 4264 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* 4265 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* 4266 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 [[TMP9]], i1 false) 4267 // CHECK18-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 4268 // CHECK18-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 4269 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 4270 // CHECK18-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 4271 // CHECK18-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 4272 // CHECK18-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP3]] 4273 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i64 [[TMP13]] 4274 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 4275 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 4276 // CHECK18-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 4277 // CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] 4278 // CHECK18-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 4279 // CHECK18-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128 4280 // CHECK18-NEXT: [[TMP15:%.*]] = load ppc_fp128*, ppc_fp128** [[VLA1_ADDR]], align 8 4281 // CHECK18-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 4282 // CHECK18-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 4283 // CHECK18-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 4284 // CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ppc_fp128* [[TMP15]], i64 [[IDXPROM11]] 4285 // CHECK18-NEXT: store ppc_fp128 [[CONV9]], ppc_fp128* [[ARRAYIDX12]], align 16 4286 // CHECK18-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4287 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) 4288 // CHECK18-NEXT: ret void 4289 // 4290 // 4291 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4292 // CHECK18-SAME: () #[[ATTR5:[0-9]+]] { 4293 // CHECK18-NEXT: entry: 4294 // CHECK18-NEXT: call void @__tgt_register_requires(i64 1) 4295 // CHECK18-NEXT: ret void 4296 // 4297 // 4298 // CHECK19-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe 4299 // CHECK19-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 4300 // CHECK19-NEXT: entry: 4301 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 4302 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 4303 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4304 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 4305 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 4306 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 4307 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 4308 // CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 4309 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 4 4310 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 4 4311 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 4 4312 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 4 4313 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 4314 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 4315 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4316 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 4317 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4318 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 4319 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4320 // CHECK19-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 4321 // CHECK19-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 4322 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 4323 // CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 4324 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 4325 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 4326 // CHECK19-NEXT: [[TMP5:%.*]] = load float*, float** [[A_ADDR]], align 4 4327 // CHECK19-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 4328 // CHECK19-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 4329 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 4330 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 4331 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 4332 // CHECK19-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 4333 // CHECK19-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 4334 // CHECK19-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 4335 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4336 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to float** 4337 // CHECK19-NEXT: store float* [[TMP5]], float** [[TMP14]], align 4 4338 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4339 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** 4340 // CHECK19-NEXT: store float* [[TMP5]], float** [[TMP16]], align 4 4341 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4342 // CHECK19-NEXT: store i64 0, i64* [[TMP17]], align 4 4343 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4344 // CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 4345 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4346 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.St** 4347 // CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP20]], align 4 4348 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4349 // CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** 4350 // CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP22]], align 4 4351 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 4352 // CHECK19-NEXT: store i64 0, i64* [[TMP23]], align 4 4353 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4354 // CHECK19-NEXT: store i8* null, i8** [[TMP24]], align 4 4355 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4356 // CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 4357 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 4358 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4359 // CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 4360 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP28]], align 4 4361 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 4362 // CHECK19-NEXT: store i64 4, i64* [[TMP29]], align 4 4363 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4364 // CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 4365 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4366 // CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to x86_fp80** 4367 // CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP32]], align 4 4368 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4369 // CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to x86_fp80** 4370 // CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP34]], align 4 4371 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 4372 // CHECK19-NEXT: store i64 0, i64* [[TMP35]], align 4 4373 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 4374 // CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 4375 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4376 // CHECK19-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* 4377 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP38]], align 4 4378 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4379 // CHECK19-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* 4380 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP40]], align 4 4381 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4382 // CHECK19-NEXT: store i64 4, i64* [[TMP41]], align 4 4383 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 4384 // CHECK19-NEXT: store i8* null, i8** [[TMP42]], align 4 4385 // CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4386 // CHECK19-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* 4387 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP44]], align 4 4388 // CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4389 // CHECK19-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* 4390 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP46]], align 4 4391 // CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 4392 // CHECK19-NEXT: store i64 4, i64* [[TMP47]], align 4 4393 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 4394 // CHECK19-NEXT: store i8* null, i8** [[TMP48]], align 4 4395 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 4396 // CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to double** 4397 // CHECK19-NEXT: store double* [[VLA]], double** [[TMP50]], align 4 4398 // CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 4399 // CHECK19-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** 4400 // CHECK19-NEXT: store double* [[VLA]], double** [[TMP52]], align 4 4401 // CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 4402 // CHECK19-NEXT: store i64 [[TMP12]], i64* [[TMP53]], align 4 4403 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 4404 // CHECK19-NEXT: store i8* null, i8** [[TMP54]], align 4 4405 // CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 4406 // CHECK19-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32* 4407 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP56]], align 4 4408 // CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 4409 // CHECK19-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32* 4410 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP58]], align 4 4411 // CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 4412 // CHECK19-NEXT: store i64 4, i64* [[TMP59]], align 4 4413 // CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 4414 // CHECK19-NEXT: store i8* null, i8** [[TMP60]], align 4 4415 // CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4416 // CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4417 // CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4418 // CHECK19-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, i32 8, i8** [[TMP61]], i8** [[TMP62]], i64* [[TMP63]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4419 // CHECK19-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 4420 // CHECK19-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4421 // CHECK19: omp_offload.failed: 4422 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(float* [[TMP5]], %struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], i32 [[TMP9]]) #[[ATTR4:[0-9]+]] 4423 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 4424 // CHECK19: omp_offload.cont: 4425 // CHECK19-NEXT: [[TMP66:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4426 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP66]]) 4427 // CHECK19-NEXT: ret void 4428 // 4429 // 4430 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152 4431 // CHECK19-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 4432 // CHECK19-NEXT: entry: 4433 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 4434 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 4435 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4436 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 4437 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 4438 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 4439 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 4440 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4441 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 4442 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 4443 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4444 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 4445 // CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 4446 // CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 4447 // CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 4448 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4449 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4450 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 4451 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 4452 // CHECK19-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 4453 // CHECK19-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 4454 // CHECK19-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 4455 // CHECK19-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 4 4456 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i32, x86_fp80*, float*, i32, i32, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[N_ADDR]], i32 [[TMP0]], x86_fp80* [[TMP5]], float* [[TMP6]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]]) 4457 // CHECK19-NEXT: ret void 4458 // 4459 // 4460 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 4461 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { 4462 // CHECK19-NEXT: entry: 4463 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4464 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4465 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 4466 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 4467 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4468 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 4469 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 4470 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 4471 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 4472 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 4473 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 4474 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 4475 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 4476 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4477 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4478 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 4479 // CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 4480 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4481 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 4482 // CHECK19-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 4483 // CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 4484 // CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 4485 // CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 4486 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 4487 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4488 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 4489 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 4490 // CHECK19-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 4491 // CHECK19-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() 4492 // CHECK19-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 4 4493 // CHECK19-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 4494 // CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128 4495 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 4496 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 4497 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 4498 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8 4499 // CHECK19-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* 4500 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* 4501 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i32 [[TMP8]], i1 false) 4502 // CHECK19-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 4503 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i32 0 4504 // CHECK19-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 4505 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 4506 // CHECK19-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 4507 // CHECK19-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]]) 4508 // CHECK19-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4509 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 4510 // CHECK19-NEXT: ret void 4511 // 4512 // 4513 // CHECK19-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe 4514 // CHECK19-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 4515 // CHECK19-NEXT: entry: 4516 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 4517 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 4518 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4519 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 4520 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 4521 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 4522 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 4523 // CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 4524 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 4 4525 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 4 4526 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 4 4527 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 4528 // CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 4529 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 4530 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4531 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 4532 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 4533 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4534 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 4535 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4536 // CHECK19-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 4537 // CHECK19-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 4538 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 4539 // CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 4540 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 4541 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 4542 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 4543 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 4544 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 4545 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 4546 // CHECK19-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 4547 // CHECK19-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 4548 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 4549 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 4550 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 4551 // CHECK19-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 4552 // CHECK19-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 4553 // CHECK19-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 4554 // CHECK19-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 4555 // CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 4556 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr i32, i32* [[B2]], i32 1 4557 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i32* [[A3]] to i8* 4558 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP13]] to i8* 4559 // CHECK19-NEXT: [[TMP16:%.*]] = ptrtoint i8* [[TMP15]] to i64 4560 // CHECK19-NEXT: [[TMP17:%.*]] = ptrtoint i8* [[TMP14]] to i64 4561 // CHECK19-NEXT: [[TMP18:%.*]] = sub i64 [[TMP16]], [[TMP17]] 4562 // CHECK19-NEXT: [[TMP19:%.*]] = sdiv exact i64 [[TMP18]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) 4563 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4564 // CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.St** 4565 // CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP21]], align 4 4566 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4567 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** 4568 // CHECK19-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP23]], align 4 4569 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4570 // CHECK19-NEXT: store i64 0, i64* [[TMP24]], align 4 4571 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4572 // CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4 4573 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4574 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 4575 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP27]], align 4 4576 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4577 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 4578 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP29]], align 4 4579 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 4580 // CHECK19-NEXT: store i64 4, i64* [[TMP30]], align 4 4581 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4582 // CHECK19-NEXT: store i8* null, i8** [[TMP31]], align 4 4583 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4584 // CHECK19-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to x86_fp80** 4585 // CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP33]], align 4 4586 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4587 // CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to x86_fp80** 4588 // CHECK19-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP35]], align 4 4589 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 4590 // CHECK19-NEXT: store i64 0, i64* [[TMP36]], align 4 4591 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4592 // CHECK19-NEXT: store i8* null, i8** [[TMP37]], align 4 4593 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4594 // CHECK19-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 4595 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP39]], align 4 4596 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4597 // CHECK19-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* 4598 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP41]], align 4 4599 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 4600 // CHECK19-NEXT: store i64 4, i64* [[TMP42]], align 4 4601 // CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 4602 // CHECK19-NEXT: store i8* null, i8** [[TMP43]], align 4 4603 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4604 // CHECK19-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32* 4605 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP45]], align 4 4606 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4607 // CHECK19-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32* 4608 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP47]], align 4 4609 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4610 // CHECK19-NEXT: store i64 4, i64* [[TMP48]], align 4 4611 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 4612 // CHECK19-NEXT: store i8* null, i8** [[TMP49]], align 4 4613 // CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4614 // CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** 4615 // CHECK19-NEXT: store double* [[VLA]], double** [[TMP51]], align 4 4616 // CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4617 // CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** 4618 // CHECK19-NEXT: store double* [[VLA]], double** [[TMP53]], align 4 4619 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 4620 // CHECK19-NEXT: store i64 [[TMP12]], i64* [[TMP54]], align 4 4621 // CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 4622 // CHECK19-NEXT: store i8* null, i8** [[TMP55]], align 4 4623 // CHECK19-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 4624 // CHECK19-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to %struct.St** 4625 // CHECK19-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP57]], align 4 4626 // CHECK19-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 4627 // CHECK19-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to i32** 4628 // CHECK19-NEXT: store i32* [[A3]], i32** [[TMP59]], align 4 4629 // CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 4630 // CHECK19-NEXT: store i64 [[TMP19]], i64* [[TMP60]], align 4 4631 // CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 4632 // CHECK19-NEXT: store i8* null, i8** [[TMP61]], align 4 4633 // CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 4634 // CHECK19-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to %struct.St** 4635 // CHECK19-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP63]], align 4 4636 // CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 4637 // CHECK19-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32** 4638 // CHECK19-NEXT: store i32* [[B2]], i32** [[TMP65]], align 4 4639 // CHECK19-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 4640 // CHECK19-NEXT: store i64 4, i64* [[TMP66]], align 4 4641 // CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 4642 // CHECK19-NEXT: store i8* null, i8** [[TMP67]], align 4 4643 // CHECK19-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 4644 // CHECK19-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to %struct.St** 4645 // CHECK19-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP69]], align 4 4646 // CHECK19-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 4647 // CHECK19-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32** 4648 // CHECK19-NEXT: store i32* [[A3]], i32** [[TMP71]], align 4 4649 // CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 4650 // CHECK19-NEXT: store i64 4, i64* [[TMP72]], align 4 4651 // CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 4652 // CHECK19-NEXT: store i8* null, i8** [[TMP73]], align 4 4653 // CHECK19-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 4654 // CHECK19-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32* 4655 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP75]], align 4 4656 // CHECK19-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 4657 // CHECK19-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* 4658 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[TMP77]], align 4 4659 // CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 4660 // CHECK19-NEXT: store i64 4, i64* [[TMP78]], align 4 4661 // CHECK19-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 9 4662 // CHECK19-NEXT: store i8* null, i8** [[TMP79]], align 4 4663 // CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4664 // CHECK19-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4665 // CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4666 // CHECK19-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, i32 10, i8** [[TMP80]], i8** [[TMP81]], i64* [[TMP82]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4667 // CHECK19-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0 4668 // CHECK19-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4669 // CHECK19: omp_offload.failed: 4670 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(%struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], %struct.St* [[THIS1]], i32 [[TMP9]]) #[[ATTR4]] 4671 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 4672 // CHECK19: omp_offload.cont: 4673 // CHECK19-NEXT: [[TMP85:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4674 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP85]]) 4675 // CHECK19-NEXT: ret void 4676 // 4677 // 4678 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144 4679 // CHECK19-SAME: (%struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] { 4680 // CHECK19-NEXT: entry: 4681 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 4682 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4683 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 4684 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 4685 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 4686 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 4687 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 4688 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4689 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 4690 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4691 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 4692 // CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 4693 // CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 4694 // CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 4695 // CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 4696 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4697 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4698 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 4699 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 4700 // CHECK19-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 4701 // CHECK19-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 4702 // CHECK19-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 4703 // CHECK19-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 4704 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, x86_fp80*, %struct.St*, i32, i32, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP0]], x86_fp80* [[TMP5]], %struct.St* [[TMP4]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]], i32* [[N_ADDR]], %struct.St* [[TMP6]]) 4705 // CHECK19-NEXT: ret void 4706 // 4707 // 4708 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 4709 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { 4710 // CHECK19-NEXT: entry: 4711 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4712 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4713 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4714 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 4715 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 4716 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 4717 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 4718 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 4719 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 4720 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 4721 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 4722 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 4723 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 4724 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4725 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4726 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4727 // CHECK19-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 4728 // CHECK19-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 4729 // CHECK19-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 4730 // CHECK19-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 4731 // CHECK19-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 4732 // CHECK19-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 4733 // CHECK19-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 4734 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4735 // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 4736 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 4737 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 4738 // CHECK19-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 4739 // CHECK19-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 4 4740 // CHECK19-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 4741 // CHECK19-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 4 4742 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 4743 // CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128 4744 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 4745 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 4746 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 4747 // CHECK19-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8 4748 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* 4749 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* 4750 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 [[TMP9]], i1 false) 4751 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 4752 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 4753 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 4754 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 4755 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 4756 // CHECK19-NEXT: [[TMP13:%.*]] = mul nsw i32 1, [[TMP3]] 4757 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i32 [[TMP13]] 4758 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 4759 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 4760 // CHECK19-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] 4761 // CHECK19-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 4762 // CHECK19-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80 4763 // CHECK19-NEXT: [[TMP15:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 4764 // CHECK19-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 4765 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 4766 // CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP15]], i32 [[TMP16]] 4767 // CHECK19-NEXT: store x86_fp80 [[CONV9]], x86_fp80* [[ARRAYIDX11]], align 4 4768 // CHECK19-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4769 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) 4770 // CHECK19-NEXT: ret void 4771 // 4772 // 4773 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4774 // CHECK19-SAME: () #[[ATTR5:[0-9]+]] { 4775 // CHECK19-NEXT: entry: 4776 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 4777 // CHECK19-NEXT: ret void 4778 // 4779 // 4780 // CHECK20-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe 4781 // CHECK20-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 4782 // CHECK20-NEXT: entry: 4783 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 4784 // CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 4785 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4786 // CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 4787 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 4788 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 4789 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 4790 // CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 4791 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x i8*], align 4 4792 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x i8*], align 4 4793 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x i8*], align 4 4794 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 4 4795 // CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 4796 // CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 4797 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4798 // CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 4799 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4800 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 4801 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4802 // CHECK20-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 4803 // CHECK20-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 4804 // CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 4805 // CHECK20-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 4806 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 4807 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 4808 // CHECK20-NEXT: [[TMP5:%.*]] = load float*, float** [[A_ADDR]], align 4 4809 // CHECK20-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 4810 // CHECK20-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 4811 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 4812 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 4813 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 4814 // CHECK20-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 4815 // CHECK20-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 4816 // CHECK20-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 4817 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4818 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to float** 4819 // CHECK20-NEXT: store float* [[TMP5]], float** [[TMP14]], align 4 4820 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4821 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to float** 4822 // CHECK20-NEXT: store float* [[TMP5]], float** [[TMP16]], align 4 4823 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4824 // CHECK20-NEXT: store i64 0, i64* [[TMP17]], align 4 4825 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4826 // CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 4827 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4828 // CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to %struct.St** 4829 // CHECK20-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP20]], align 4 4830 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4831 // CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to %struct.St** 4832 // CHECK20-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP22]], align 4 4833 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 4834 // CHECK20-NEXT: store i64 0, i64* [[TMP23]], align 4 4835 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4836 // CHECK20-NEXT: store i8* null, i8** [[TMP24]], align 4 4837 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4838 // CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 4839 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP26]], align 4 4840 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4841 // CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 4842 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP28]], align 4 4843 // CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 4844 // CHECK20-NEXT: store i64 4, i64* [[TMP29]], align 4 4845 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4846 // CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 4847 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4848 // CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to x86_fp80** 4849 // CHECK20-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP32]], align 4 4850 // CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4851 // CHECK20-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to x86_fp80** 4852 // CHECK20-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP34]], align 4 4853 // CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 4854 // CHECK20-NEXT: store i64 0, i64* [[TMP35]], align 4 4855 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 4856 // CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 4857 // CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4858 // CHECK20-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* 4859 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP38]], align 4 4860 // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4861 // CHECK20-NEXT: [[TMP40:%.*]] = bitcast i8** [[TMP39]] to i32* 4862 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP40]], align 4 4863 // CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4864 // CHECK20-NEXT: store i64 4, i64* [[TMP41]], align 4 4865 // CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 4866 // CHECK20-NEXT: store i8* null, i8** [[TMP42]], align 4 4867 // CHECK20-NEXT: [[TMP43:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4868 // CHECK20-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* 4869 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP44]], align 4 4870 // CHECK20-NEXT: [[TMP45:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4871 // CHECK20-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i32* 4872 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP46]], align 4 4873 // CHECK20-NEXT: [[TMP47:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 4874 // CHECK20-NEXT: store i64 4, i64* [[TMP47]], align 4 4875 // CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 4876 // CHECK20-NEXT: store i8* null, i8** [[TMP48]], align 4 4877 // CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 4878 // CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to double** 4879 // CHECK20-NEXT: store double* [[VLA]], double** [[TMP50]], align 4 4880 // CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 4881 // CHECK20-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to double** 4882 // CHECK20-NEXT: store double* [[VLA]], double** [[TMP52]], align 4 4883 // CHECK20-NEXT: [[TMP53:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 4884 // CHECK20-NEXT: store i64 [[TMP12]], i64* [[TMP53]], align 4 4885 // CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 4886 // CHECK20-NEXT: store i8* null, i8** [[TMP54]], align 4 4887 // CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 4888 // CHECK20-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32* 4889 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[TMP56]], align 4 4890 // CHECK20-NEXT: [[TMP57:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 4891 // CHECK20-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32* 4892 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[TMP58]], align 4 4893 // CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 4894 // CHECK20-NEXT: store i64 4, i64* [[TMP59]], align 4 4895 // CHECK20-NEXT: [[TMP60:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 4896 // CHECK20-NEXT: store i8* null, i8** [[TMP60]], align 4 4897 // CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4898 // CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [8 x i8*], [8 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4899 // CHECK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [8 x i64], [8 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4900 // CHECK20-NEXT: [[TMP64:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, i32 8, i8** [[TMP61]], i8** [[TMP62]], i64* [[TMP63]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4901 // CHECK20-NEXT: [[TMP65:%.*]] = icmp ne i32 [[TMP64]], 0 4902 // CHECK20-NEXT: br i1 [[TMP65]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4903 // CHECK20: omp_offload.failed: 4904 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(float* [[TMP5]], %struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], i32 [[TMP9]]) #[[ATTR4:[0-9]+]] 4905 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 4906 // CHECK20: omp_offload.cont: 4907 // CHECK20-NEXT: [[TMP66:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4908 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP66]]) 4909 // CHECK20-NEXT: ret void 4910 // 4911 // 4912 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152 4913 // CHECK20-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 4914 // CHECK20-NEXT: entry: 4915 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 4916 // CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 4917 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4918 // CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 4919 // CHECK20-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 4920 // CHECK20-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 4921 // CHECK20-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 4922 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4923 // CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 4924 // CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 4925 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4926 // CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 4927 // CHECK20-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 4928 // CHECK20-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 4929 // CHECK20-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 4930 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4931 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4932 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 4933 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 4934 // CHECK20-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 4935 // CHECK20-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 4936 // CHECK20-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 4937 // CHECK20-NEXT: [[TMP6:%.*]] = load float*, float** [[A_ADDR]], align 4 4938 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i32, x86_fp80*, float*, i32, i32, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP4]], i32* [[N_ADDR]], i32 [[TMP0]], x86_fp80* [[TMP5]], float* [[TMP6]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]]) 4939 // CHECK20-NEXT: ret void 4940 // 4941 // 4942 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. 4943 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2]] { 4944 // CHECK20-NEXT: entry: 4945 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4946 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4947 // CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 4948 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 4949 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4950 // CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 4951 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca float*, align 4 4952 // CHECK20-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 4953 // CHECK20-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 4954 // CHECK20-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 4955 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 4956 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 4957 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 4958 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4959 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4960 // CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 4961 // CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 4962 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4963 // CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 4964 // CHECK20-NEXT: store float* [[A]], float** [[A_ADDR]], align 4 4965 // CHECK20-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 4966 // CHECK20-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 4967 // CHECK20-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 4968 // CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 4 4969 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4970 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 4971 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 4972 // CHECK20-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 4973 // CHECK20-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() 4974 // CHECK20-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 4 4975 // CHECK20-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 4976 // CHECK20-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128 4977 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 4978 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 4979 // CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 4980 // CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8 4981 // CHECK20-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* 4982 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* 4983 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i32 [[TMP8]], i1 false) 4984 // CHECK20-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 4985 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i32 0 4986 // CHECK20-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 4987 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 4988 // CHECK20-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 4989 // CHECK20-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]]) 4990 // CHECK20-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4991 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 4992 // CHECK20-NEXT: ret void 4993 // 4994 // 4995 // CHECK20-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe 4996 // CHECK20-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 4997 // CHECK20-NEXT: entry: 4998 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 4999 // CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5000 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5001 // CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5002 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5003 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5004 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5005 // CHECK20-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 5006 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x i8*], align 4 5007 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x i8*], align 4 5008 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x i8*], align 4 5009 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 5010 // CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 5011 // CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5012 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5013 // CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5014 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 5015 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5016 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5017 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5018 // CHECK20-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 5019 // CHECK20-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 4 5020 // CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 5021 // CHECK20-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 5022 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 5023 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 5024 // CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 5025 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 5026 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 5027 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[A]], align 4 5028 // CHECK20-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5029 // CHECK20-NEXT: [[TMP7:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5030 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[N_ADDR]], align 4 5031 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[N_CASTED]], align 4 5032 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[N_CASTED]], align 4 5033 // CHECK20-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 5034 // CHECK20-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 5035 // CHECK20-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 5036 // CHECK20-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 5037 // CHECK20-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 5038 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr i32, i32* [[B2]], i32 1 5039 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i32* [[A3]] to i8* 5040 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast i32* [[TMP13]] to i8* 5041 // CHECK20-NEXT: [[TMP16:%.*]] = ptrtoint i8* [[TMP15]] to i64 5042 // CHECK20-NEXT: [[TMP17:%.*]] = ptrtoint i8* [[TMP14]] to i64 5043 // CHECK20-NEXT: [[TMP18:%.*]] = sub i64 [[TMP16]], [[TMP17]] 5044 // CHECK20-NEXT: [[TMP19:%.*]] = sdiv exact i64 [[TMP18]], ptrtoint (i8* getelementptr (i8, i8* null, i32 1) to i64) 5045 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5046 // CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to %struct.St** 5047 // CHECK20-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP21]], align 4 5048 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5049 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.St** 5050 // CHECK20-NEXT: store %struct.St* [[TMP6]], %struct.St** [[TMP23]], align 4 5051 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5052 // CHECK20-NEXT: store i64 0, i64* [[TMP24]], align 4 5053 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5054 // CHECK20-NEXT: store i8* null, i8** [[TMP25]], align 4 5055 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5056 // CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 5057 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP27]], align 4 5058 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5059 // CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 5060 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP29]], align 4 5061 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 5062 // CHECK20-NEXT: store i64 4, i64* [[TMP30]], align 4 5063 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5064 // CHECK20-NEXT: store i8* null, i8** [[TMP31]], align 4 5065 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5066 // CHECK20-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to x86_fp80** 5067 // CHECK20-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP33]], align 4 5068 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5069 // CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to x86_fp80** 5070 // CHECK20-NEXT: store x86_fp80* [[TMP7]], x86_fp80** [[TMP35]], align 4 5071 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 5072 // CHECK20-NEXT: store i64 0, i64* [[TMP36]], align 4 5073 // CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5074 // CHECK20-NEXT: store i8* null, i8** [[TMP37]], align 4 5075 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5076 // CHECK20-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 5077 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP39]], align 4 5078 // CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5079 // CHECK20-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* 5080 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP41]], align 4 5081 // CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5082 // CHECK20-NEXT: store i64 4, i64* [[TMP42]], align 4 5083 // CHECK20-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 5084 // CHECK20-NEXT: store i8* null, i8** [[TMP43]], align 4 5085 // CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 5086 // CHECK20-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32* 5087 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP45]], align 4 5088 // CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 5089 // CHECK20-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32* 5090 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP47]], align 4 5091 // CHECK20-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 5092 // CHECK20-NEXT: store i64 4, i64* [[TMP48]], align 4 5093 // CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 5094 // CHECK20-NEXT: store i8* null, i8** [[TMP49]], align 4 5095 // CHECK20-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 5096 // CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to double** 5097 // CHECK20-NEXT: store double* [[VLA]], double** [[TMP51]], align 4 5098 // CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 5099 // CHECK20-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to double** 5100 // CHECK20-NEXT: store double* [[VLA]], double** [[TMP53]], align 4 5101 // CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 5102 // CHECK20-NEXT: store i64 [[TMP12]], i64* [[TMP54]], align 4 5103 // CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 5104 // CHECK20-NEXT: store i8* null, i8** [[TMP55]], align 4 5105 // CHECK20-NEXT: [[TMP56:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 5106 // CHECK20-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to %struct.St** 5107 // CHECK20-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP57]], align 4 5108 // CHECK20-NEXT: [[TMP58:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 6 5109 // CHECK20-NEXT: [[TMP59:%.*]] = bitcast i8** [[TMP58]] to i32** 5110 // CHECK20-NEXT: store i32* [[A3]], i32** [[TMP59]], align 4 5111 // CHECK20-NEXT: [[TMP60:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 5112 // CHECK20-NEXT: store i64 [[TMP19]], i64* [[TMP60]], align 4 5113 // CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 5114 // CHECK20-NEXT: store i8* null, i8** [[TMP61]], align 4 5115 // CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 5116 // CHECK20-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to %struct.St** 5117 // CHECK20-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP63]], align 4 5118 // CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 7 5119 // CHECK20-NEXT: [[TMP65:%.*]] = bitcast i8** [[TMP64]] to i32** 5120 // CHECK20-NEXT: store i32* [[B2]], i32** [[TMP65]], align 4 5121 // CHECK20-NEXT: [[TMP66:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5122 // CHECK20-NEXT: store i64 4, i64* [[TMP66]], align 4 5123 // CHECK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 5124 // CHECK20-NEXT: store i8* null, i8** [[TMP67]], align 4 5125 // CHECK20-NEXT: [[TMP68:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 5126 // CHECK20-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to %struct.St** 5127 // CHECK20-NEXT: store %struct.St* [[THIS1]], %struct.St** [[TMP69]], align 4 5128 // CHECK20-NEXT: [[TMP70:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 8 5129 // CHECK20-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32** 5130 // CHECK20-NEXT: store i32* [[A3]], i32** [[TMP71]], align 4 5131 // CHECK20-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 5132 // CHECK20-NEXT: store i64 4, i64* [[TMP72]], align 4 5133 // CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 5134 // CHECK20-NEXT: store i8* null, i8** [[TMP73]], align 4 5135 // CHECK20-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 5136 // CHECK20-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to i32* 5137 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[TMP75]], align 4 5138 // CHECK20-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 9 5139 // CHECK20-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* 5140 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[TMP77]], align 4 5141 // CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 9 5142 // CHECK20-NEXT: store i64 4, i64* [[TMP78]], align 4 5143 // CHECK20-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 9 5144 // CHECK20-NEXT: store i8* null, i8** [[TMP79]], align 4 5145 // CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5146 // CHECK20-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5147 // CHECK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5148 // CHECK20-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, i32 10, i8** [[TMP80]], i8** [[TMP81]], i64* [[TMP82]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.2, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5149 // CHECK20-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0 5150 // CHECK20-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5151 // CHECK20: omp_offload.failed: 5152 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(%struct.St* [[TMP6]], i32 [[TMP0]], x86_fp80* [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], double* [[VLA]], %struct.St* [[THIS1]], i32 [[TMP9]]) #[[ATTR4]] 5153 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 5154 // CHECK20: omp_offload.cont: 5155 // CHECK20-NEXT: [[TMP85:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5156 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP85]]) 5157 // CHECK20-NEXT: ret void 5158 // 5159 // 5160 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144 5161 // CHECK20-SAME: (%struct.St* [[S:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], %struct.St* [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] { 5162 // CHECK20-NEXT: entry: 5163 // CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5164 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5165 // CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5166 // CHECK20-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 5167 // CHECK20-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 5168 // CHECK20-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 5169 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 5170 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5171 // CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5172 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5173 // CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5174 // CHECK20-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 5175 // CHECK20-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 5176 // CHECK20-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 5177 // CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 5178 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5179 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5180 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 5181 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 5182 // CHECK20-NEXT: [[TMP3:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 5183 // CHECK20-NEXT: [[TMP4:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 5184 // CHECK20-NEXT: [[TMP5:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5185 // CHECK20-NEXT: [[TMP6:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 4 5186 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, x86_fp80*, %struct.St*, i32, i32, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP0]], x86_fp80* [[TMP5]], %struct.St* [[TMP4]], i32 [[TMP1]], i32 [[TMP2]], double* [[TMP3]], i32* [[N_ADDR]], %struct.St* [[TMP6]]) 5187 // CHECK20-NEXT: ret void 5188 // 5189 // 5190 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 5191 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], double* nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { 5192 // CHECK20-NEXT: entry: 5193 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5194 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5195 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5196 // CHECK20-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 4 5197 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 5198 // CHECK20-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 5199 // CHECK20-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 5200 // CHECK20-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 4 5201 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 4 5202 // CHECK20-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 4 5203 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5204 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5205 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5206 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5207 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5208 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5209 // CHECK20-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 4 5210 // CHECK20-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 5211 // CHECK20-NEXT: store i32 [[VLA2]], i32* [[VLA_ADDR3]], align 4 5212 // CHECK20-NEXT: store i32 [[VLA4]], i32* [[VLA_ADDR5]], align 4 5213 // CHECK20-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 4 5214 // CHECK20-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 4 5215 // CHECK20-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 4 5216 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5217 // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 5218 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR3]], align 4 5219 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR5]], align 4 5220 // CHECK20-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 4 5221 // CHECK20-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 4 5222 // CHECK20-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 5223 // CHECK20-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 4 5224 // CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 5225 // CHECK20-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128 5226 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR0]], align 4 5227 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 5228 // CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 5229 // CHECK20-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8 5230 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast double* [[VLA7]] to i8* 5231 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP4]] to i8* 5232 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 [[TMP9]], i1 false) 5233 // CHECK20-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 5234 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 5235 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 5236 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[A]], align 4 5237 // CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 5238 // CHECK20-NEXT: [[TMP13:%.*]] = mul nsw i32 1, [[TMP3]] 5239 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[VLA7]], i32 [[TMP13]] 5240 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP5]], align 4 5241 // CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP14]], 1 5242 // CHECK20-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i32 [[SUB]] 5243 // CHECK20-NEXT: store double [[CONV]], double* [[ARRAYIDX8]], align 8 5244 // CHECK20-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80 5245 // CHECK20-NEXT: [[TMP15:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 4 5246 // CHECK20-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 5247 // CHECK20-NEXT: [[TMP16:%.*]] = load i32, i32* [[B10]], align 4 5248 // CHECK20-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP15]], i32 [[TMP16]] 5249 // CHECK20-NEXT: store x86_fp80 [[CONV9]], x86_fp80* [[ARRAYIDX11]], align 4 5250 // CHECK20-NEXT: [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5251 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP17]]) 5252 // CHECK20-NEXT: ret void 5253 // 5254 // 5255 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5256 // CHECK20-SAME: () #[[ATTR5:[0-9]+]] { 5257 // CHECK20-NEXT: entry: 5258 // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) 5259 // CHECK20-NEXT: ret void 5260 // 5261 //