1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -Wno-vla -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 5 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -Wno-vla -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 8 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 9 10 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 12 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 15 // RUN: %clang_cc1 -no-enable-noundef-analysis -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 18 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 19 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 22 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 23 24 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 25 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 26 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 27 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 28 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 29 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 30 31 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -Wno-vla -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 33 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -Wno-vla -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 35 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 36 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK19 37 38 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 39 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 40 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 41 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -verify -Wno-vla -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 42 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping 43 // RUN: %clang_cc1 -no-enable-noundef-analysis -DARRAY -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -include-pch %t -verify -Wno-vla %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 44 // expected-no-diagnostics 45 #ifndef HEADER 46 #define HEADER 47 #ifndef ARRAY 48 struct St { 49 int a, b; 50 St() : a(0), b(0) {} 51 St(const St &st) : a(st.a + st.b), b(0) {} 52 ~St() {} 53 }; 54 55 volatile int g __attribute__((aligned(128))) = 1212; 56 57 template <class T> 58 struct S { 59 T f; 60 S(T a) : f(a + g) {} 61 S() : f(g) {} 62 S(const S &s, St t = St()) : f(s.f + t.a) {} 63 operator T() { return T(); } 64 ~S() {} 65 }; 66 67 68 template <typename T> 69 T tmain() { 70 S<T> test; 71 T t_var __attribute__((aligned(128))) = T(); 72 T vec[] __attribute__((aligned(128))) = {1, 2}; 73 S<T> s_arr[] __attribute__((aligned(128))) = {1, 2}; 74 S<T> var __attribute__((aligned(128))) (3); 75 #pragma omp target 76 #pragma omp teams firstprivate(t_var, vec, s_arr, var) 77 { 78 vec[0] = t_var; 79 s_arr[0] = var; 80 } 81 #pragma omp target 82 #pragma omp teams firstprivate(t_var) 83 {} 84 return T(); 85 } 86 87 int main() { 88 static int sivar; 89 #ifdef LAMBDA 90 [&]() { 91 #pragma omp target 92 #pragma omp teams firstprivate(g, sivar) 93 { 94 g = 1; 95 sivar = 2; 96 [&]() { 97 g = 2; 98 sivar = 4; 99 }(); 100 } 101 }(); 102 return 0; 103 #else 104 S<float> test; 105 int t_var = 0; 106 int vec[] = {1, 2}; 107 S<float> s_arr[] = {1, 2}; 108 S<float> var(3); 109 #pragma omp target 110 #pragma omp teams firstprivate(t_var, vec, s_arr, var, sivar) 111 { 112 vec[0] = t_var; 113 s_arr[0] = var; 114 sivar = 2; 115 } 116 #pragma omp target 117 #pragma omp teams firstprivate(t_var) 118 {} 119 return tmain<int>(); 120 #endif 121 } 122 123 124 125 126 127 128 129 130 131 132 133 134 135 #else 136 struct St { 137 int a, b; 138 St() : a(0), b(0) {} 139 St(const St &) { } 140 ~St() {} 141 void St_func(St s[2], int n, long double vla1[n]) { 142 double vla2[n][n] __attribute__((aligned(128))); 143 a = b; 144 #pragma omp target 145 #pragma omp teams firstprivate(s, vla1, vla2) 146 vla1[b] = vla2[1][n - 1] = a = b; 147 } 148 }; 149 150 void array_func(float a[3], St s[2], int n, long double vla1[n]) { 151 double vla2[n][n] __attribute__((aligned(128))); 152 #pragma omp target 153 #pragma omp teams firstprivate(a, s, vla1, vla2) 154 s[0].St_func(s, n, vla1); 155 ; 156 } 157 158 #endif 159 #endif 160 // CHECK1-LABEL: define {{[^@]+}}@main 161 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 162 // CHECK1-NEXT: entry: 163 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 164 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 165 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 166 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 1 dereferenceable(1) [[REF_TMP]]) 167 // CHECK1-NEXT: ret i32 0 168 // 169 // 170 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 171 // CHECK1-SAME: (i64 [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 172 // CHECK1-NEXT: entry: 173 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 174 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 175 // CHECK1-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8 176 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 177 // CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 178 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 179 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4 180 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 181 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 182 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 183 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 184 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 185 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined, i64 [[TMP1]], i64 [[TMP3]]) 186 // CHECK1-NEXT: ret void 187 // 188 // 189 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined 190 // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 191 // CHECK1-NEXT: entry: 192 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 193 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 194 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 195 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 196 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 197 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 198 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 199 // CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 200 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 201 // CHECK1-NEXT: store i32 1, ptr [[G_ADDR]], align 4 202 // CHECK1-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 203 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 204 // CHECK1-NEXT: store ptr [[G_ADDR]], ptr [[TMP0]], align 8 205 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 206 // CHECK1-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP1]], align 8 207 // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr nonnull align 8 dereferenceable(16) [[REF_TMP]]) 208 // CHECK1-NEXT: ret void 209 // 210 // 211 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 212 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] { 213 // CHECK1-NEXT: entry: 214 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 215 // CHECK1-NEXT: ret void 216 // 217 // 218 // CHECK3-LABEL: define {{[^@]+}}@main 219 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 220 // CHECK3-NEXT: entry: 221 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 222 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 223 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 224 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 1 dereferenceable(1) [[REF_TMP]]) 225 // CHECK3-NEXT: ret i32 0 226 // 227 // 228 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91 229 // CHECK3-SAME: (i32 [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 230 // CHECK3-NEXT: entry: 231 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32, align 4 232 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 233 // CHECK3-NEXT: [[G_CASTED:%.*]] = alloca i32, align 4 234 // CHECK3-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 235 // CHECK3-NEXT: store i32 [[G]], ptr [[G_ADDR]], align 4 236 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 237 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4 238 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[G_CASTED]], align 4 239 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[G_CASTED]], align 4 240 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 241 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 242 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 243 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1:[0-9]+]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined, i32 [[TMP1]], i32 [[TMP3]]) 244 // CHECK3-NEXT: ret void 245 // 246 // 247 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined 248 // CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 249 // CHECK3-NEXT: entry: 250 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 251 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 252 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32, align 4 253 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 254 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 255 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 256 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 257 // CHECK3-NEXT: store i32 [[G]], ptr [[G_ADDR]], align 4 258 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 259 // CHECK3-NEXT: store i32 1, ptr [[G_ADDR]], align 4 260 // CHECK3-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 261 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 262 // CHECK3-NEXT: store ptr [[G_ADDR]], ptr [[TMP0]], align 4 263 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 264 // CHECK3-NEXT: store ptr [[SIVAR_ADDR]], ptr [[TMP1]], align 4 265 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr nonnull align 4 dereferenceable(8) [[REF_TMP]]) 266 // CHECK3-NEXT: ret void 267 // 268 // 269 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 270 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] { 271 // CHECK3-NEXT: entry: 272 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 273 // CHECK3-NEXT: ret void 274 // 275 // 276 // CHECK9-LABEL: define {{[^@]+}}@main 277 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 278 // CHECK9-NEXT: entry: 279 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 280 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 281 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 282 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 283 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 284 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 285 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 286 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 287 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 288 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 289 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 290 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 291 // CHECK9-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i64, align 8 292 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x ptr], align 8 293 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x ptr], align 8 294 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x ptr], align 8 295 // CHECK9-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 296 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 297 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) 298 // CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 4 299 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) 300 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 301 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 302 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1 303 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 304 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 305 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 306 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 307 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 308 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 309 // CHECK9-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 310 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 311 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 312 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[TMP4]], align 8 313 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 314 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 315 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 316 // CHECK9-NEXT: store ptr null, ptr [[TMP6]], align 8 317 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 318 // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP7]], align 8 319 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 320 // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP8]], align 8 321 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 322 // CHECK9-NEXT: store ptr null, ptr [[TMP9]], align 8 323 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 324 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 8 325 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 326 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 8 327 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 328 // CHECK9-NEXT: store ptr null, ptr [[TMP12]], align 8 329 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 330 // CHECK9-NEXT: store ptr [[VAR]], ptr [[TMP13]], align 8 331 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 332 // CHECK9-NEXT: store ptr [[VAR]], ptr [[TMP14]], align 8 333 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 334 // CHECK9-NEXT: store ptr null, ptr [[TMP15]], align 8 335 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 336 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[TMP16]], align 8 337 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 338 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[TMP17]], align 8 339 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 340 // CHECK9-NEXT: store ptr null, ptr [[TMP18]], align 8 341 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 342 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 343 // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 344 // CHECK9-NEXT: store i32 2, ptr [[TMP21]], align 4 345 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 346 // CHECK9-NEXT: store i32 5, ptr [[TMP22]], align 4 347 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 348 // CHECK9-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8 349 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 350 // CHECK9-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8 351 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 352 // CHECK9-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 8 353 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 354 // CHECK9-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8 355 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 356 // CHECK9-NEXT: store ptr null, ptr [[TMP27]], align 8 357 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 358 // CHECK9-NEXT: store ptr null, ptr [[TMP28]], align 8 359 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 360 // CHECK9-NEXT: store i64 0, ptr [[TMP29]], align 8 361 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 362 // CHECK9-NEXT: store i64 0, ptr [[TMP30]], align 8 363 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 364 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 365 // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 366 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 367 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 368 // CHECK9-NEXT: store i32 0, ptr [[TMP33]], align 4 369 // CHECK9-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, ptr [[KERNEL_ARGS]]) 370 // CHECK9-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 371 // CHECK9-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 372 // CHECK9: omp_offload.failed: 373 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i64 [[TMP1]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]], i64 [[TMP3]]) #[[ATTR5:[0-9]+]] 374 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 375 // CHECK9: omp_offload.cont: 376 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[T_VAR]], align 4 377 // CHECK9-NEXT: store i32 [[TMP36]], ptr [[T_VAR_CASTED1]], align 4 378 // CHECK9-NEXT: [[TMP37:%.*]] = load i64, ptr [[T_VAR_CASTED1]], align 8 379 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 380 // CHECK9-NEXT: store i64 [[TMP37]], ptr [[TMP38]], align 8 381 // CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 382 // CHECK9-NEXT: store i64 [[TMP37]], ptr [[TMP39]], align 8 383 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 0 384 // CHECK9-NEXT: store ptr null, ptr [[TMP40]], align 8 385 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 386 // CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 387 // CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0 388 // CHECK9-NEXT: store i32 2, ptr [[TMP43]], align 4 389 // CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1 390 // CHECK9-NEXT: store i32 1, ptr [[TMP44]], align 4 391 // CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2 392 // CHECK9-NEXT: store ptr [[TMP41]], ptr [[TMP45]], align 8 393 // CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3 394 // CHECK9-NEXT: store ptr [[TMP42]], ptr [[TMP46]], align 8 395 // CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4 396 // CHECK9-NEXT: store ptr @.offload_sizes.1, ptr [[TMP47]], align 8 397 // CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5 398 // CHECK9-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP48]], align 8 399 // CHECK9-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6 400 // CHECK9-NEXT: store ptr null, ptr [[TMP49]], align 8 401 // CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7 402 // CHECK9-NEXT: store ptr null, ptr [[TMP50]], align 8 403 // CHECK9-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8 404 // CHECK9-NEXT: store i64 0, ptr [[TMP51]], align 8 405 // CHECK9-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9 406 // CHECK9-NEXT: store i64 0, ptr [[TMP52]], align 8 407 // CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10 408 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP53]], align 4 409 // CHECK9-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11 410 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP54]], align 4 411 // CHECK9-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12 412 // CHECK9-NEXT: store i32 0, ptr [[TMP55]], align 4 413 // CHECK9-NEXT: [[TMP56:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, ptr [[KERNEL_ARGS5]]) 414 // CHECK9-NEXT: [[TMP57:%.*]] = icmp ne i32 [[TMP56]], 0 415 // CHECK9-NEXT: br i1 [[TMP57]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 416 // CHECK9: omp_offload.failed6: 417 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i64 [[TMP37]]) #[[ATTR5]] 418 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT7]] 419 // CHECK9: omp_offload.cont7: 420 // CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() 421 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 422 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] 423 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 424 // CHECK9-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 425 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 426 // CHECK9: arraydestroy.body: 427 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP58]], [[OMP_OFFLOAD_CONT7]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 428 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 429 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] 430 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 431 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 432 // CHECK9: arraydestroy.done8: 433 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] 434 // CHECK9-NEXT: [[TMP59:%.*]] = load i32, ptr [[RETVAL]], align 4 435 // CHECK9-NEXT: ret i32 [[TMP59]] 436 // 437 // 438 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 439 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat { 440 // CHECK9-NEXT: entry: 441 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 442 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 443 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 444 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) 445 // CHECK9-NEXT: ret void 446 // 447 // 448 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 449 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 450 // CHECK9-NEXT: entry: 451 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 452 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 453 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 454 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 455 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 456 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 457 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 458 // CHECK9-NEXT: ret void 459 // 460 // 461 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 462 // CHECK9-SAME: (i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 463 // CHECK9-NEXT: entry: 464 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 465 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 466 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 467 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 468 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 469 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 470 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 471 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 472 // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 473 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 474 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 475 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 476 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 477 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 478 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 479 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 480 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 481 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 482 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 483 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 484 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8 485 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]]) 486 // CHECK9-NEXT: ret void 487 // 488 // 489 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.omp_outlined 490 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 491 // CHECK9-NEXT: entry: 492 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 493 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 494 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 495 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 496 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 497 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 498 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 499 // CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 500 // CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 501 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 502 // CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 503 // CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 504 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 505 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 506 // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 507 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 508 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 509 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 510 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 511 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 512 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 513 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 514 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) 515 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 516 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 517 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 518 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 519 // CHECK9: omp.arraycpy.body: 520 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 521 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 522 // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 523 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) 524 // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] 525 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 526 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 527 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 528 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 529 // CHECK9: omp.arraycpy.done3: 530 // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 531 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) 532 // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] 533 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 534 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 535 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 536 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 0 537 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i64 4, i1 false) 538 // CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 539 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] 540 // CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 541 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 542 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 543 // CHECK9: arraydestroy.body: 544 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 545 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 546 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] 547 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 548 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 549 // CHECK9: arraydestroy.done8: 550 // CHECK9-NEXT: ret void 551 // 552 // 553 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev 554 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 555 // CHECK9-NEXT: entry: 556 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 557 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 558 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 559 // CHECK9-NEXT: call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) 560 // CHECK9-NEXT: ret void 561 // 562 // 563 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 564 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 565 // CHECK9-NEXT: entry: 566 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 567 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 568 // CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 569 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 570 // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 571 // CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 572 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 573 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 574 // CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) 575 // CHECK9-NEXT: ret void 576 // 577 // 578 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev 579 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 580 // CHECK9-NEXT: entry: 581 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 582 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 583 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 584 // CHECK9-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] 585 // CHECK9-NEXT: ret void 586 // 587 // 588 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 589 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 590 // CHECK9-NEXT: entry: 591 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 592 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 593 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 594 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] 595 // CHECK9-NEXT: ret void 596 // 597 // 598 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 599 // CHECK9-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { 600 // CHECK9-NEXT: entry: 601 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 602 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 603 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 604 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 605 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 606 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 607 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.omp_outlined, i64 [[TMP1]]) 608 // CHECK9-NEXT: ret void 609 // 610 // 611 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.omp_outlined 612 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR4]] { 613 // CHECK9-NEXT: entry: 614 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 615 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 616 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 617 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 618 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 619 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 620 // CHECK9-NEXT: ret void 621 // 622 // 623 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 624 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] comdat { 625 // CHECK9-NEXT: entry: 626 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 627 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 628 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 629 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 630 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 631 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 632 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 633 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 634 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8 635 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8 636 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 637 // CHECK9-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i64, align 8 638 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x ptr], align 8 639 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x ptr], align 8 640 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x ptr], align 8 641 // CHECK9-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 642 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) 643 // CHECK9-NEXT: store i32 0, ptr [[T_VAR]], align 128 644 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 645 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 646 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) 647 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 648 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) 649 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 signext 3) 650 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 651 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 652 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 653 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 654 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[TMP2]], align 8 655 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 656 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[TMP3]], align 8 657 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 658 // CHECK9-NEXT: store ptr null, ptr [[TMP4]], align 8 659 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 660 // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 8 661 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 662 // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP6]], align 8 663 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 664 // CHECK9-NEXT: store ptr null, ptr [[TMP7]], align 8 665 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 666 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP8]], align 8 667 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 668 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[TMP9]], align 8 669 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 670 // CHECK9-NEXT: store ptr null, ptr [[TMP10]], align 8 671 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 672 // CHECK9-NEXT: store ptr [[VAR]], ptr [[TMP11]], align 8 673 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 674 // CHECK9-NEXT: store ptr [[VAR]], ptr [[TMP12]], align 8 675 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 676 // CHECK9-NEXT: store ptr null, ptr [[TMP13]], align 8 677 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 678 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 679 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 680 // CHECK9-NEXT: store i32 2, ptr [[TMP16]], align 4 681 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 682 // CHECK9-NEXT: store i32 4, ptr [[TMP17]], align 4 683 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 684 // CHECK9-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 685 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 686 // CHECK9-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 687 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 688 // CHECK9-NEXT: store ptr @.offload_sizes.3, ptr [[TMP20]], align 8 689 // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 690 // CHECK9-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP21]], align 8 691 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 692 // CHECK9-NEXT: store ptr null, ptr [[TMP22]], align 8 693 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 694 // CHECK9-NEXT: store ptr null, ptr [[TMP23]], align 8 695 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 696 // CHECK9-NEXT: store i64 0, ptr [[TMP24]], align 8 697 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 698 // CHECK9-NEXT: store i64 0, ptr [[TMP25]], align 8 699 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 700 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 701 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 702 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 703 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 704 // CHECK9-NEXT: store i32 0, ptr [[TMP28]], align 4 705 // CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, ptr [[KERNEL_ARGS]]) 706 // CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 707 // CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 708 // CHECK9: omp_offload.failed: 709 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i64 [[TMP1]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) #[[ATTR5]] 710 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] 711 // CHECK9: omp_offload.cont: 712 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[T_VAR]], align 128 713 // CHECK9-NEXT: store i32 [[TMP31]], ptr [[T_VAR_CASTED1]], align 4 714 // CHECK9-NEXT: [[TMP32:%.*]] = load i64, ptr [[T_VAR_CASTED1]], align 8 715 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 716 // CHECK9-NEXT: store i64 [[TMP32]], ptr [[TMP33]], align 8 717 // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 718 // CHECK9-NEXT: store i64 [[TMP32]], ptr [[TMP34]], align 8 719 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i64 0, i64 0 720 // CHECK9-NEXT: store ptr null, ptr [[TMP35]], align 8 721 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 722 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 723 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0 724 // CHECK9-NEXT: store i32 2, ptr [[TMP38]], align 4 725 // CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1 726 // CHECK9-NEXT: store i32 1, ptr [[TMP39]], align 4 727 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2 728 // CHECK9-NEXT: store ptr [[TMP36]], ptr [[TMP40]], align 8 729 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3 730 // CHECK9-NEXT: store ptr [[TMP37]], ptr [[TMP41]], align 8 731 // CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4 732 // CHECK9-NEXT: store ptr @.offload_sizes.5, ptr [[TMP42]], align 8 733 // CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5 734 // CHECK9-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP43]], align 8 735 // CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6 736 // CHECK9-NEXT: store ptr null, ptr [[TMP44]], align 8 737 // CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7 738 // CHECK9-NEXT: store ptr null, ptr [[TMP45]], align 8 739 // CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8 740 // CHECK9-NEXT: store i64 0, ptr [[TMP46]], align 8 741 // CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9 742 // CHECK9-NEXT: store i64 0, ptr [[TMP47]], align 8 743 // CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10 744 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP48]], align 4 745 // CHECK9-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11 746 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP49]], align 4 747 // CHECK9-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12 748 // CHECK9-NEXT: store i32 0, ptr [[TMP50]], align 4 749 // CHECK9-NEXT: [[TMP51:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, ptr [[KERNEL_ARGS5]]) 750 // CHECK9-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0 751 // CHECK9-NEXT: br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 752 // CHECK9: omp_offload.failed6: 753 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i64 [[TMP32]]) #[[ATTR5]] 754 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT7]] 755 // CHECK9: omp_offload.cont7: 756 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 757 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] 758 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 759 // CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 760 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 761 // CHECK9: arraydestroy.body: 762 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP53]], [[OMP_OFFLOAD_CONT7]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 763 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 764 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] 765 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 766 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 767 // CHECK9: arraydestroy.done8: 768 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] 769 // CHECK9-NEXT: [[TMP54:%.*]] = load i32, ptr [[RETVAL]], align 4 770 // CHECK9-NEXT: ret i32 [[TMP54]] 771 // 772 // 773 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 774 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 775 // CHECK9-NEXT: entry: 776 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 777 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 778 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 779 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 780 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 781 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 782 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 783 // CHECK9-NEXT: ret void 784 // 785 // 786 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 787 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 788 // CHECK9-NEXT: entry: 789 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 790 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 791 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 792 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 793 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 794 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 795 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 796 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 797 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 798 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 799 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 800 // CHECK9-NEXT: ret void 801 // 802 // 803 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev 804 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 805 // CHECK9-NEXT: entry: 806 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 807 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 808 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 809 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 810 // CHECK9-NEXT: store i32 0, ptr [[A]], align 4 811 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 812 // CHECK9-NEXT: store i32 0, ptr [[B]], align 4 813 // CHECK9-NEXT: ret void 814 // 815 // 816 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 817 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 818 // CHECK9-NEXT: entry: 819 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 820 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 821 // CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 822 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 823 // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 824 // CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 825 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 826 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 827 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 828 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 829 // CHECK9-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 830 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 831 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 832 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 833 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 834 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 835 // CHECK9-NEXT: ret void 836 // 837 // 838 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev 839 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 840 // CHECK9-NEXT: entry: 841 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 842 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 843 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 844 // CHECK9-NEXT: ret void 845 // 846 // 847 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 848 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 849 // CHECK9-NEXT: entry: 850 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 851 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 852 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 853 // CHECK9-NEXT: ret void 854 // 855 // 856 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 857 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 858 // CHECK9-NEXT: entry: 859 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 860 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 861 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 862 // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) 863 // CHECK9-NEXT: ret void 864 // 865 // 866 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 867 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 868 // CHECK9-NEXT: entry: 869 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 870 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 871 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 872 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 873 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 874 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 875 // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) 876 // CHECK9-NEXT: ret void 877 // 878 // 879 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 880 // CHECK9-SAME: (i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 881 // CHECK9-NEXT: entry: 882 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 883 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 884 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 885 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 886 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 887 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 888 // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 889 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 890 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 891 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 892 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 893 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 894 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 895 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 896 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 897 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]]) 898 // CHECK9-NEXT: ret void 899 // 900 // 901 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.omp_outlined 902 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 903 // CHECK9-NEXT: entry: 904 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 905 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 906 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 907 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 908 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 909 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 910 // CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 128 911 // CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128 912 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 913 // CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 914 // CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 915 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 916 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 917 // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 918 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 919 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 920 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 921 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 922 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 923 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 924 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i64 8, i1 false) 925 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 926 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 927 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 928 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 929 // CHECK9: omp.arraycpy.body: 930 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 931 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 932 // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 933 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) 934 // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] 935 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 936 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 937 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 938 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 939 // CHECK9: omp.arraycpy.done3: 940 // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 941 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) 942 // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] 943 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 944 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 945 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128 946 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i64 0, i64 0 947 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i64 4, i1 false) 948 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] 949 // CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 950 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 951 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 952 // CHECK9: arraydestroy.body: 953 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 954 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 955 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] 956 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 957 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 958 // CHECK9: arraydestroy.done8: 959 // CHECK9-NEXT: ret void 960 // 961 // 962 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 963 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 964 // CHECK9-NEXT: entry: 965 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 966 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 967 // CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 968 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 969 // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 970 // CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 971 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 972 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 973 // CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) 974 // CHECK9-NEXT: ret void 975 // 976 // 977 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 978 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 979 // CHECK9-NEXT: entry: 980 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 981 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 982 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 983 // CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] 984 // CHECK9-NEXT: ret void 985 // 986 // 987 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 988 // CHECK9-SAME: (i64 [[T_VAR:%.*]]) #[[ATTR3]] { 989 // CHECK9-NEXT: entry: 990 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 991 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 992 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 993 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 994 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 995 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 996 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, i64 [[TMP1]]) 997 // CHECK9-NEXT: ret void 998 // 999 // 1000 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined 1001 // CHECK9-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR4]] { 1002 // CHECK9-NEXT: entry: 1003 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1004 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1005 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 1006 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1007 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1008 // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 1009 // CHECK9-NEXT: ret void 1010 // 1011 // 1012 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1013 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1014 // CHECK9-NEXT: entry: 1015 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1016 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1017 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1018 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1019 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 1020 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1021 // CHECK9-NEXT: ret void 1022 // 1023 // 1024 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1025 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1026 // CHECK9-NEXT: entry: 1027 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1028 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1029 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1030 // CHECK9-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1031 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1032 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1033 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1034 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 1035 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1036 // CHECK9-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1037 // CHECK9-NEXT: ret void 1038 // 1039 // 1040 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1041 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1042 // CHECK9-NEXT: entry: 1043 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1044 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 1045 // CHECK9-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8 1046 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1047 // CHECK9-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 1048 // CHECK9-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8 1049 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1050 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1051 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 1052 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 1053 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 1054 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1055 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1056 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1057 // CHECK9-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1058 // CHECK9-NEXT: ret void 1059 // 1060 // 1061 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1062 // CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { 1063 // CHECK9-NEXT: entry: 1064 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1065 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1066 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1067 // CHECK9-NEXT: ret void 1068 // 1069 // 1070 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1071 // CHECK9-SAME: () #[[ATTR7:[0-9]+]] { 1072 // CHECK9-NEXT: entry: 1073 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 1074 // CHECK9-NEXT: ret void 1075 // 1076 // 1077 // CHECK11-LABEL: define {{[^@]+}}@main 1078 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 1079 // CHECK11-NEXT: entry: 1080 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1081 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1082 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1083 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1084 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1085 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 1086 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1087 // CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1088 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 1089 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 1090 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 1091 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1092 // CHECK11-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 1093 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x ptr], align 4 1094 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x ptr], align 4 1095 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x ptr], align 4 1096 // CHECK11-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1097 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 1098 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) 1099 // CHECK11-NEXT: store i32 0, ptr [[T_VAR]], align 4 1100 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false) 1101 // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1102 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 1103 // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i32 1 1104 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 1105 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 1106 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 1107 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1108 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1109 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 1110 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4 1111 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1112 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1113 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[TMP4]], align 4 1114 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1115 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 1116 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1117 // CHECK11-NEXT: store ptr null, ptr [[TMP6]], align 4 1118 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1119 // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP7]], align 4 1120 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1121 // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP8]], align 4 1122 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1123 // CHECK11-NEXT: store ptr null, ptr [[TMP9]], align 4 1124 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1125 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 4 1126 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1127 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 4 1128 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1129 // CHECK11-NEXT: store ptr null, ptr [[TMP12]], align 4 1130 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1131 // CHECK11-NEXT: store ptr [[VAR]], ptr [[TMP13]], align 4 1132 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1133 // CHECK11-NEXT: store ptr [[VAR]], ptr [[TMP14]], align 4 1134 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1135 // CHECK11-NEXT: store ptr null, ptr [[TMP15]], align 4 1136 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1137 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[TMP16]], align 4 1138 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1139 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[TMP17]], align 4 1140 // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1141 // CHECK11-NEXT: store ptr null, ptr [[TMP18]], align 4 1142 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1143 // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1144 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1145 // CHECK11-NEXT: store i32 2, ptr [[TMP21]], align 4 1146 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1147 // CHECK11-NEXT: store i32 5, ptr [[TMP22]], align 4 1148 // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1149 // CHECK11-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4 1150 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1151 // CHECK11-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4 1152 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1153 // CHECK11-NEXT: store ptr @.offload_sizes, ptr [[TMP25]], align 4 1154 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1155 // CHECK11-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 4 1156 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1157 // CHECK11-NEXT: store ptr null, ptr [[TMP27]], align 4 1158 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1159 // CHECK11-NEXT: store ptr null, ptr [[TMP28]], align 4 1160 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1161 // CHECK11-NEXT: store i64 0, ptr [[TMP29]], align 8 1162 // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1163 // CHECK11-NEXT: store i64 0, ptr [[TMP30]], align 8 1164 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1165 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4 1166 // CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1167 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4 1168 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1169 // CHECK11-NEXT: store i32 0, ptr [[TMP33]], align 4 1170 // CHECK11-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.region_id, ptr [[KERNEL_ARGS]]) 1171 // CHECK11-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1172 // CHECK11-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1173 // CHECK11: omp_offload.failed: 1174 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109(i32 [[TMP1]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]], i32 [[TMP3]]) #[[ATTR5:[0-9]+]] 1175 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1176 // CHECK11: omp_offload.cont: 1177 // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[T_VAR]], align 4 1178 // CHECK11-NEXT: store i32 [[TMP36]], ptr [[T_VAR_CASTED1]], align 4 1179 // CHECK11-NEXT: [[TMP37:%.*]] = load i32, ptr [[T_VAR_CASTED1]], align 4 1180 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1181 // CHECK11-NEXT: store i32 [[TMP37]], ptr [[TMP38]], align 4 1182 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1183 // CHECK11-NEXT: store i32 [[TMP37]], ptr [[TMP39]], align 4 1184 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 1185 // CHECK11-NEXT: store ptr null, ptr [[TMP40]], align 4 1186 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1187 // CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1188 // CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0 1189 // CHECK11-NEXT: store i32 2, ptr [[TMP43]], align 4 1190 // CHECK11-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1 1191 // CHECK11-NEXT: store i32 1, ptr [[TMP44]], align 4 1192 // CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2 1193 // CHECK11-NEXT: store ptr [[TMP41]], ptr [[TMP45]], align 4 1194 // CHECK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3 1195 // CHECK11-NEXT: store ptr [[TMP42]], ptr [[TMP46]], align 4 1196 // CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4 1197 // CHECK11-NEXT: store ptr @.offload_sizes.1, ptr [[TMP47]], align 4 1198 // CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5 1199 // CHECK11-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP48]], align 4 1200 // CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6 1201 // CHECK11-NEXT: store ptr null, ptr [[TMP49]], align 4 1202 // CHECK11-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7 1203 // CHECK11-NEXT: store ptr null, ptr [[TMP50]], align 4 1204 // CHECK11-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8 1205 // CHECK11-NEXT: store i64 0, ptr [[TMP51]], align 8 1206 // CHECK11-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9 1207 // CHECK11-NEXT: store i64 0, ptr [[TMP52]], align 8 1208 // CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10 1209 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP53]], align 4 1210 // CHECK11-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11 1211 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP54]], align 4 1212 // CHECK11-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12 1213 // CHECK11-NEXT: store i32 0, ptr [[TMP55]], align 4 1214 // CHECK11-NEXT: [[TMP56:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.region_id, ptr [[KERNEL_ARGS5]]) 1215 // CHECK11-NEXT: [[TMP57:%.*]] = icmp ne i32 [[TMP56]], 0 1216 // CHECK11-NEXT: br i1 [[TMP57]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 1217 // CHECK11: omp_offload.failed6: 1218 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116(i32 [[TMP37]]) #[[ATTR5]] 1219 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT7]] 1220 // CHECK11: omp_offload.cont7: 1221 // CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1222 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 1223 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] 1224 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1225 // CHECK11-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1226 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1227 // CHECK11: arraydestroy.body: 1228 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP58]], [[OMP_OFFLOAD_CONT7]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1229 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1230 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] 1231 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1232 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1233 // CHECK11: arraydestroy.done8: 1234 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] 1235 // CHECK11-NEXT: [[TMP59:%.*]] = load i32, ptr [[RETVAL]], align 4 1236 // CHECK11-NEXT: ret i32 [[TMP59]] 1237 // 1238 // 1239 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1240 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1241 // CHECK11-NEXT: entry: 1242 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1243 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1244 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1245 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) 1246 // CHECK11-NEXT: ret void 1247 // 1248 // 1249 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1250 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1251 // CHECK11-NEXT: entry: 1252 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1253 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1254 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1255 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1256 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1257 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1258 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1259 // CHECK11-NEXT: ret void 1260 // 1261 // 1262 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109 1263 // CHECK11-SAME: (i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 1264 // CHECK11-NEXT: entry: 1265 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1266 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1267 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1268 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1269 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1270 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1271 // CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1272 // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1273 // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1274 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1275 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1276 // CHECK11-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1277 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1278 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1279 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1280 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1281 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1282 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1283 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 1284 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4 1285 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4 1286 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]]) 1287 // CHECK11-NEXT: ret void 1288 // 1289 // 1290 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l109.omp_outlined 1291 // CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1292 // CHECK11-NEXT: entry: 1293 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1294 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1295 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1296 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1297 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1298 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1299 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1300 // CHECK11-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1301 // CHECK11-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1302 // CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1303 // CHECK11-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1304 // CHECK11-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1305 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1306 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1307 // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1308 // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1309 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1310 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1311 // CHECK11-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 1312 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1313 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1314 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1315 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) 1316 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1317 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1318 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1319 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1320 // CHECK11: omp.arraycpy.body: 1321 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1322 // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1323 // CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1324 // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) 1325 // CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] 1326 // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1327 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1328 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1329 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1330 // CHECK11: omp.arraycpy.done3: 1331 // CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1332 // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) 1333 // CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] 1334 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1335 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 1336 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 1337 // CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1338 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i32 4, i1 false) 1339 // CHECK11-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 1340 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] 1341 // CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 1342 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 1343 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1344 // CHECK11: arraydestroy.body: 1345 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1346 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1347 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] 1348 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 1349 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1350 // CHECK11: arraydestroy.done8: 1351 // CHECK11-NEXT: ret void 1352 // 1353 // 1354 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1355 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1356 // CHECK11-NEXT: entry: 1357 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1358 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1359 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1360 // CHECK11-NEXT: call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) 1361 // CHECK11-NEXT: ret void 1362 // 1363 // 1364 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1365 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1366 // CHECK11-NEXT: entry: 1367 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1368 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1369 // CHECK11-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1370 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1371 // CHECK11-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1372 // CHECK11-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1373 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1374 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1375 // CHECK11-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) 1376 // CHECK11-NEXT: ret void 1377 // 1378 // 1379 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1380 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1381 // CHECK11-NEXT: entry: 1382 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1383 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1384 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1385 // CHECK11-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]] 1386 // CHECK11-NEXT: ret void 1387 // 1388 // 1389 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1390 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1391 // CHECK11-NEXT: entry: 1392 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1393 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1394 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1395 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] 1396 // CHECK11-NEXT: ret void 1397 // 1398 // 1399 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116 1400 // CHECK11-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] { 1401 // CHECK11-NEXT: entry: 1402 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1403 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1404 // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1405 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1406 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1407 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1408 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.omp_outlined, i32 [[TMP1]]) 1409 // CHECK11-NEXT: ret void 1410 // 1411 // 1412 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l116.omp_outlined 1413 // CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR4]] { 1414 // CHECK11-NEXT: entry: 1415 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1416 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1417 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1418 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1419 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1420 // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1421 // CHECK11-NEXT: ret void 1422 // 1423 // 1424 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1425 // CHECK11-SAME: () #[[ATTR6:[0-9]+]] comdat { 1426 // CHECK11-NEXT: entry: 1427 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1428 // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1429 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 1430 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 1431 // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 1432 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 1433 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1434 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 1435 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4 1436 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4 1437 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1438 // CHECK11-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 1439 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [1 x ptr], align 4 1440 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [1 x ptr], align 4 1441 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [1 x ptr], align 4 1442 // CHECK11-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1443 // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) 1444 // CHECK11-NEXT: store i32 0, ptr [[T_VAR]], align 128 1445 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC]], ptr align 128 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1446 // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1447 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 1448 // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1 1449 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 1450 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 1451 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 1452 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1453 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1454 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1455 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[TMP2]], align 4 1456 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1457 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4 1458 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1459 // CHECK11-NEXT: store ptr null, ptr [[TMP4]], align 4 1460 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1461 // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 4 1462 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1463 // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP6]], align 4 1464 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1465 // CHECK11-NEXT: store ptr null, ptr [[TMP7]], align 4 1466 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1467 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP8]], align 4 1468 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1469 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[TMP9]], align 4 1470 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1471 // CHECK11-NEXT: store ptr null, ptr [[TMP10]], align 4 1472 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1473 // CHECK11-NEXT: store ptr [[VAR]], ptr [[TMP11]], align 4 1474 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1475 // CHECK11-NEXT: store ptr [[VAR]], ptr [[TMP12]], align 4 1476 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1477 // CHECK11-NEXT: store ptr null, ptr [[TMP13]], align 4 1478 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1479 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1480 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1481 // CHECK11-NEXT: store i32 2, ptr [[TMP16]], align 4 1482 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1483 // CHECK11-NEXT: store i32 4, ptr [[TMP17]], align 4 1484 // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1485 // CHECK11-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 1486 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1487 // CHECK11-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 1488 // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1489 // CHECK11-NEXT: store ptr @.offload_sizes.3, ptr [[TMP20]], align 4 1490 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1491 // CHECK11-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP21]], align 4 1492 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1493 // CHECK11-NEXT: store ptr null, ptr [[TMP22]], align 4 1494 // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1495 // CHECK11-NEXT: store ptr null, ptr [[TMP23]], align 4 1496 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1497 // CHECK11-NEXT: store i64 0, ptr [[TMP24]], align 8 1498 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1499 // CHECK11-NEXT: store i64 0, ptr [[TMP25]], align 8 1500 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1501 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 1502 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1503 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 1504 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1505 // CHECK11-NEXT: store i32 0, ptr [[TMP28]], align 4 1506 // CHECK11-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.region_id, ptr [[KERNEL_ARGS]]) 1507 // CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1508 // CHECK11-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1509 // CHECK11: omp_offload.failed: 1510 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75(i32 [[TMP1]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) #[[ATTR5]] 1511 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] 1512 // CHECK11: omp_offload.cont: 1513 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[T_VAR]], align 128 1514 // CHECK11-NEXT: store i32 [[TMP31]], ptr [[T_VAR_CASTED1]], align 4 1515 // CHECK11-NEXT: [[TMP32:%.*]] = load i32, ptr [[T_VAR_CASTED1]], align 4 1516 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1517 // CHECK11-NEXT: store i32 [[TMP32]], ptr [[TMP33]], align 4 1518 // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1519 // CHECK11-NEXT: store i32 [[TMP32]], ptr [[TMP34]], align 4 1520 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 1521 // CHECK11-NEXT: store ptr null, ptr [[TMP35]], align 4 1522 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 1523 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 1524 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0 1525 // CHECK11-NEXT: store i32 2, ptr [[TMP38]], align 4 1526 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1 1527 // CHECK11-NEXT: store i32 1, ptr [[TMP39]], align 4 1528 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2 1529 // CHECK11-NEXT: store ptr [[TMP36]], ptr [[TMP40]], align 4 1530 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3 1531 // CHECK11-NEXT: store ptr [[TMP37]], ptr [[TMP41]], align 4 1532 // CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4 1533 // CHECK11-NEXT: store ptr @.offload_sizes.5, ptr [[TMP42]], align 4 1534 // CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5 1535 // CHECK11-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP43]], align 4 1536 // CHECK11-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6 1537 // CHECK11-NEXT: store ptr null, ptr [[TMP44]], align 4 1538 // CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7 1539 // CHECK11-NEXT: store ptr null, ptr [[TMP45]], align 4 1540 // CHECK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8 1541 // CHECK11-NEXT: store i64 0, ptr [[TMP46]], align 8 1542 // CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9 1543 // CHECK11-NEXT: store i64 0, ptr [[TMP47]], align 8 1544 // CHECK11-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10 1545 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP48]], align 4 1546 // CHECK11-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11 1547 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP49]], align 4 1548 // CHECK11-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12 1549 // CHECK11-NEXT: store i32 0, ptr [[TMP50]], align 4 1550 // CHECK11-NEXT: [[TMP51:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.region_id, ptr [[KERNEL_ARGS5]]) 1551 // CHECK11-NEXT: [[TMP52:%.*]] = icmp ne i32 [[TMP51]], 0 1552 // CHECK11-NEXT: br i1 [[TMP52]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 1553 // CHECK11: omp_offload.failed6: 1554 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81(i32 [[TMP32]]) #[[ATTR5]] 1555 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT7]] 1556 // CHECK11: omp_offload.cont7: 1557 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 1558 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] 1559 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1560 // CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1561 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1562 // CHECK11: arraydestroy.body: 1563 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP53]], [[OMP_OFFLOAD_CONT7]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1564 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1565 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] 1566 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1567 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1568 // CHECK11: arraydestroy.done8: 1569 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] 1570 // CHECK11-NEXT: [[TMP54:%.*]] = load i32, ptr [[RETVAL]], align 4 1571 // CHECK11-NEXT: ret i32 [[TMP54]] 1572 // 1573 // 1574 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1575 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1576 // CHECK11-NEXT: entry: 1577 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1578 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1579 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1580 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1581 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 1582 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1583 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 1584 // CHECK11-NEXT: ret void 1585 // 1586 // 1587 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1588 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1589 // CHECK11-NEXT: entry: 1590 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1591 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1592 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1593 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1594 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1595 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1596 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1597 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 1598 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1599 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1600 // CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 4 1601 // CHECK11-NEXT: ret void 1602 // 1603 // 1604 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1605 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1606 // CHECK11-NEXT: entry: 1607 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1608 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1609 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1610 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 1611 // CHECK11-NEXT: store i32 0, ptr [[A]], align 4 1612 // CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 1613 // CHECK11-NEXT: store i32 0, ptr [[B]], align 4 1614 // CHECK11-NEXT: ret void 1615 // 1616 // 1617 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1618 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1619 // CHECK11-NEXT: entry: 1620 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1621 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1622 // CHECK11-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1623 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1624 // CHECK11-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1625 // CHECK11-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1626 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1627 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1628 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1629 // CHECK11-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 1630 // CHECK11-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 1631 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1632 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1633 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1634 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1635 // CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 4 1636 // CHECK11-NEXT: ret void 1637 // 1638 // 1639 // CHECK11-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1640 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1641 // CHECK11-NEXT: entry: 1642 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1643 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1644 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1645 // CHECK11-NEXT: ret void 1646 // 1647 // 1648 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1649 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1650 // CHECK11-NEXT: entry: 1651 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1652 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1653 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1654 // CHECK11-NEXT: ret void 1655 // 1656 // 1657 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1658 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1659 // CHECK11-NEXT: entry: 1660 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1661 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1662 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1663 // CHECK11-NEXT: call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) 1664 // CHECK11-NEXT: ret void 1665 // 1666 // 1667 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1668 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1669 // CHECK11-NEXT: entry: 1670 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1671 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1672 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1673 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1674 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1675 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1676 // CHECK11-NEXT: call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 1677 // CHECK11-NEXT: ret void 1678 // 1679 // 1680 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75 1681 // CHECK11-SAME: (i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1682 // CHECK11-NEXT: entry: 1683 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1684 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1685 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1686 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1687 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1688 // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1689 // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1690 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1691 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1692 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1693 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1694 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1695 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1696 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 1697 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1698 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]]) 1699 // CHECK11-NEXT: ret void 1700 // 1701 // 1702 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l75.omp_outlined 1703 // CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { 1704 // CHECK11-NEXT: entry: 1705 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1706 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1707 // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4 1708 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1709 // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 1710 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 1711 // CHECK11-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 128 1712 // CHECK11-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128 1713 // CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1714 // CHECK11-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 1715 // CHECK11-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1716 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1717 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1718 // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 1719 // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1720 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 1721 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 1722 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 1723 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 1724 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 1725 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i32 8, i1 false) 1726 // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 1727 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1728 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] 1729 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1730 // CHECK11: omp.arraycpy.body: 1731 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1732 // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1733 // CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1734 // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) 1735 // CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR5]] 1736 // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1737 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1738 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 1739 // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1740 // CHECK11: omp.arraycpy.done3: 1741 // CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1742 // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) 1743 // CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR5]] 1744 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1745 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 1746 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128 1747 // CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 1748 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i32 4, i1 false) 1749 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] 1750 // CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 1751 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i32 2 1752 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1753 // CHECK11: arraydestroy.body: 1754 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1755 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1756 // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] 1757 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 1758 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1759 // CHECK11: arraydestroy.done8: 1760 // CHECK11-NEXT: ret void 1761 // 1762 // 1763 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1764 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1765 // CHECK11-NEXT: entry: 1766 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1767 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1768 // CHECK11-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1769 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1770 // CHECK11-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1771 // CHECK11-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1772 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1773 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1774 // CHECK11-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) 1775 // CHECK11-NEXT: ret void 1776 // 1777 // 1778 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1779 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1780 // CHECK11-NEXT: entry: 1781 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1782 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1783 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1784 // CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] 1785 // CHECK11-NEXT: ret void 1786 // 1787 // 1788 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81 1789 // CHECK11-SAME: (i32 [[T_VAR:%.*]]) #[[ATTR3]] { 1790 // CHECK11-NEXT: entry: 1791 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1792 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 1793 // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1794 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 1795 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4 1796 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 1797 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined, i32 [[TMP1]]) 1798 // CHECK11-NEXT: ret void 1799 // 1800 // 1801 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l81.omp_outlined 1802 // CHECK11-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR4]] { 1803 // CHECK11-NEXT: entry: 1804 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1805 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1806 // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1807 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1808 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1809 // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 1810 // CHECK11-NEXT: ret void 1811 // 1812 // 1813 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1814 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1815 // CHECK11-NEXT: entry: 1816 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1817 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1818 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1819 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1820 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 128 1821 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1822 // CHECK11-NEXT: ret void 1823 // 1824 // 1825 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1826 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1827 // CHECK11-NEXT: entry: 1828 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1829 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1830 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1831 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1832 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1833 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1834 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1835 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 128 1836 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1837 // CHECK11-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1838 // CHECK11-NEXT: ret void 1839 // 1840 // 1841 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1842 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1843 // CHECK11-NEXT: entry: 1844 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1845 // CHECK11-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 1846 // CHECK11-NEXT: [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4 1847 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1848 // CHECK11-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 1849 // CHECK11-NEXT: store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4 1850 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1851 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1852 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4 1853 // CHECK11-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 1854 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 1855 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 1856 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1857 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1858 // CHECK11-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1859 // CHECK11-NEXT: ret void 1860 // 1861 // 1862 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1863 // CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1864 // CHECK11-NEXT: entry: 1865 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1866 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1867 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1868 // CHECK11-NEXT: ret void 1869 // 1870 // 1871 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1872 // CHECK11-SAME: () #[[ATTR7:[0-9]+]] { 1873 // CHECK11-NEXT: entry: 1874 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) 1875 // CHECK11-NEXT: ret void 1876 // 1877 // 1878 // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPg 1879 // CHECK17-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i32 signext [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 1880 // CHECK17-NEXT: entry: 1881 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 1882 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 1883 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1884 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 1885 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 1886 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1887 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1888 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1889 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x ptr], align 8 1890 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x ptr], align 8 1891 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x ptr], align 8 1892 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 8 1893 // CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1894 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 1895 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 1896 // CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1897 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 1898 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1899 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1900 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 1901 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 1902 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 1903 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 1904 // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave.p0() 1905 // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 1906 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 1907 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 1908 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8 1909 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 1910 // CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[A_ADDR]], align 8 1911 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8 1912 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 1913 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[N_ADDR]], align 4 1914 // CHECK17-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4 1915 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[N_CASTED]], align 8 1916 // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 1917 // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 1918 // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 64, i1 false) 1919 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1920 // CHECK17-NEXT: store ptr [[TMP8]], ptr [[TMP15]], align 8 1921 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1922 // CHECK17-NEXT: store ptr [[TMP8]], ptr [[TMP16]], align 8 1923 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1924 // CHECK17-NEXT: store ptr null, ptr [[TMP17]], align 8 1925 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1926 // CHECK17-NEXT: store ptr [[TMP9]], ptr [[TMP18]], align 8 1927 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1928 // CHECK17-NEXT: store ptr [[TMP9]], ptr [[TMP19]], align 8 1929 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1930 // CHECK17-NEXT: store ptr null, ptr [[TMP20]], align 8 1931 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1932 // CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP21]], align 8 1933 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1934 // CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP22]], align 8 1935 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1936 // CHECK17-NEXT: store ptr null, ptr [[TMP23]], align 8 1937 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1938 // CHECK17-NEXT: store ptr [[TMP10]], ptr [[TMP24]], align 8 1939 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1940 // CHECK17-NEXT: store ptr [[TMP10]], ptr [[TMP25]], align 8 1941 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1942 // CHECK17-NEXT: store ptr null, ptr [[TMP26]], align 8 1943 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1944 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP27]], align 8 1945 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1946 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP28]], align 8 1947 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1948 // CHECK17-NEXT: store ptr null, ptr [[TMP29]], align 8 1949 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 1950 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP30]], align 8 1951 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 1952 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP31]], align 8 1953 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 1954 // CHECK17-NEXT: store ptr null, ptr [[TMP32]], align 8 1955 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 1956 // CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP33]], align 8 1957 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6 1958 // CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP34]], align 8 1959 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 6 1960 // CHECK17-NEXT: store i64 [[TMP14]], ptr [[TMP35]], align 8 1961 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 1962 // CHECK17-NEXT: store ptr null, ptr [[TMP36]], align 8 1963 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 1964 // CHECK17-NEXT: store i64 [[TMP12]], ptr [[TMP37]], align 8 1965 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7 1966 // CHECK17-NEXT: store i64 [[TMP12]], ptr [[TMP38]], align 8 1967 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 1968 // CHECK17-NEXT: store ptr null, ptr [[TMP39]], align 8 1969 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1970 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1971 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [8 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1972 // CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1973 // CHECK17-NEXT: store i32 2, ptr [[TMP43]], align 4 1974 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1975 // CHECK17-NEXT: store i32 8, ptr [[TMP44]], align 4 1976 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1977 // CHECK17-NEXT: store ptr [[TMP40]], ptr [[TMP45]], align 8 1978 // CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1979 // CHECK17-NEXT: store ptr [[TMP41]], ptr [[TMP46]], align 8 1980 // CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1981 // CHECK17-NEXT: store ptr [[TMP42]], ptr [[TMP47]], align 8 1982 // CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1983 // CHECK17-NEXT: store ptr @.offload_maptypes, ptr [[TMP48]], align 8 1984 // CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1985 // CHECK17-NEXT: store ptr null, ptr [[TMP49]], align 8 1986 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1987 // CHECK17-NEXT: store ptr null, ptr [[TMP50]], align 8 1988 // CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1989 // CHECK17-NEXT: store i64 0, ptr [[TMP51]], align 8 1990 // CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 1991 // CHECK17-NEXT: store i64 0, ptr [[TMP52]], align 8 1992 // CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 1993 // CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP53]], align 4 1994 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 1995 // CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP54]], align 4 1996 // CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 1997 // CHECK17-NEXT: store i32 0, ptr [[TMP55]], align 4 1998 // CHECK17-NEXT: [[TMP56:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.region_id, ptr [[KERNEL_ARGS]]) 1999 // CHECK17-NEXT: [[TMP57:%.*]] = icmp ne i32 [[TMP56]], 0 2000 // CHECK17-NEXT: br i1 [[TMP57]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2001 // CHECK17: omp_offload.failed: 2002 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152(ptr [[TMP8]], ptr [[TMP9]], i64 [[TMP1]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], i64 [[TMP12]]) #[[ATTR5:[0-9]+]] 2003 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 2004 // CHECK17: omp_offload.cont: 2005 // CHECK17-NEXT: [[TMP58:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 2006 // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP58]]) 2007 // CHECK17-NEXT: ret void 2008 // 2009 // 2010 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152 2011 // CHECK17-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i64 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 2012 // CHECK17-NEXT: entry: 2013 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2014 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 2015 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2016 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 2017 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 2018 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 2019 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 8 2020 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 2021 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2022 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 2023 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 2024 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 2025 // CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8 2026 // CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8 2027 // CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8 2028 // CHECK17-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 2029 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 2030 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 2031 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 2032 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 2033 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[S_ADDR]], align 8 2034 // CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 2035 // CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[A_ADDR]], align 8 2036 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 8, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.omp_outlined, ptr [[TMP4]], ptr [[N_ADDR]], i64 [[TMP0]], ptr [[TMP5]], ptr [[TMP6]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) 2037 // CHECK17-NEXT: ret void 2038 // 2039 // 2040 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPg_l152.omp_outlined 2041 // CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[S:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR3:[0-9]+]] { 2042 // CHECK17-NEXT: entry: 2043 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2044 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2045 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 2046 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 2047 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2048 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 2049 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 2050 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 2051 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 2052 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 8 2053 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 2054 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2055 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 2056 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2057 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2058 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 2059 // CHECK17-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 2060 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 2061 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 2062 // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 2063 // CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8 2064 // CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8 2065 // CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8 2066 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8 2067 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 2068 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 2069 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 2070 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 2071 // CHECK17-NEXT: [[TMP5:%.*]] = call ptr @llvm.stacksave.p0() 2072 // CHECK17-NEXT: store ptr [[TMP5]], ptr [[SAVED_STACK]], align 8 2073 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 2074 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 2075 // CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 2076 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 2077 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 2078 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 2079 // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP8]], i1 false) 2080 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8 2081 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i64 0 2082 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 8 2083 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 4 2084 // CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 2085 // CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPg(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 signext [[TMP11]], ptr [[TMP12]]) 2086 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 2087 // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]]) 2088 // CHECK17-NEXT: ret void 2089 // 2090 // 2091 // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPg 2092 // CHECK17-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 signext [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] comdat { 2093 // CHECK17-NEXT: entry: 2094 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2095 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 2096 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2097 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 2098 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 2099 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2100 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 2101 // CHECK17-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 2102 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x ptr], align 8 2103 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x ptr], align 8 2104 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x ptr], align 8 2105 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 2106 // CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2107 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2108 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 2109 // CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2110 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 2111 // CHECK17-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2112 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2113 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 2114 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 2115 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 2116 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 2117 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 2118 // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave.p0() 2119 // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 2120 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 2121 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 2122 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR0]], align 8 2123 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 2124 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 1 2125 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[B]], align 4 2126 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0 2127 // CHECK17-NEXT: store i32 [[TMP8]], ptr [[A]], align 4 2128 // CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 8 2129 // CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 2130 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[N_ADDR]], align 4 2131 // CHECK17-NEXT: store i32 [[TMP11]], ptr [[N_CASTED]], align 4 2132 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[N_CASTED]], align 8 2133 // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 2134 // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 2135 // CHECK17-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 2136 // CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0 2137 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[B2]], i32 1 2138 // CHECK17-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP15]] to i64 2139 // CHECK17-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[A3]] to i64 2140 // CHECK17-NEXT: [[TMP18:%.*]] = sub i64 [[TMP16]], [[TMP17]] 2141 // CHECK17-NEXT: [[TMP19:%.*]] = sdiv exact i64 [[TMP18]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) 2142 // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.1, i64 80, i1 false) 2143 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2144 // CHECK17-NEXT: store ptr [[TMP9]], ptr [[TMP20]], align 8 2145 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2146 // CHECK17-NEXT: store ptr [[TMP9]], ptr [[TMP21]], align 8 2147 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2148 // CHECK17-NEXT: store ptr null, ptr [[TMP22]], align 8 2149 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2150 // CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP23]], align 8 2151 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2152 // CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP24]], align 8 2153 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2154 // CHECK17-NEXT: store ptr null, ptr [[TMP25]], align 8 2155 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2156 // CHECK17-NEXT: store ptr [[TMP10]], ptr [[TMP26]], align 8 2157 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2158 // CHECK17-NEXT: store ptr [[TMP10]], ptr [[TMP27]], align 8 2159 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2160 // CHECK17-NEXT: store ptr null, ptr [[TMP28]], align 8 2161 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2162 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP29]], align 8 2163 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2164 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP30]], align 8 2165 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2166 // CHECK17-NEXT: store ptr null, ptr [[TMP31]], align 8 2167 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2168 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP32]], align 8 2169 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2170 // CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP33]], align 8 2171 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 2172 // CHECK17-NEXT: store ptr null, ptr [[TMP34]], align 8 2173 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 2174 // CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP35]], align 8 2175 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 2176 // CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP36]], align 8 2177 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 5 2178 // CHECK17-NEXT: store i64 [[TMP14]], ptr [[TMP37]], align 8 2179 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 2180 // CHECK17-NEXT: store ptr null, ptr [[TMP38]], align 8 2181 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 2182 // CHECK17-NEXT: store ptr [[THIS1]], ptr [[TMP39]], align 8 2183 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6 2184 // CHECK17-NEXT: store ptr [[A3]], ptr [[TMP40]], align 8 2185 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 6 2186 // CHECK17-NEXT: store i64 [[TMP19]], ptr [[TMP41]], align 8 2187 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6 2188 // CHECK17-NEXT: store ptr null, ptr [[TMP42]], align 8 2189 // CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 2190 // CHECK17-NEXT: store ptr [[THIS1]], ptr [[TMP43]], align 8 2191 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7 2192 // CHECK17-NEXT: store ptr [[B2]], ptr [[TMP44]], align 8 2193 // CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7 2194 // CHECK17-NEXT: store ptr null, ptr [[TMP45]], align 8 2195 // CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 2196 // CHECK17-NEXT: store ptr [[THIS1]], ptr [[TMP46]], align 8 2197 // CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8 2198 // CHECK17-NEXT: store ptr [[A3]], ptr [[TMP47]], align 8 2199 // CHECK17-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8 2200 // CHECK17-NEXT: store ptr null, ptr [[TMP48]], align 8 2201 // CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 2202 // CHECK17-NEXT: store i64 [[TMP12]], ptr [[TMP49]], align 8 2203 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 9 2204 // CHECK17-NEXT: store i64 [[TMP12]], ptr [[TMP50]], align 8 2205 // CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 9 2206 // CHECK17-NEXT: store ptr null, ptr [[TMP51]], align 8 2207 // CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2208 // CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2209 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2210 // CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2211 // CHECK17-NEXT: store i32 2, ptr [[TMP55]], align 4 2212 // CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2213 // CHECK17-NEXT: store i32 10, ptr [[TMP56]], align 4 2214 // CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2215 // CHECK17-NEXT: store ptr [[TMP52]], ptr [[TMP57]], align 8 2216 // CHECK17-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2217 // CHECK17-NEXT: store ptr [[TMP53]], ptr [[TMP58]], align 8 2218 // CHECK17-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2219 // CHECK17-NEXT: store ptr [[TMP54]], ptr [[TMP59]], align 8 2220 // CHECK17-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2221 // CHECK17-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP60]], align 8 2222 // CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2223 // CHECK17-NEXT: store ptr null, ptr [[TMP61]], align 8 2224 // CHECK17-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2225 // CHECK17-NEXT: store ptr null, ptr [[TMP62]], align 8 2226 // CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2227 // CHECK17-NEXT: store i64 0, ptr [[TMP63]], align 8 2228 // CHECK17-NEXT: [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2229 // CHECK17-NEXT: store i64 0, ptr [[TMP64]], align 8 2230 // CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2231 // CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP65]], align 4 2232 // CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2233 // CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP66]], align 4 2234 // CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2235 // CHECK17-NEXT: store i32 0, ptr [[TMP67]], align 4 2236 // CHECK17-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.region_id, ptr [[KERNEL_ARGS]]) 2237 // CHECK17-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 2238 // CHECK17-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2239 // CHECK17: omp_offload.failed: 2240 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144(ptr [[TMP9]], i64 [[TMP1]], ptr [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], ptr [[VLA]], ptr [[THIS1]], i64 [[TMP12]]) #[[ATTR5]] 2241 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 2242 // CHECK17: omp_offload.cont: 2243 // CHECK17-NEXT: [[TMP70:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 2244 // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP70]]) 2245 // CHECK17-NEXT: ret void 2246 // 2247 // 2248 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144 2249 // CHECK17-SAME: (ptr [[S:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], ptr [[THIS:%.*]], i64 [[N:%.*]]) #[[ATTR2]] { 2250 // CHECK17-NEXT: entry: 2251 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 2252 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2253 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 2254 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 2255 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 2256 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 8 2257 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2258 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 2259 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 2260 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 2261 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 2262 // CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8 2263 // CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8 2264 // CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8 2265 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2266 // CHECK17-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 2267 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 2268 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 2269 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 2270 // CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 2271 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2272 // CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 2273 // CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[S_ADDR]], align 8 2274 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 8, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.omp_outlined, i64 [[TMP0]], ptr [[TMP5]], ptr [[TMP4]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]], ptr [[N_ADDR]], ptr [[TMP6]]) 2275 // CHECK17-NEXT: ret void 2276 // 2277 // 2278 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPg_l144.omp_outlined 2279 // CHECK17-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], ptr nonnull align 8 dereferenceable(8) [[VLA26:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], ptr [[S:%.*]]) #[[ATTR3]] { 2280 // CHECK17-NEXT: entry: 2281 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2282 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2283 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2284 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 8 2285 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2286 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 2287 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 2288 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 8 2289 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 2290 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 2291 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 2292 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2293 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 2294 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2295 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2296 // CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 2297 // CHECK17-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 8 2298 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2299 // CHECK17-NEXT: store i64 [[VLA2]], ptr [[VLA_ADDR3]], align 8 2300 // CHECK17-NEXT: store i64 [[VLA4]], ptr [[VLA_ADDR5]], align 8 2301 // CHECK17-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 8 2302 // CHECK17-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 2303 // CHECK17-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 2304 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 2305 // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2306 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR3]], align 8 2307 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR5]], align 8 2308 // CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 8 2309 // CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[N_ADDR]], align 8 2310 // CHECK17-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave.p0() 2311 // CHECK17-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 8 2312 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 2313 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP7]], align 128 2314 // CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 2315 // CHECK17-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8 2316 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 2317 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 8 2318 // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i64 [[TMP9]], i1 false) 2319 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP1]], i32 0, i32 1 2320 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4 2321 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 0 2322 // CHECK17-NEXT: store i32 [[TMP10]], ptr [[A]], align 4 2323 // CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double 2324 // CHECK17-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP3]] 2325 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[VLA7]], i64 [[TMP11]] 2326 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP5]], align 4 2327 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP12]], 1 2328 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 2329 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i64 [[IDXPROM]] 2330 // CHECK17-NEXT: store double [[CONV]], ptr [[ARRAYIDX8]], align 8 2331 // CHECK17-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to ppc_fp128 2332 // CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 8 2333 // CHECK17-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 1 2334 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[B10]], align 4 2335 // CHECK17-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP14]] to i64 2336 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds ppc_fp128, ptr [[TMP13]], i64 [[IDXPROM11]] 2337 // CHECK17-NEXT: store ppc_fp128 [[CONV9]], ptr [[ARRAYIDX12]], align 16 2338 // CHECK17-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 2339 // CHECK17-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]]) 2340 // CHECK17-NEXT: ret void 2341 // 2342 // 2343 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2344 // CHECK17-SAME: () #[[ATTR6:[0-9]+]] { 2345 // CHECK17-NEXT: entry: 2346 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 2347 // CHECK17-NEXT: ret void 2348 // 2349 // 2350 // CHECK19-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe 2351 // CHECK19-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 2352 // CHECK19-NEXT: entry: 2353 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 2354 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2355 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2356 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 4 2357 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2358 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2359 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2360 // CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 2361 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [8 x ptr], align 4 2362 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [8 x ptr], align 4 2363 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [8 x ptr], align 4 2364 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [8 x i64], align 4 2365 // CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2366 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 2367 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2368 // CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2369 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 2370 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2371 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 2372 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 2373 // CHECK19-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0() 2374 // CHECK19-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 4 2375 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 2376 // CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 2377 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 2378 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 2379 // CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[A_ADDR]], align 4 2380 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2381 // CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 2382 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 4 2383 // CHECK19-NEXT: store i32 [[TMP8]], ptr [[N_CASTED]], align 4 2384 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_CASTED]], align 4 2385 // CHECK19-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 2386 // CHECK19-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 2387 // CHECK19-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 2388 // CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes, i32 64, i1 false) 2389 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2390 // CHECK19-NEXT: store ptr [[TMP5]], ptr [[TMP13]], align 4 2391 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2392 // CHECK19-NEXT: store ptr [[TMP5]], ptr [[TMP14]], align 4 2393 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2394 // CHECK19-NEXT: store ptr null, ptr [[TMP15]], align 4 2395 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2396 // CHECK19-NEXT: store ptr [[TMP6]], ptr [[TMP16]], align 4 2397 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2398 // CHECK19-NEXT: store ptr [[TMP6]], ptr [[TMP17]], align 4 2399 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2400 // CHECK19-NEXT: store ptr null, ptr [[TMP18]], align 4 2401 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2402 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[TMP19]], align 4 2403 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2404 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[TMP20]], align 4 2405 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2406 // CHECK19-NEXT: store ptr null, ptr [[TMP21]], align 4 2407 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2408 // CHECK19-NEXT: store ptr [[TMP7]], ptr [[TMP22]], align 4 2409 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2410 // CHECK19-NEXT: store ptr [[TMP7]], ptr [[TMP23]], align 4 2411 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2412 // CHECK19-NEXT: store ptr null, ptr [[TMP24]], align 4 2413 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2414 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP25]], align 4 2415 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2416 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP26]], align 4 2417 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2418 // CHECK19-NEXT: store ptr null, ptr [[TMP27]], align 4 2419 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 2420 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[TMP28]], align 4 2421 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 2422 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[TMP29]], align 4 2423 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 2424 // CHECK19-NEXT: store ptr null, ptr [[TMP30]], align 4 2425 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 2426 // CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP31]], align 4 2427 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6 2428 // CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP32]], align 4 2429 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 6 2430 // CHECK19-NEXT: store i64 [[TMP12]], ptr [[TMP33]], align 4 2431 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 2432 // CHECK19-NEXT: store ptr null, ptr [[TMP34]], align 4 2433 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 2434 // CHECK19-NEXT: store i32 [[TMP9]], ptr [[TMP35]], align 4 2435 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7 2436 // CHECK19-NEXT: store i32 [[TMP9]], ptr [[TMP36]], align 4 2437 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 2438 // CHECK19-NEXT: store ptr null, ptr [[TMP37]], align 4 2439 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2440 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [8 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2441 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [8 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2442 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2443 // CHECK19-NEXT: store i32 2, ptr [[TMP41]], align 4 2444 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2445 // CHECK19-NEXT: store i32 8, ptr [[TMP42]], align 4 2446 // CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2447 // CHECK19-NEXT: store ptr [[TMP38]], ptr [[TMP43]], align 4 2448 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2449 // CHECK19-NEXT: store ptr [[TMP39]], ptr [[TMP44]], align 4 2450 // CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2451 // CHECK19-NEXT: store ptr [[TMP40]], ptr [[TMP45]], align 4 2452 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2453 // CHECK19-NEXT: store ptr @.offload_maptypes, ptr [[TMP46]], align 4 2454 // CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2455 // CHECK19-NEXT: store ptr null, ptr [[TMP47]], align 4 2456 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2457 // CHECK19-NEXT: store ptr null, ptr [[TMP48]], align 4 2458 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2459 // CHECK19-NEXT: store i64 0, ptr [[TMP49]], align 8 2460 // CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2461 // CHECK19-NEXT: store i64 0, ptr [[TMP50]], align 8 2462 // CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2463 // CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP51]], align 4 2464 // CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2465 // CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP52]], align 4 2466 // CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2467 // CHECK19-NEXT: store i32 0, ptr [[TMP53]], align 4 2468 // CHECK19-NEXT: [[TMP54:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.region_id, ptr [[KERNEL_ARGS]]) 2469 // CHECK19-NEXT: [[TMP55:%.*]] = icmp ne i32 [[TMP54]], 0 2470 // CHECK19-NEXT: br i1 [[TMP55]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2471 // CHECK19: omp_offload.failed: 2472 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152(ptr [[TMP5]], ptr [[TMP6]], i32 [[TMP0]], ptr [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], ptr [[VLA]], i32 [[TMP9]]) #[[ATTR5:[0-9]+]] 2473 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 2474 // CHECK19: omp_offload.cont: 2475 // CHECK19-NEXT: [[TMP56:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2476 // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP56]]) 2477 // CHECK19-NEXT: ret void 2478 // 2479 // 2480 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152 2481 // CHECK19-SAME: (ptr [[A:%.*]], ptr [[S:%.*]], i32 [[VLA:%.*]], ptr [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], ptr nonnull align 4 dereferenceable(8) [[VLA26:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { 2482 // CHECK19-NEXT: entry: 2483 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 2484 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2485 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2486 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 4 2487 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 2488 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 2489 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 4 2490 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2491 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 2492 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2493 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2494 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 2495 // CHECK19-NEXT: store i32 [[VLA2]], ptr [[VLA_ADDR3]], align 4 2496 // CHECK19-NEXT: store i32 [[VLA4]], ptr [[VLA_ADDR5]], align 4 2497 // CHECK19-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 4 2498 // CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2499 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2500 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR3]], align 4 2501 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR5]], align 4 2502 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 4 2503 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2504 // CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 2505 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[A_ADDR]], align 4 2506 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 8, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.omp_outlined, ptr [[TMP4]], ptr [[N_ADDR]], i32 [[TMP0]], ptr [[TMP5]], ptr [[TMP6]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) 2507 // CHECK19-NEXT: ret void 2508 // 2509 // 2510 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z10array_funcPfP2StiPe_l152.omp_outlined 2511 // CHECK19-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr [[S:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], i32 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[A:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], ptr nonnull align 4 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR3:[0-9]+]] { 2512 // CHECK19-NEXT: entry: 2513 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2514 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2515 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2516 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 4 2517 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2518 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 4 2519 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 2520 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 2521 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 2522 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 4 2523 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2524 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2525 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2526 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2527 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2528 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2529 // CHECK19-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4 2530 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2531 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 2532 // CHECK19-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 2533 // CHECK19-NEXT: store i32 [[VLA2]], ptr [[VLA_ADDR3]], align 4 2534 // CHECK19-NEXT: store i32 [[VLA4]], ptr [[VLA_ADDR5]], align 4 2535 // CHECK19-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 4 2536 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 4 2537 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2538 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR3]], align 4 2539 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR5]], align 4 2540 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 4 2541 // CHECK19-NEXT: [[TMP5:%.*]] = call ptr @llvm.stacksave.p0() 2542 // CHECK19-NEXT: store ptr [[TMP5]], ptr [[SAVED_STACK]], align 4 2543 // CHECK19-NEXT: [[TMP6:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 2544 // CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP6]], align 128 2545 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR0]], align 4 2546 // CHECK19-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 2547 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 2548 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 8 2549 // CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i32 [[TMP8]], i1 false) 2550 // CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2551 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP9]], i32 0 2552 // CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2553 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP0]], align 4 2554 // CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 2555 // CHECK19-NEXT: call void @_ZN2St7St_funcEPS_iPe(ptr nonnull align 4 dereferenceable(8) [[ARRAYIDX]], ptr [[TMP10]], i32 [[TMP11]], ptr [[TMP12]]) 2556 // CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2557 // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]]) 2558 // CHECK19-NEXT: ret void 2559 // 2560 // 2561 // CHECK19-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe 2562 // CHECK19-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr [[S:%.*]], i32 [[N:%.*]], ptr [[VLA1:%.*]]) #[[ATTR0]] comdat align 2 { 2563 // CHECK19-NEXT: entry: 2564 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2565 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2566 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2567 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 4 2568 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2569 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2570 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2571 // CHECK19-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 2572 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [10 x ptr], align 4 2573 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [10 x ptr], align 4 2574 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [10 x ptr], align 4 2575 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 2576 // CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2577 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2578 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2579 // CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2580 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 2581 // CHECK19-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2582 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2583 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 2584 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 2585 // CHECK19-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0() 2586 // CHECK19-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 4 2587 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 2588 // CHECK19-NEXT: [[VLA:%.*]] = alloca double, i32 [[TMP4]], align 128 2589 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 2590 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4 2591 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 1 2592 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 2593 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0 2594 // CHECK19-NEXT: store i32 [[TMP5]], ptr [[A]], align 4 2595 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2596 // CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 2597 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 4 2598 // CHECK19-NEXT: store i32 [[TMP8]], ptr [[N_CASTED]], align 4 2599 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_CASTED]], align 4 2600 // CHECK19-NEXT: [[TMP10:%.*]] = mul nuw i32 [[TMP1]], [[TMP2]] 2601 // CHECK19-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 8 2602 // CHECK19-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 2603 // CHECK19-NEXT: [[B2:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 2604 // CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 0 2605 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[B2]], i32 1 2606 // CHECK19-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i64 2607 // CHECK19-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[A3]] to i64 2608 // CHECK19-NEXT: [[TMP16:%.*]] = sub i64 [[TMP14]], [[TMP15]] 2609 // CHECK19-NEXT: [[TMP17:%.*]] = sdiv exact i64 [[TMP16]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) 2610 // CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.1, i32 80, i1 false) 2611 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2612 // CHECK19-NEXT: store ptr [[TMP6]], ptr [[TMP18]], align 4 2613 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2614 // CHECK19-NEXT: store ptr [[TMP6]], ptr [[TMP19]], align 4 2615 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2616 // CHECK19-NEXT: store ptr null, ptr [[TMP20]], align 4 2617 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2618 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[TMP21]], align 4 2619 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2620 // CHECK19-NEXT: store i32 [[TMP0]], ptr [[TMP22]], align 4 2621 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2622 // CHECK19-NEXT: store ptr null, ptr [[TMP23]], align 4 2623 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2624 // CHECK19-NEXT: store ptr [[TMP7]], ptr [[TMP24]], align 4 2625 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2626 // CHECK19-NEXT: store ptr [[TMP7]], ptr [[TMP25]], align 4 2627 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2628 // CHECK19-NEXT: store ptr null, ptr [[TMP26]], align 4 2629 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2630 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP27]], align 4 2631 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2632 // CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP28]], align 4 2633 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2634 // CHECK19-NEXT: store ptr null, ptr [[TMP29]], align 4 2635 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2636 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[TMP30]], align 4 2637 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2638 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[TMP31]], align 4 2639 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2640 // CHECK19-NEXT: store ptr null, ptr [[TMP32]], align 4 2641 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 2642 // CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP33]], align 4 2643 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5 2644 // CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP34]], align 4 2645 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 5 2646 // CHECK19-NEXT: store i64 [[TMP12]], ptr [[TMP35]], align 4 2647 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 2648 // CHECK19-NEXT: store ptr null, ptr [[TMP36]], align 4 2649 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6 2650 // CHECK19-NEXT: store ptr [[THIS1]], ptr [[TMP37]], align 4 2651 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6 2652 // CHECK19-NEXT: store ptr [[A3]], ptr [[TMP38]], align 4 2653 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 6 2654 // CHECK19-NEXT: store i64 [[TMP17]], ptr [[TMP39]], align 4 2655 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6 2656 // CHECK19-NEXT: store ptr null, ptr [[TMP40]], align 4 2657 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7 2658 // CHECK19-NEXT: store ptr [[THIS1]], ptr [[TMP41]], align 4 2659 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7 2660 // CHECK19-NEXT: store ptr [[B2]], ptr [[TMP42]], align 4 2661 // CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7 2662 // CHECK19-NEXT: store ptr null, ptr [[TMP43]], align 4 2663 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8 2664 // CHECK19-NEXT: store ptr [[THIS1]], ptr [[TMP44]], align 4 2665 // CHECK19-NEXT: [[TMP45:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8 2666 // CHECK19-NEXT: store ptr [[A3]], ptr [[TMP45]], align 4 2667 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8 2668 // CHECK19-NEXT: store ptr null, ptr [[TMP46]], align 4 2669 // CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 9 2670 // CHECK19-NEXT: store i32 [[TMP9]], ptr [[TMP47]], align 4 2671 // CHECK19-NEXT: [[TMP48:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 9 2672 // CHECK19-NEXT: store i32 [[TMP9]], ptr [[TMP48]], align 4 2673 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 9 2674 // CHECK19-NEXT: store ptr null, ptr [[TMP49]], align 4 2675 // CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2676 // CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2677 // CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2678 // CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2679 // CHECK19-NEXT: store i32 2, ptr [[TMP53]], align 4 2680 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2681 // CHECK19-NEXT: store i32 10, ptr [[TMP54]], align 4 2682 // CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2683 // CHECK19-NEXT: store ptr [[TMP50]], ptr [[TMP55]], align 4 2684 // CHECK19-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2685 // CHECK19-NEXT: store ptr [[TMP51]], ptr [[TMP56]], align 4 2686 // CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2687 // CHECK19-NEXT: store ptr [[TMP52]], ptr [[TMP57]], align 4 2688 // CHECK19-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2689 // CHECK19-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP58]], align 4 2690 // CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2691 // CHECK19-NEXT: store ptr null, ptr [[TMP59]], align 4 2692 // CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2693 // CHECK19-NEXT: store ptr null, ptr [[TMP60]], align 4 2694 // CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2695 // CHECK19-NEXT: store i64 0, ptr [[TMP61]], align 8 2696 // CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 2697 // CHECK19-NEXT: store i64 0, ptr [[TMP62]], align 8 2698 // CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 2699 // CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP63]], align 4 2700 // CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 2701 // CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP64]], align 4 2702 // CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 2703 // CHECK19-NEXT: store i32 0, ptr [[TMP65]], align 4 2704 // CHECK19-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.region_id, ptr [[KERNEL_ARGS]]) 2705 // CHECK19-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 2706 // CHECK19-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2707 // CHECK19: omp_offload.failed: 2708 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144(ptr [[TMP6]], i32 [[TMP0]], ptr [[TMP7]], i32 [[TMP1]], i32 [[TMP2]], ptr [[VLA]], ptr [[THIS1]], i32 [[TMP9]]) #[[ATTR5]] 2709 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 2710 // CHECK19: omp_offload.cont: 2711 // CHECK19-NEXT: [[TMP68:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2712 // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP68]]) 2713 // CHECK19-NEXT: ret void 2714 // 2715 // 2716 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144 2717 // CHECK19-SAME: (ptr [[S:%.*]], i32 [[VLA:%.*]], ptr [[VLA1:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], ptr nonnull align 4 dereferenceable(8) [[VLA26:%.*]], ptr [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR2]] { 2718 // CHECK19-NEXT: entry: 2719 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2720 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2721 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 4 2722 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 2723 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 2724 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 4 2725 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2726 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2727 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2728 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2729 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 2730 // CHECK19-NEXT: store i32 [[VLA2]], ptr [[VLA_ADDR3]], align 4 2731 // CHECK19-NEXT: store i32 [[VLA4]], ptr [[VLA_ADDR5]], align 4 2732 // CHECK19-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 4 2733 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2734 // CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2735 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2736 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR3]], align 4 2737 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR5]], align 4 2738 // CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 4 2739 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2740 // CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 2741 // CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[S_ADDR]], align 4 2742 // CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 8, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.omp_outlined, i32 [[TMP0]], ptr [[TMP5]], ptr [[TMP4]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]], ptr [[N_ADDR]], ptr [[TMP6]]) 2743 // CHECK19-NEXT: ret void 2744 // 2745 // 2746 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2St7St_funcEPS_iPe_l144.omp_outlined 2747 // CHECK19-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], i32 [[VLA:%.*]], ptr [[VLA1:%.*]], ptr [[THIS:%.*]], i32 [[VLA2:%.*]], i32 [[VLA4:%.*]], ptr nonnull align 4 dereferenceable(8) [[VLA26:%.*]], ptr nonnull align 4 dereferenceable(4) [[N:%.*]], ptr [[S:%.*]]) #[[ATTR3]] { 2748 // CHECK19-NEXT: entry: 2749 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2750 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2751 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2752 // CHECK19-NEXT: [[VLA1_ADDR:%.*]] = alloca ptr, align 4 2753 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2754 // CHECK19-NEXT: [[VLA_ADDR3:%.*]] = alloca i32, align 4 2755 // CHECK19-NEXT: [[VLA_ADDR5:%.*]] = alloca i32, align 4 2756 // CHECK19-NEXT: [[VLA2_ADDR:%.*]] = alloca ptr, align 4 2757 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 4 2758 // CHECK19-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 4 2759 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2760 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2761 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2762 // CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2763 // CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2764 // CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2765 // CHECK19-NEXT: store ptr [[VLA1]], ptr [[VLA1_ADDR]], align 4 2766 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2767 // CHECK19-NEXT: store i32 [[VLA2]], ptr [[VLA_ADDR3]], align 4 2768 // CHECK19-NEXT: store i32 [[VLA4]], ptr [[VLA_ADDR5]], align 4 2769 // CHECK19-NEXT: store ptr [[VLA26]], ptr [[VLA2_ADDR]], align 4 2770 // CHECK19-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4 2771 // CHECK19-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 4 2772 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2773 // CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2774 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR3]], align 4 2775 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR5]], align 4 2776 // CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VLA2_ADDR]], align 4 2777 // CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[N_ADDR]], align 4 2778 // CHECK19-NEXT: [[TMP6:%.*]] = call ptr @llvm.stacksave.p0() 2779 // CHECK19-NEXT: store ptr [[TMP6]], ptr [[SAVED_STACK]], align 4 2780 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 2781 // CHECK19-NEXT: [[VLA7:%.*]] = alloca double, i32 [[TMP7]], align 128 2782 // CHECK19-NEXT: store i32 [[TMP2]], ptr [[__VLA_EXPR0]], align 4 2783 // CHECK19-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 2784 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP2]], [[TMP3]] 2785 // CHECK19-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 8 2786 // CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VLA7]], ptr align 128 [[TMP4]], i32 [[TMP9]], i1 false) 2787 // CHECK19-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP1]], i32 0, i32 1 2788 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[B]], align 4 2789 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 0 2790 // CHECK19-NEXT: store i32 [[TMP10]], ptr [[A]], align 4 2791 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double 2792 // CHECK19-NEXT: [[TMP11:%.*]] = mul nsw i32 1, [[TMP3]] 2793 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[VLA7]], i32 [[TMP11]] 2794 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP5]], align 4 2795 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP12]], 1 2796 // CHECK19-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX]], i32 [[SUB]] 2797 // CHECK19-NEXT: store double [[CONV]], ptr [[ARRAYIDX8]], align 8 2798 // CHECK19-NEXT: [[CONV9:%.*]] = fpext double [[CONV]] to x86_fp80 2799 // CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[VLA1_ADDR]], align 4 2800 // CHECK19-NEXT: [[B10:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[TMP1]], i32 0, i32 1 2801 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[B10]], align 4 2802 // CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, ptr [[TMP13]], i32 [[TMP14]] 2803 // CHECK19-NEXT: store x86_fp80 [[CONV9]], ptr [[ARRAYIDX11]], align 4 2804 // CHECK19-NEXT: [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2805 // CHECK19-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP15]]) 2806 // CHECK19-NEXT: ret void 2807 // 2808 // 2809 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2810 // CHECK19-SAME: () #[[ATTR6:[0-9]+]] { 2811 // CHECK19-NEXT: entry: 2812 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 2813 // CHECK19-NEXT: ret void 2814 // 2815