1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 8 9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 23 24 // expected-no-diagnostics 25 #ifndef HEADER 26 #define HEADER 27 28 struct St { 29 int a, b; 30 St() : a(0), b(0) {} 31 St(const St &st) : a(st.a + st.b), b(0) {} 32 ~St() {} 33 }; 34 35 volatile int g = 1212; 36 volatile int &g1 = g; 37 38 template <class T> 39 struct S { 40 T f; 41 S(T a) : f(a + g) {} 42 S() : f(g) {} 43 S(const S &s, St t = St()) : f(s.f + t.a) {} 44 operator T() { return T(); } 45 ~S() {} 46 }; 47 48 49 template <typename T> 50 T tmain() { 51 S<T> test; 52 T t_var = T(); 53 T vec[] = {1, 2}; 54 S<T> s_arr[] = {1, 2}; 55 S<T> &var = test; 56 #pragma omp target 57 #pragma omp teams distribute simd private(t_var, vec, s_arr, var) 58 for (int i = 0; i < 2; ++i) { 59 vec[i] = t_var; 60 s_arr[i] = var; 61 } 62 return T(); 63 } 64 65 S<float> test; 66 int t_var = 333; 67 int vec[] = {1, 2}; 68 S<float> s_arr[] = {1, 2}; 69 S<float> var(3); 70 71 int main() { 72 static int sivar; 73 #ifdef LAMBDA 74 [&]() { 75 #pragma omp target 76 #pragma omp teams distribute simd private(g, g1, sivar) 77 for (int i = 0; i < 2; ++i) { 78 79 // Skip global, bound tid and loop vars 80 81 g = 1; 82 g1 = 1; 83 sivar = 2; 84 [&]() { 85 g = 2; 86 g1 = 2; 87 sivar = 4; 88 89 }(); 90 } 91 }(); 92 return 0; 93 #else 94 #pragma omp target 95 #pragma omp teams distribute simd private(t_var, vec, s_arr, var, sivar) 96 for (int i = 0; i < 2; ++i) { 97 vec[i] = t_var; 98 s_arr[i] = var; 99 sivar += i; 100 } 101 return tmain<int>(); 102 #endif 103 } 104 105 106 107 // Skip global, bound tid and loop vars 108 109 // private(s_arr) 110 111 // private(var) 112 113 114 115 116 117 // Skip global, bound tid and loop vars 118 119 // private(s_arr) 120 121 122 // private(var) 123 124 125 #endif 126 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 127 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 128 // CHECK1-NEXT: entry: 129 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 130 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 131 // CHECK1-NEXT: ret void 132 // 133 // 134 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 135 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 136 // CHECK1-NEXT: entry: 137 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 138 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 139 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 140 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 141 // CHECK1-NEXT: ret void 142 // 143 // 144 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 145 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 146 // CHECK1-NEXT: entry: 147 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 148 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 149 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 150 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 151 // CHECK1-NEXT: ret void 152 // 153 // 154 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 155 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 156 // CHECK1-NEXT: entry: 157 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 158 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 160 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 161 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 162 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 163 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 164 // CHECK1-NEXT: ret void 165 // 166 // 167 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 168 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 169 // CHECK1-NEXT: entry: 170 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 171 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 172 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 173 // CHECK1-NEXT: ret void 174 // 175 // 176 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 177 // CHECK1-SAME: () #[[ATTR0]] { 178 // CHECK1-NEXT: entry: 179 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 180 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 181 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 182 // CHECK1-NEXT: ret void 183 // 184 // 185 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 186 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 187 // CHECK1-NEXT: entry: 188 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 189 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 190 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 191 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 192 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 193 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 194 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 195 // CHECK1-NEXT: ret void 196 // 197 // 198 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 199 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 200 // CHECK1-NEXT: entry: 201 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 202 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 203 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 204 // CHECK1: arraydestroy.body: 205 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 206 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 207 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 208 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 209 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 210 // CHECK1: arraydestroy.done1: 211 // CHECK1-NEXT: ret void 212 // 213 // 214 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 215 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 216 // CHECK1-NEXT: entry: 217 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 218 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 219 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 220 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 221 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 222 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 223 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 224 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 225 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 226 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 227 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 228 // CHECK1-NEXT: ret void 229 // 230 // 231 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 232 // CHECK1-SAME: () #[[ATTR0]] { 233 // CHECK1-NEXT: entry: 234 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 235 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 236 // CHECK1-NEXT: ret void 237 // 238 // 239 // CHECK1-LABEL: define {{[^@]+}}@main 240 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 241 // CHECK1-NEXT: entry: 242 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 243 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 244 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 245 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 246 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 247 // CHECK1-NEXT: store i32 2, ptr [[TMP0]], align 4 248 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 249 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 250 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 251 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 252 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 253 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 254 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 255 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 256 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 257 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 258 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 259 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 260 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 261 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 262 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 263 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 264 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 265 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 266 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 267 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 268 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 269 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4 270 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 271 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 272 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS]]) 273 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 274 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 275 // CHECK1: omp_offload.failed: 276 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] 277 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 278 // CHECK1: omp_offload.cont: 279 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 280 // CHECK1-NEXT: ret i32 [[CALL]] 281 // 282 // 283 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 284 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { 285 // CHECK1-NEXT: entry: 286 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined) 287 // CHECK1-NEXT: ret void 288 // 289 // 290 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined 291 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 292 // CHECK1-NEXT: entry: 293 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 294 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 295 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 296 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 297 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 298 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 299 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 300 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 301 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 302 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 303 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 304 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 305 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 306 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 307 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 308 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 309 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 310 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 311 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 312 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 313 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 314 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 315 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 316 // CHECK1: arrayctor.loop: 317 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 318 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 319 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 320 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 321 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 322 // CHECK1: arrayctor.cont: 323 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 324 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 325 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 326 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 327 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 328 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 329 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 330 // CHECK1: cond.true: 331 // CHECK1-NEXT: br label [[COND_END:%.*]] 332 // CHECK1: cond.false: 333 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 334 // CHECK1-NEXT: br label [[COND_END]] 335 // CHECK1: cond.end: 336 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 337 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 338 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 339 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 340 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 341 // CHECK1: omp.inner.for.cond: 342 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]] 343 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]] 344 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 345 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 346 // CHECK1: omp.inner.for.cond.cleanup: 347 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 348 // CHECK1: omp.inner.for.body: 349 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 350 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 351 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 352 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 353 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP5]] 354 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 355 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 356 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 357 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] 358 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 359 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 360 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] 361 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]] 362 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] 363 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP5]] 364 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 365 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP5]] 366 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 367 // CHECK1: omp.body.continue: 368 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 369 // CHECK1: omp.inner.for.inc: 370 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 371 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 372 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]] 373 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 374 // CHECK1: omp.inner.for.end: 375 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 376 // CHECK1: omp.loop.exit: 377 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 378 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 379 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) 380 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 381 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 382 // CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 383 // CHECK1: .omp.final.then: 384 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 385 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 386 // CHECK1: .omp.final.done: 387 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 388 // CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 389 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 390 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 391 // CHECK1: arraydestroy.body: 392 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 393 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 394 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 395 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 396 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 397 // CHECK1: arraydestroy.done7: 398 // CHECK1-NEXT: ret void 399 // 400 // 401 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 402 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 403 // CHECK1-NEXT: entry: 404 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 405 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 406 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 407 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 408 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 409 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 410 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 411 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 412 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 413 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 414 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 415 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 416 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 417 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 418 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 419 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 420 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 421 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 422 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 423 // CHECK1-NEXT: store i32 2, ptr [[TMP0]], align 4 424 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 425 // CHECK1-NEXT: store i32 0, ptr [[TMP1]], align 4 426 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 427 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8 428 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 429 // CHECK1-NEXT: store ptr null, ptr [[TMP3]], align 8 430 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 431 // CHECK1-NEXT: store ptr null, ptr [[TMP4]], align 8 432 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 433 // CHECK1-NEXT: store ptr null, ptr [[TMP5]], align 8 434 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 435 // CHECK1-NEXT: store ptr null, ptr [[TMP6]], align 8 436 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 437 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 438 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 439 // CHECK1-NEXT: store i64 2, ptr [[TMP8]], align 8 440 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 441 // CHECK1-NEXT: store i64 0, ptr [[TMP9]], align 8 442 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 443 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 444 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 445 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4 446 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 447 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 448 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 449 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 450 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 451 // CHECK1: omp_offload.failed: 452 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 453 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 454 // CHECK1: omp_offload.cont: 455 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 456 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 457 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 458 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 459 // CHECK1: arraydestroy.body: 460 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 461 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 462 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 463 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 464 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 465 // CHECK1: arraydestroy.done2: 466 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 467 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 468 // CHECK1-NEXT: ret i32 [[TMP16]] 469 // 470 // 471 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 472 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 473 // CHECK1-NEXT: entry: 474 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 475 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 476 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 477 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 478 // CHECK1-NEXT: ret void 479 // 480 // 481 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 482 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 483 // CHECK1-NEXT: entry: 484 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 485 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 486 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 487 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 488 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 489 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 490 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 491 // CHECK1-NEXT: ret void 492 // 493 // 494 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 495 // CHECK1-SAME: () #[[ATTR4]] { 496 // CHECK1-NEXT: entry: 497 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) 498 // CHECK1-NEXT: ret void 499 // 500 // 501 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 502 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 503 // CHECK1-NEXT: entry: 504 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 505 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 506 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 507 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 508 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 509 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 510 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 511 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 512 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 513 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 514 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 515 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 516 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 517 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 518 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 519 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 520 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 521 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 522 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 523 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 524 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 525 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 526 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 527 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 528 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 529 // CHECK1: arrayctor.loop: 530 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 531 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 532 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 533 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 534 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 535 // CHECK1: arrayctor.cont: 536 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 537 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 538 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 539 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 540 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 541 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 542 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 543 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 544 // CHECK1: cond.true: 545 // CHECK1-NEXT: br label [[COND_END:%.*]] 546 // CHECK1: cond.false: 547 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 548 // CHECK1-NEXT: br label [[COND_END]] 549 // CHECK1: cond.end: 550 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 551 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 552 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 553 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 554 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 555 // CHECK1: omp.inner.for.cond: 556 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 557 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 558 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 559 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 560 // CHECK1: omp.inner.for.cond.cleanup: 561 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 562 // CHECK1: omp.inner.for.body: 563 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 564 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 565 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 566 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 567 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP11]] 568 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 569 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 570 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 571 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] 572 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP11]] 573 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 574 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 575 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] 576 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] 577 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 578 // CHECK1: omp.body.continue: 579 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 580 // CHECK1: omp.inner.for.inc: 581 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 582 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 583 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 584 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 585 // CHECK1: omp.inner.for.end: 586 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 587 // CHECK1: omp.loop.exit: 588 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 589 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 590 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 591 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 592 // CHECK1-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 593 // CHECK1-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 594 // CHECK1: .omp.final.then: 595 // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 596 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 597 // CHECK1: .omp.final.done: 598 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 599 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 600 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 601 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 602 // CHECK1: arraydestroy.body: 603 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 604 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 605 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 606 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 607 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 608 // CHECK1: arraydestroy.done8: 609 // CHECK1-NEXT: ret void 610 // 611 // 612 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 613 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 614 // CHECK1-NEXT: entry: 615 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 616 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 617 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 618 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 619 // CHECK1-NEXT: ret void 620 // 621 // 622 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 623 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 624 // CHECK1-NEXT: entry: 625 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 626 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 627 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 628 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 629 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 630 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 631 // CHECK1-NEXT: ret void 632 // 633 // 634 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 635 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 636 // CHECK1-NEXT: entry: 637 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 638 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 639 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 640 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 641 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 642 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 643 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 644 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 645 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 646 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 647 // CHECK1-NEXT: ret void 648 // 649 // 650 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 651 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 652 // CHECK1-NEXT: entry: 653 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 654 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 655 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 656 // CHECK1-NEXT: ret void 657 // 658 // 659 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp 660 // CHECK1-SAME: () #[[ATTR0]] { 661 // CHECK1-NEXT: entry: 662 // CHECK1-NEXT: call void @__cxx_global_var_init() 663 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 664 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 665 // CHECK1-NEXT: ret void 666 // 667 // 668 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 669 // CHECK1-SAME: () #[[ATTR0]] { 670 // CHECK1-NEXT: entry: 671 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 672 // CHECK1-NEXT: ret void 673 // 674 // 675 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 676 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 677 // CHECK3-NEXT: entry: 678 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 679 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 680 // CHECK3-NEXT: ret void 681 // 682 // 683 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 684 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 685 // CHECK3-NEXT: entry: 686 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 687 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 688 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 689 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 690 // CHECK3-NEXT: ret void 691 // 692 // 693 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 694 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 695 // CHECK3-NEXT: entry: 696 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 697 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 698 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 699 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 700 // CHECK3-NEXT: ret void 701 // 702 // 703 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 704 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 705 // CHECK3-NEXT: entry: 706 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 707 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 708 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 709 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 710 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 711 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 712 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 713 // CHECK3-NEXT: ret void 714 // 715 // 716 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 717 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 718 // CHECK3-NEXT: entry: 719 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 720 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 721 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 722 // CHECK3-NEXT: ret void 723 // 724 // 725 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 726 // CHECK3-SAME: () #[[ATTR0]] { 727 // CHECK3-NEXT: entry: 728 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 729 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 730 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 731 // CHECK3-NEXT: ret void 732 // 733 // 734 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 735 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 736 // CHECK3-NEXT: entry: 737 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 738 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 739 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 740 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 741 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 742 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 743 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 744 // CHECK3-NEXT: ret void 745 // 746 // 747 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 748 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 749 // CHECK3-NEXT: entry: 750 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 751 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 752 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 753 // CHECK3: arraydestroy.body: 754 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 755 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 756 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 757 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 758 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 759 // CHECK3: arraydestroy.done1: 760 // CHECK3-NEXT: ret void 761 // 762 // 763 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 764 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 765 // CHECK3-NEXT: entry: 766 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 767 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 768 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 769 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 770 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 771 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 772 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 773 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 774 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 775 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 776 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 777 // CHECK3-NEXT: ret void 778 // 779 // 780 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 781 // CHECK3-SAME: () #[[ATTR0]] { 782 // CHECK3-NEXT: entry: 783 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 784 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 785 // CHECK3-NEXT: ret void 786 // 787 // 788 // CHECK3-LABEL: define {{[^@]+}}@main 789 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 790 // CHECK3-NEXT: entry: 791 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 792 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 793 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 794 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 795 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 796 // CHECK3-NEXT: store i32 2, ptr [[TMP0]], align 4 797 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 798 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 799 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 800 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 801 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 802 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 803 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 804 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 805 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 806 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 807 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 808 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 809 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 810 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 811 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 812 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 813 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 814 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 815 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 816 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 817 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 818 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4 819 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 820 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 821 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.region_id, ptr [[KERNEL_ARGS]]) 822 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 823 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 824 // CHECK3: omp_offload.failed: 825 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94() #[[ATTR2]] 826 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 827 // CHECK3: omp_offload.cont: 828 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 829 // CHECK3-NEXT: ret i32 [[CALL]] 830 // 831 // 832 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94 833 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { 834 // CHECK3-NEXT: entry: 835 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined) 836 // CHECK3-NEXT: ret void 837 // 838 // 839 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l94.omp_outlined 840 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 841 // CHECK3-NEXT: entry: 842 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 843 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 844 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 845 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 846 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 847 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 848 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 849 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 850 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 851 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 852 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 853 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 854 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 855 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 856 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 857 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 858 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 859 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 860 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 861 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 862 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 863 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 864 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 865 // CHECK3: arrayctor.loop: 866 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 867 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 868 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 869 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 870 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 871 // CHECK3: arrayctor.cont: 872 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 873 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 874 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 875 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 876 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 877 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 878 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 879 // CHECK3: cond.true: 880 // CHECK3-NEXT: br label [[COND_END:%.*]] 881 // CHECK3: cond.false: 882 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 883 // CHECK3-NEXT: br label [[COND_END]] 884 // CHECK3: cond.end: 885 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 886 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 887 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 888 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 889 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 890 // CHECK3: omp.inner.for.cond: 891 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 892 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 893 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 894 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 895 // CHECK3: omp.inner.for.cond.cleanup: 896 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 897 // CHECK3: omp.inner.for.body: 898 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 899 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 900 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 901 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 902 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] 903 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 904 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 905 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] 906 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 907 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] 908 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]] 909 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 910 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP6]] 911 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] 912 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP6]] 913 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 914 // CHECK3: omp.body.continue: 915 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 916 // CHECK3: omp.inner.for.inc: 917 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 918 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 919 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 920 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 921 // CHECK3: omp.inner.for.end: 922 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 923 // CHECK3: omp.loop.exit: 924 // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 925 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 926 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) 927 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 928 // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 929 // CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 930 // CHECK3: .omp.final.then: 931 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 932 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 933 // CHECK3: .omp.final.done: 934 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 935 // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 936 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 937 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 938 // CHECK3: arraydestroy.body: 939 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 940 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 941 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 942 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 943 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 944 // CHECK3: arraydestroy.done6: 945 // CHECK3-NEXT: ret void 946 // 947 // 948 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 949 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat { 950 // CHECK3-NEXT: entry: 951 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 952 // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 953 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 954 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 955 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 956 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 957 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 958 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 959 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 960 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 961 // CHECK3-NEXT: store i32 0, ptr [[T_VAR]], align 4 962 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 963 // CHECK3-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 964 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 965 // CHECK3-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1 966 // CHECK3-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 967 // CHECK3-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 968 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 969 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 970 // CHECK3-NEXT: store i32 2, ptr [[TMP0]], align 4 971 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 972 // CHECK3-NEXT: store i32 0, ptr [[TMP1]], align 4 973 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 974 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4 975 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 976 // CHECK3-NEXT: store ptr null, ptr [[TMP3]], align 4 977 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 978 // CHECK3-NEXT: store ptr null, ptr [[TMP4]], align 4 979 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 980 // CHECK3-NEXT: store ptr null, ptr [[TMP5]], align 4 981 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 982 // CHECK3-NEXT: store ptr null, ptr [[TMP6]], align 4 983 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 984 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 985 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 986 // CHECK3-NEXT: store i64 2, ptr [[TMP8]], align 8 987 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9 988 // CHECK3-NEXT: store i64 0, ptr [[TMP9]], align 8 989 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10 990 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4 991 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11 992 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4 993 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 994 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 995 // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) 996 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 997 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 998 // CHECK3: omp_offload.failed: 999 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]] 1000 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1001 // CHECK3: omp_offload.cont: 1002 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 1003 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1004 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1005 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1006 // CHECK3: arraydestroy.body: 1007 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1008 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1009 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1010 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1011 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1012 // CHECK3: arraydestroy.done2: 1013 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1014 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 1015 // CHECK3-NEXT: ret i32 [[TMP16]] 1016 // 1017 // 1018 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1019 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1020 // CHECK3-NEXT: entry: 1021 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1022 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1023 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1024 // CHECK3-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1025 // CHECK3-NEXT: ret void 1026 // 1027 // 1028 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1029 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1030 // CHECK3-NEXT: entry: 1031 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1032 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1033 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1034 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1035 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1036 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1037 // CHECK3-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1038 // CHECK3-NEXT: ret void 1039 // 1040 // 1041 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 1042 // CHECK3-SAME: () #[[ATTR4]] { 1043 // CHECK3-NEXT: entry: 1044 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) 1045 // CHECK3-NEXT: ret void 1046 // 1047 // 1048 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined 1049 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] { 1050 // CHECK3-NEXT: entry: 1051 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 1052 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 1053 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1054 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 1055 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1056 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1057 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1058 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1059 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1060 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1061 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1062 // CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1063 // CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1064 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 1065 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 1066 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 1067 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 1068 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1069 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1070 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1071 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1072 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1073 // CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1074 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1075 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1076 // CHECK3: arrayctor.loop: 1077 // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1078 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1079 // CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1080 // CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1081 // CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1082 // CHECK3: arrayctor.cont: 1083 // CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1084 // CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 1085 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1086 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1087 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1088 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1089 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 1090 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1091 // CHECK3: cond.true: 1092 // CHECK3-NEXT: br label [[COND_END:%.*]] 1093 // CHECK3: cond.false: 1094 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1095 // CHECK3-NEXT: br label [[COND_END]] 1096 // CHECK3: cond.end: 1097 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1098 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1099 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1100 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1101 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1102 // CHECK3: omp.inner.for.cond: 1103 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 1104 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 1105 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1106 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1107 // CHECK3: omp.inner.for.cond.cleanup: 1108 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1109 // CHECK3: omp.inner.for.body: 1110 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 1111 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1112 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1113 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 1114 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP12]] 1115 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 1116 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] 1117 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] 1118 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP12]] 1119 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 1120 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] 1121 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] 1122 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1123 // CHECK3: omp.body.continue: 1124 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1125 // CHECK3: omp.inner.for.inc: 1126 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 1127 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1 1128 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 1129 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 1130 // CHECK3: omp.inner.for.end: 1131 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1132 // CHECK3: omp.loop.exit: 1133 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 1134 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 1135 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) 1136 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 1137 // CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 1138 // CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1139 // CHECK3: .omp.final.then: 1140 // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 1141 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 1142 // CHECK3: .omp.final.done: 1143 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1144 // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1145 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 1146 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1147 // CHECK3: arraydestroy.body: 1148 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1149 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1150 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1151 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] 1152 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] 1153 // CHECK3: arraydestroy.done7: 1154 // CHECK3-NEXT: ret void 1155 // 1156 // 1157 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1158 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1159 // CHECK3-NEXT: entry: 1160 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1161 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1162 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1163 // CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1164 // CHECK3-NEXT: ret void 1165 // 1166 // 1167 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1168 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1169 // CHECK3-NEXT: entry: 1170 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1171 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1172 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1173 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1174 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1175 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1176 // CHECK3-NEXT: ret void 1177 // 1178 // 1179 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1180 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1181 // CHECK3-NEXT: entry: 1182 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1183 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1184 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1185 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1186 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1187 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1188 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1189 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1190 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1191 // CHECK3-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1192 // CHECK3-NEXT: ret void 1193 // 1194 // 1195 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1196 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1197 // CHECK3-NEXT: entry: 1198 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1199 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1200 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1201 // CHECK3-NEXT: ret void 1202 // 1203 // 1204 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp 1205 // CHECK3-SAME: () #[[ATTR0]] { 1206 // CHECK3-NEXT: entry: 1207 // CHECK3-NEXT: call void @__cxx_global_var_init() 1208 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1209 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1210 // CHECK3-NEXT: ret void 1211 // 1212 // 1213 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1214 // CHECK3-SAME: () #[[ATTR0]] { 1215 // CHECK3-NEXT: entry: 1216 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1217 // CHECK3-NEXT: ret void 1218 // 1219 // 1220 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 1221 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 1222 // CHECK5-NEXT: entry: 1223 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1224 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1225 // CHECK5-NEXT: ret void 1226 // 1227 // 1228 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1229 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1230 // CHECK5-NEXT: entry: 1231 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1232 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1233 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1234 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1235 // CHECK5-NEXT: ret void 1236 // 1237 // 1238 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1239 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1240 // CHECK5-NEXT: entry: 1241 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1242 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1243 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1244 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1245 // CHECK5-NEXT: ret void 1246 // 1247 // 1248 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1249 // CHECK5-SAME: () #[[ATTR0]] { 1250 // CHECK5-NEXT: entry: 1251 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1252 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 1253 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1254 // CHECK5-NEXT: ret void 1255 // 1256 // 1257 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1258 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1259 // CHECK5-NEXT: entry: 1260 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1261 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1262 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1263 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1264 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1265 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1266 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1267 // CHECK5-NEXT: ret void 1268 // 1269 // 1270 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1271 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1272 // CHECK5-NEXT: entry: 1273 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 1274 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 1275 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1276 // CHECK5: arraydestroy.body: 1277 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1278 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1279 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1280 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1281 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1282 // CHECK5: arraydestroy.done1: 1283 // CHECK5-NEXT: ret void 1284 // 1285 // 1286 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1287 // CHECK5-SAME: () #[[ATTR0]] { 1288 // CHECK5-NEXT: entry: 1289 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1290 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1291 // CHECK5-NEXT: ret void 1292 // 1293 // 1294 // CHECK5-LABEL: define {{[^@]+}}@main 1295 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1296 // CHECK5-NEXT: entry: 1297 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1298 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1299 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1300 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1301 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1302 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1303 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1304 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1305 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1306 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1307 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1308 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1309 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1310 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1311 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1312 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1313 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1314 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 1315 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1316 // CHECK5: arrayctor.loop: 1317 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1318 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1319 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 1320 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1321 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1322 // CHECK5: arrayctor.cont: 1323 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1324 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1325 // CHECK5: omp.inner.for.cond: 1326 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 1327 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 1328 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1329 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1330 // CHECK5: omp.inner.for.cond.cleanup: 1331 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1332 // CHECK5: omp.inner.for.body: 1333 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1334 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1335 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1336 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1337 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] 1338 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1339 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 1340 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 1341 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] 1342 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1343 // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 1344 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] 1345 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] 1346 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 1347 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] 1348 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 1349 // CHECK5-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] 1350 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1351 // CHECK5: omp.body.continue: 1352 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1353 // CHECK5: omp.inner.for.inc: 1354 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1355 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 1356 // CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 1357 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 1358 // CHECK5: omp.inner.for.end: 1359 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1360 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1361 // CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1362 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i64 2 1363 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1364 // CHECK5: arraydestroy.body: 1365 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1366 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1367 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1368 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1369 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1370 // CHECK5: arraydestroy.done6: 1371 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() 1372 // CHECK5-NEXT: ret i32 [[CALL]] 1373 // 1374 // 1375 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1376 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat { 1377 // CHECK5-NEXT: entry: 1378 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1379 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1380 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1381 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1382 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1383 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 1384 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 1385 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 1386 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1387 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1388 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1389 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 1390 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 1391 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1392 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 1393 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 1394 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 1395 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1396 // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4 1397 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 1398 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 1399 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1) 1400 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 1401 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) 1402 // CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 1403 // CHECK5-NEXT: store ptr undef, ptr [[_TMP1]], align 8 1404 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1405 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1406 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1407 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1408 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1409 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 1410 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1411 // CHECK5: arrayctor.loop: 1412 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1413 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1414 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 1415 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1416 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1417 // CHECK5: arrayctor.cont: 1418 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 1419 // CHECK5-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 1420 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1421 // CHECK5: omp.inner.for.cond: 1422 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 1423 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]] 1424 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1425 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1426 // CHECK5: omp.inner.for.cond.cleanup: 1427 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1428 // CHECK5: omp.inner.for.body: 1429 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1430 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1431 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1432 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1433 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] 1434 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1435 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 1436 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] 1437 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] 1438 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]] 1439 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] 1440 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 1441 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] 1442 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] 1443 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1444 // CHECK5: omp.body.continue: 1445 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1446 // CHECK5: omp.inner.for.inc: 1447 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1448 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1 1449 // CHECK5-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]] 1450 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 1451 // CHECK5: omp.inner.for.end: 1452 // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 1453 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1454 // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1455 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 1456 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1457 // CHECK5: arraydestroy.body: 1458 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1459 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1460 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1461 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] 1462 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] 1463 // CHECK5: arraydestroy.done11: 1464 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 1465 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1466 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 1467 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] 1468 // CHECK5: arraydestroy.body13: 1469 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] 1470 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 1471 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] 1472 // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] 1473 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] 1474 // CHECK5: arraydestroy.done17: 1475 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1476 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 1477 // CHECK5-NEXT: ret i32 [[TMP11]] 1478 // 1479 // 1480 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1481 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1482 // CHECK5-NEXT: entry: 1483 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1484 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1485 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1486 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1487 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1488 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1489 // CHECK5-NEXT: store float [[CONV]], ptr [[F]], align 4 1490 // CHECK5-NEXT: ret void 1491 // 1492 // 1493 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1494 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1495 // CHECK5-NEXT: entry: 1496 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1497 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1498 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1499 // CHECK5-NEXT: ret void 1500 // 1501 // 1502 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1503 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1504 // CHECK5-NEXT: entry: 1505 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1506 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1507 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1508 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1509 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1510 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1511 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1512 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1513 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1514 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1515 // CHECK5-NEXT: store float [[ADD]], ptr [[F]], align 4 1516 // CHECK5-NEXT: ret void 1517 // 1518 // 1519 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1520 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1521 // CHECK5-NEXT: entry: 1522 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1523 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1524 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1525 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1526 // CHECK5-NEXT: ret void 1527 // 1528 // 1529 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1530 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1531 // CHECK5-NEXT: entry: 1532 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1533 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1534 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1535 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1536 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1537 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1538 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]]) 1539 // CHECK5-NEXT: ret void 1540 // 1541 // 1542 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1543 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1544 // CHECK5-NEXT: entry: 1545 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1546 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1547 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1548 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1549 // CHECK5-NEXT: ret void 1550 // 1551 // 1552 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1553 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1554 // CHECK5-NEXT: entry: 1555 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1556 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1557 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1558 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1559 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1560 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1561 // CHECK5-NEXT: ret void 1562 // 1563 // 1564 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1565 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1566 // CHECK5-NEXT: entry: 1567 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1568 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1569 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1570 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1571 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1572 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1573 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1574 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1575 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1576 // CHECK5-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1577 // CHECK5-NEXT: ret void 1578 // 1579 // 1580 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1581 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1582 // CHECK5-NEXT: entry: 1583 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1584 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1585 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1586 // CHECK5-NEXT: ret void 1587 // 1588 // 1589 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp 1590 // CHECK5-SAME: () #[[ATTR0]] { 1591 // CHECK5-NEXT: entry: 1592 // CHECK5-NEXT: call void @__cxx_global_var_init() 1593 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 1594 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 1595 // CHECK5-NEXT: ret void 1596 // 1597 // 1598 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 1599 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 1600 // CHECK7-NEXT: entry: 1601 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1602 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1603 // CHECK7-NEXT: ret void 1604 // 1605 // 1606 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1607 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1608 // CHECK7-NEXT: entry: 1609 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1610 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1611 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1612 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1613 // CHECK7-NEXT: ret void 1614 // 1615 // 1616 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1617 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1618 // CHECK7-NEXT: entry: 1619 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1620 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1621 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1622 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1623 // CHECK7-NEXT: ret void 1624 // 1625 // 1626 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1627 // CHECK7-SAME: () #[[ATTR0]] { 1628 // CHECK7-NEXT: entry: 1629 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 1630 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00) 1631 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 1632 // CHECK7-NEXT: ret void 1633 // 1634 // 1635 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1636 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1637 // CHECK7-NEXT: entry: 1638 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1639 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1640 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1641 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1642 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1643 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1644 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 1645 // CHECK7-NEXT: ret void 1646 // 1647 // 1648 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1649 // CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 1650 // CHECK7-NEXT: entry: 1651 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 1652 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 1653 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1654 // CHECK7: arraydestroy.body: 1655 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1656 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1657 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1658 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 1659 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1660 // CHECK7: arraydestroy.done1: 1661 // CHECK7-NEXT: ret void 1662 // 1663 // 1664 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1665 // CHECK7-SAME: () #[[ATTR0]] { 1666 // CHECK7-NEXT: entry: 1667 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 1668 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 1669 // CHECK7-NEXT: ret void 1670 // 1671 // 1672 // CHECK7-LABEL: define {{[^@]+}}@main 1673 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 1674 // CHECK7-NEXT: entry: 1675 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1676 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1677 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1678 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1679 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1680 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1681 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1682 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1683 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 1684 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1685 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1686 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 1687 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1688 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1689 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1690 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1691 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1692 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 1693 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1694 // CHECK7: arrayctor.loop: 1695 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1696 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1697 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 1698 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1699 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1700 // CHECK7: arrayctor.cont: 1701 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 1702 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1703 // CHECK7: omp.inner.for.cond: 1704 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 1705 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 1706 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1707 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1708 // CHECK7: omp.inner.for.cond.cleanup: 1709 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1710 // CHECK7: omp.inner.for.body: 1711 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 1712 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1713 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1714 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 1715 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]] 1716 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 1717 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]] 1718 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] 1719 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 1720 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]] 1721 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] 1722 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 1723 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] 1724 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] 1725 // CHECK7-NEXT: store i32 [[ADD2]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] 1726 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1727 // CHECK7: omp.body.continue: 1728 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1729 // CHECK7: omp.inner.for.inc: 1730 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 1731 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 1732 // CHECK7-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 1733 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 1734 // CHECK7: omp.inner.for.end: 1735 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 1736 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1737 // CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 1738 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2 1739 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1740 // CHECK7: arraydestroy.body: 1741 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1742 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1743 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1744 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 1745 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 1746 // CHECK7: arraydestroy.done5: 1747 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 1748 // CHECK7-NEXT: ret i32 [[CALL]] 1749 // 1750 // 1751 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1752 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat { 1753 // CHECK7-NEXT: entry: 1754 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1755 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1756 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1757 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1758 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1759 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 1760 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 1761 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 1762 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1763 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1764 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1765 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 1766 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 1767 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 1768 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 1769 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 1770 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 1771 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 1772 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4 1773 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false) 1774 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1775 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 1776 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1 1777 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 1778 // CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 1779 // CHECK7-NEXT: store ptr undef, ptr [[_TMP1]], align 4 1780 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1781 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 1782 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1783 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 1784 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1785 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 1786 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 1787 // CHECK7: arrayctor.loop: 1788 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 1789 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 1790 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 1791 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 1792 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 1793 // CHECK7: arrayctor.cont: 1794 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) 1795 // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 1796 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1797 // CHECK7: omp.inner.for.cond: 1798 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 1799 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]] 1800 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]] 1801 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1802 // CHECK7: omp.inner.for.cond.cleanup: 1803 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1804 // CHECK7: omp.inner.for.body: 1805 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 1806 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1 1807 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1808 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 1809 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]] 1810 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 1811 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] 1812 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] 1813 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]] 1814 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] 1815 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] 1816 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] 1817 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1818 // CHECK7: omp.body.continue: 1819 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1820 // CHECK7: omp.inner.for.inc: 1821 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 1822 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1 1823 // CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]] 1824 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 1825 // CHECK7: omp.inner.for.end: 1826 // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 1827 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1828 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 1829 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 1830 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1831 // CHECK7: arraydestroy.body: 1832 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1833 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1834 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1835 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 1836 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 1837 // CHECK7: arraydestroy.done10: 1838 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 1839 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 1840 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 1841 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]] 1842 // CHECK7: arraydestroy.body12: 1843 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] 1844 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 1845 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] 1846 // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] 1847 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] 1848 // CHECK7: arraydestroy.done16: 1849 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 1850 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 1851 // CHECK7-NEXT: ret i32 [[TMP11]] 1852 // 1853 // 1854 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1855 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1856 // CHECK7-NEXT: entry: 1857 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1858 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1859 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1860 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1861 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1862 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1863 // CHECK7-NEXT: store float [[CONV]], ptr [[F]], align 4 1864 // CHECK7-NEXT: ret void 1865 // 1866 // 1867 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1868 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1869 // CHECK7-NEXT: entry: 1870 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1871 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1872 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1873 // CHECK7-NEXT: ret void 1874 // 1875 // 1876 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1877 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1878 // CHECK7-NEXT: entry: 1879 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1880 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1881 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1882 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 1883 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1884 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 1885 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 1886 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1887 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1888 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1889 // CHECK7-NEXT: store float [[ADD]], ptr [[F]], align 4 1890 // CHECK7-NEXT: ret void 1891 // 1892 // 1893 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1894 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1895 // CHECK7-NEXT: entry: 1896 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1897 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1898 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1899 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1900 // CHECK7-NEXT: ret void 1901 // 1902 // 1903 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1904 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1905 // CHECK7-NEXT: entry: 1906 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1907 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1908 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1909 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1910 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1911 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1912 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 1913 // CHECK7-NEXT: ret void 1914 // 1915 // 1916 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1917 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1918 // CHECK7-NEXT: entry: 1919 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1920 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1921 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1922 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1923 // CHECK7-NEXT: ret void 1924 // 1925 // 1926 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1927 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1928 // CHECK7-NEXT: entry: 1929 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1930 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1931 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1932 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1933 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 1934 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 1935 // CHECK7-NEXT: ret void 1936 // 1937 // 1938 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1939 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1940 // CHECK7-NEXT: entry: 1941 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1942 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1943 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1944 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 1945 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1946 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 1947 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 1948 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 1949 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1950 // CHECK7-NEXT: store i32 [[ADD]], ptr [[F]], align 4 1951 // CHECK7-NEXT: ret void 1952 // 1953 // 1954 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1955 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1956 // CHECK7-NEXT: entry: 1957 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 1958 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 1959 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 1960 // CHECK7-NEXT: ret void 1961 // 1962 // 1963 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp 1964 // CHECK7-SAME: () #[[ATTR0]] { 1965 // CHECK7-NEXT: entry: 1966 // CHECK7-NEXT: call void @__cxx_global_var_init() 1967 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 1968 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 1969 // CHECK7-NEXT: ret void 1970 // 1971 // 1972 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init 1973 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1974 // CHECK9-NEXT: entry: 1975 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 1976 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 1977 // CHECK9-NEXT: ret void 1978 // 1979 // 1980 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1981 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1982 // CHECK9-NEXT: entry: 1983 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1984 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1985 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1986 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 1987 // CHECK9-NEXT: ret void 1988 // 1989 // 1990 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1991 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1992 // CHECK9-NEXT: entry: 1993 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1994 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1995 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1996 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1997 // CHECK9-NEXT: ret void 1998 // 1999 // 2000 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2001 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2002 // CHECK9-NEXT: entry: 2003 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2004 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2005 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2006 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2007 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2008 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2009 // CHECK9-NEXT: store float [[CONV]], ptr [[F]], align 4 2010 // CHECK9-NEXT: ret void 2011 // 2012 // 2013 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2014 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2015 // CHECK9-NEXT: entry: 2016 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2017 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2018 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2019 // CHECK9-NEXT: ret void 2020 // 2021 // 2022 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2023 // CHECK9-SAME: () #[[ATTR0]] { 2024 // CHECK9-NEXT: entry: 2025 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2026 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2027 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2028 // CHECK9-NEXT: ret void 2029 // 2030 // 2031 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2032 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2033 // CHECK9-NEXT: entry: 2034 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2035 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2036 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2037 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2038 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2039 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2040 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2041 // CHECK9-NEXT: ret void 2042 // 2043 // 2044 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2045 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2046 // CHECK9-NEXT: entry: 2047 // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2048 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2049 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2050 // CHECK9: arraydestroy.body: 2051 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2052 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2053 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2054 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2055 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2056 // CHECK9: arraydestroy.done1: 2057 // CHECK9-NEXT: ret void 2058 // 2059 // 2060 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2061 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2062 // CHECK9-NEXT: entry: 2063 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2064 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2065 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2066 // CHECK9-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2067 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2068 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2069 // CHECK9-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2070 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2071 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2072 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2073 // CHECK9-NEXT: store float [[ADD]], ptr [[F]], align 4 2074 // CHECK9-NEXT: ret void 2075 // 2076 // 2077 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2078 // CHECK9-SAME: () #[[ATTR0]] { 2079 // CHECK9-NEXT: entry: 2080 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2081 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2082 // CHECK9-NEXT: ret void 2083 // 2084 // 2085 // CHECK9-LABEL: define {{[^@]+}}@main 2086 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] { 2087 // CHECK9-NEXT: entry: 2088 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2089 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2090 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 2091 // CHECK9-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2092 // CHECK9-NEXT: ret i32 0 2093 // 2094 // 2095 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75 2096 // CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] { 2097 // CHECK9-NEXT: entry: 2098 // CHECK9-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 2099 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 2100 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 2101 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 2102 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined) 2103 // CHECK9-NEXT: ret void 2104 // 2105 // 2106 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined 2107 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] { 2108 // CHECK9-NEXT: entry: 2109 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 2110 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 2111 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2112 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 2113 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 2114 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2115 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2116 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2117 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2118 // CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 2119 // CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 2120 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 2121 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 2122 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 2123 // CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 2124 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 2125 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 2126 // CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 2127 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2128 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 2129 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2130 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2131 // CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 2132 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 2133 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2134 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2135 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2136 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 2137 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2138 // CHECK9: cond.true: 2139 // CHECK9-NEXT: br label [[COND_END:%.*]] 2140 // CHECK9: cond.false: 2141 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2142 // CHECK9-NEXT: br label [[COND_END]] 2143 // CHECK9: cond.end: 2144 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2145 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2146 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2147 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2148 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2149 // CHECK9: omp.inner.for.cond: 2150 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]] 2151 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]] 2152 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2153 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2154 // CHECK9: omp.inner.for.body: 2155 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2156 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2157 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2158 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] 2159 // CHECK9-NEXT: store i32 1, ptr [[G]], align 4, !llvm.access.group [[ACC_GRP4]] 2160 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP4]] 2161 // CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP4]] 2162 // CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP4]] 2163 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 2164 // CHECK9-NEXT: store ptr [[G]], ptr [[TMP9]], align 8, !llvm.access.group [[ACC_GRP4]] 2165 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 2166 // CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP4]] 2167 // CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP4]] 2168 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 2169 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP4]] 2170 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP4]] 2171 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2172 // CHECK9: omp.body.continue: 2173 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2174 // CHECK9: omp.inner.for.inc: 2175 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2176 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 2177 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]] 2178 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 2179 // CHECK9: omp.inner.for.end: 2180 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2181 // CHECK9: omp.loop.exit: 2182 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2183 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 2184 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 2185 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2186 // CHECK9: .omp.final.then: 2187 // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 2188 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] 2189 // CHECK9: .omp.final.done: 2190 // CHECK9-NEXT: ret void 2191 // 2192 // 2193 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp 2194 // CHECK9-SAME: () #[[ATTR0]] { 2195 // CHECK9-NEXT: entry: 2196 // CHECK9-NEXT: call void @__cxx_global_var_init() 2197 // CHECK9-NEXT: call void @__cxx_global_var_init.1() 2198 // CHECK9-NEXT: call void @__cxx_global_var_init.2() 2199 // CHECK9-NEXT: ret void 2200 // 2201 // 2202 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2203 // CHECK9-SAME: () #[[ATTR0]] { 2204 // CHECK9-NEXT: entry: 2205 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) 2206 // CHECK9-NEXT: ret void 2207 // 2208 // 2209 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init 2210 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2211 // CHECK11-NEXT: entry: 2212 // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test) 2213 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 2214 // CHECK11-NEXT: ret void 2215 // 2216 // 2217 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2218 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2219 // CHECK11-NEXT: entry: 2220 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2221 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2222 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2223 // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 2224 // CHECK11-NEXT: ret void 2225 // 2226 // 2227 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2228 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2229 // CHECK11-NEXT: entry: 2230 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2231 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2232 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2233 // CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2234 // CHECK11-NEXT: ret void 2235 // 2236 // 2237 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2238 // CHECK11-SAME: () #[[ATTR0]] { 2239 // CHECK11-NEXT: entry: 2240 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00) 2241 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00) 2242 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 2243 // CHECK11-NEXT: ret void 2244 // 2245 // 2246 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2247 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2248 // CHECK11-NEXT: entry: 2249 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2250 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2251 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2252 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2253 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2254 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2255 // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 2256 // CHECK11-NEXT: ret void 2257 // 2258 // 2259 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2260 // CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] { 2261 // CHECK11-NEXT: entry: 2262 // CHECK11-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 2263 // CHECK11-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 2264 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2265 // CHECK11: arraydestroy.body: 2266 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2267 // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2268 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2269 // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 2270 // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2271 // CHECK11: arraydestroy.done1: 2272 // CHECK11-NEXT: ret void 2273 // 2274 // 2275 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2276 // CHECK11-SAME: () #[[ATTR0]] { 2277 // CHECK11-NEXT: entry: 2278 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00) 2279 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 2280 // CHECK11-NEXT: ret void 2281 // 2282 // 2283 // CHECK11-LABEL: define {{[^@]+}}@main 2284 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 2285 // CHECK11-NEXT: entry: 2286 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2287 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 2288 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 2289 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 2290 // CHECK11-NEXT: ret i32 0 2291 // 2292 // 2293 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2294 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2295 // CHECK11-NEXT: entry: 2296 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2297 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2298 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2299 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2300 // CHECK11-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 2301 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2302 // CHECK11-NEXT: store float [[CONV]], ptr [[F]], align 4 2303 // CHECK11-NEXT: ret void 2304 // 2305 // 2306 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2307 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2308 // CHECK11-NEXT: entry: 2309 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2310 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2311 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2312 // CHECK11-NEXT: ret void 2313 // 2314 // 2315 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2316 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2317 // CHECK11-NEXT: entry: 2318 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 2319 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2320 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 2321 // CHECK11-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 2322 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 2323 // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 2324 // CHECK11-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 2325 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 2326 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2327 // CHECK11-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2328 // CHECK11-NEXT: store float [[ADD]], ptr [[F]], align 4 2329 // CHECK11-NEXT: ret void 2330 // 2331 // 2332 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_simd_private_codegen.cpp 2333 // CHECK11-SAME: () #[[ATTR0]] { 2334 // CHECK11-NEXT: entry: 2335 // CHECK11-NEXT: call void @__cxx_global_var_init() 2336 // CHECK11-NEXT: call void @__cxx_global_var_init.1() 2337 // CHECK11-NEXT: call void @__cxx_global_var_init.2() 2338 // CHECK11-NEXT: ret void 2339 // 2340