1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 9 10 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 22 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 26 27 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // Test host codegen. 37 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 38 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 39 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 40 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 41 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 42 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 43 44 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 46 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 49 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 50 51 // Test target codegen - host bc file has to be created first. 52 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 53 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 54 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 55 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 56 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 57 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 58 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 59 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 60 61 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 62 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 64 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 65 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 66 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 68 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 69 70 // expected-no-diagnostics 71 #ifndef HEADER 72 #define HEADER 73 74 75 76 77 // We have 8 target regions, but only 7 that actually will generate offloading 78 // code, only 6 will have mapped arguments, and only 4 have all-constant map 79 // sizes. 80 81 82 83 // Check target registration is registered as a Ctor. 84 85 86 template<typename tx, typename ty> 87 struct TT{ 88 tx X; 89 ty Y; 90 }; 91 92 int global; 93 94 int foo(int n) { 95 int a = 0; 96 short aa = 0; 97 float b[10]; 98 float bn[n]; 99 double c[5][10]; 100 double cn[5][n]; 101 TT<long long, char> d; 102 103 #pragma omp target teams distribute num_teams(a) thread_limit(a) firstprivate(aa) nowait 104 for (int i = 0; i < 10; ++i) { 105 } 106 107 #pragma omp target teams distribute if(target: 0) 108 for (int i = 0; i < 10; ++i) { 109 a += 1; 110 } 111 112 113 #pragma omp target teams distribute if(target: 1) 114 for (int i = 0; i < 10; ++i) { 115 aa += 1; 116 } 117 118 119 120 #pragma omp target teams distribute if(target: n>10) 121 for (int i = 0; i < 10; ++i) { 122 a += 1; 123 aa += 1; 124 } 125 126 // We capture 3 VLA sizes in this target region 127 128 129 130 131 132 // The names below are not necessarily consistent with the names used for the 133 // addresses above as some are repeated. 134 135 136 137 138 139 140 141 142 143 144 145 #pragma omp target teams distribute if(target: n>20) dist_schedule(static, n) 146 for (int i = 0; i < 10; ++i) { 147 a += 1; 148 b[2] += 1.0; 149 bn[3] += 1.0; 150 c[1][2] += 1.0; 151 cn[1][3] += 1.0; 152 d.X += 1; 153 d.Y += 1; 154 } 155 156 return a; 157 } 158 159 // Check that the offloading functions are emitted and that the arguments are 160 // correct and loaded correctly for the target regions in foo(). 161 162 163 164 165 // Create stack storage and store argument in there. 166 167 // Create stack storage and store argument in there. 168 169 // Create stack storage and store argument in there. 170 171 // Create local storage for each capture. 172 173 174 175 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 176 177 template<typename tx> 178 tx ftemplate(int n) { 179 tx a = 0; 180 short aa = 0; 181 tx b[10]; 182 183 #pragma omp target teams distribute if(target: n>40) 184 for (int i = 0; i < 10; ++i) { 185 a += 1; 186 aa += 1; 187 b[2] += 1; 188 } 189 190 return a; 191 } 192 193 static 194 int fstatic(int n) { 195 int a = 0; 196 short aa = 0; 197 char aaa = 0; 198 int b[10]; 199 200 #pragma omp target teams distribute if(target: n>50) 201 for (int i = a; i < n; ++i) { 202 a += 1; 203 aa += 1; 204 aaa += 1; 205 b[2] += 1; 206 } 207 208 return a; 209 } 210 211 struct S1 { 212 double a; 213 214 int r1(int n){ 215 int b = n+1; 216 short int c[2][n]; 217 218 #pragma omp target teams distribute if(target: n>60) 219 for (int i = 0; i < 10; ++i) { 220 this->a = (double)b + 1.5; 221 c[1][1] = ++a; 222 } 223 224 return c[1][1] + (int)b; 225 } 226 }; 227 228 int bar(int n){ 229 int a = 0; 230 231 a += foo(n); 232 233 S1 S; 234 a += S.r1(n); 235 236 a += fstatic(n); 237 238 a += ftemplate<int>(n); 239 240 return a; 241 } 242 243 244 245 // We capture 2 VLA sizes in this target region 246 247 248 // The names below are not necessarily consistent with the names used for the 249 // addresses above as some are repeated. 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 // Check that the offloading functions are emitted and that the arguments are 272 // correct and loaded correctly for the target regions of the callees of bar(). 273 274 // Create local storage for each capture. 275 // Store captures in the context. 276 277 278 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 279 280 281 // Create local storage for each capture. 282 // Store captures in the context. 283 284 285 286 287 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 288 289 // Create local storage for each capture. 290 // Store captures in the context. 291 292 293 294 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 295 296 #endif 297 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 298 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 299 // CHECK1-NEXT: entry: 300 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 301 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 302 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 303 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 304 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 305 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 306 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 307 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 308 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 309 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 310 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 311 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 312 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 8 314 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 315 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 316 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 317 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 318 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 319 // CHECK1-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 8 321 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 8 323 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 324 // CHECK1-NEXT: [[A_CASTED8:%.*]] = alloca i64, align 8 325 // CHECK1-NEXT: [[AA_CASTED9:%.*]] = alloca i64, align 8 326 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 8 327 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 8 328 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 8 329 // CHECK1-NEXT: [[_TMP13:%.*]] = alloca i32, align 4 330 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 331 // CHECK1-NEXT: [[A_CASTED18:%.*]] = alloca i64, align 8 332 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED19:%.*]] = alloca i64, align 8 333 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [10 x ptr], align 8 334 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [10 x ptr], align 8 335 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [10 x ptr], align 8 336 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 337 // CHECK1-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 338 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 339 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 340 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 341 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 342 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 343 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 344 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 345 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 346 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 347 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 348 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 349 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 350 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 351 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 352 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8 353 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 354 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4 355 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 356 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_2]], align 4 357 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2 358 // CHECK1-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2 359 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8 360 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 361 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 362 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 363 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 364 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4 365 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 8 366 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 367 // CHECK1-NEXT: store i64 [[TMP10]], ptr [[TMP15]], align 8 368 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 369 // CHECK1-NEXT: store i64 [[TMP10]], ptr [[TMP16]], align 8 370 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 371 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 372 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 373 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP18]], align 8 374 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 375 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP19]], align 8 376 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 377 // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 378 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 379 // CHECK1-NEXT: store i64 [[TMP14]], ptr [[TMP21]], align 8 380 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 381 // CHECK1-NEXT: store i64 [[TMP14]], ptr [[TMP22]], align 8 382 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 383 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 384 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 385 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 386 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 387 // CHECK1-NEXT: [[TMP27:%.*]] = load i16, ptr [[AA]], align 2 388 // CHECK1-NEXT: store i16 [[TMP27]], ptr [[TMP26]], align 4 389 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 390 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 391 // CHECK1-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4 392 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2 393 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 394 // CHECK1-NEXT: store i32 [[TMP31]], ptr [[TMP30]], align 4 395 // CHECK1-NEXT: [[TMP32:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1) 396 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP32]], i32 0, i32 0 397 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP33]], i32 0, i32 0 398 // CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP34]], align 8 399 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false) 400 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP32]], i32 0, i32 1 401 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP36]], i32 0, i32 0 402 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP37]], ptr align 8 [[TMP24]], i64 24, i1 false) 403 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 1 404 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP38]], ptr align 8 [[TMP25]], i64 24, i1 false) 405 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 2 406 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP39]], ptr align 8 @.offload_sizes, i64 24, i1 false) 407 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 3 408 // CHECK1-NEXT: [[TMP41:%.*]] = load i16, ptr [[AA]], align 2 409 // CHECK1-NEXT: store i16 [[TMP41]], ptr [[TMP40]], align 8 410 // CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP32]]) 411 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[A]], align 4 412 // CHECK1-NEXT: store i32 [[TMP43]], ptr [[A_CASTED]], align 4 413 // CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[A_CASTED]], align 8 414 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP44]]) #[[ATTR3:[0-9]+]] 415 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[AA]], align 2 416 // CHECK1-NEXT: store i16 [[TMP45]], ptr [[AA_CASTED4]], align 2 417 // CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[AA_CASTED4]], align 8 418 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 419 // CHECK1-NEXT: store i64 [[TMP46]], ptr [[TMP47]], align 8 420 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 421 // CHECK1-NEXT: store i64 [[TMP46]], ptr [[TMP48]], align 8 422 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0 423 // CHECK1-NEXT: store ptr null, ptr [[TMP49]], align 8 424 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 425 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 426 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 427 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 428 // CHECK1-NEXT: store i32 1, ptr [[TMP52]], align 4 429 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 430 // CHECK1-NEXT: store i32 1, ptr [[TMP53]], align 4 431 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 432 // CHECK1-NEXT: store ptr [[TMP50]], ptr [[TMP54]], align 8 433 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 434 // CHECK1-NEXT: store ptr [[TMP51]], ptr [[TMP55]], align 8 435 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 436 // CHECK1-NEXT: store ptr @.offload_sizes.4, ptr [[TMP56]], align 8 437 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 438 // CHECK1-NEXT: store ptr @.offload_maptypes.5, ptr [[TMP57]], align 8 439 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 440 // CHECK1-NEXT: store ptr null, ptr [[TMP58]], align 8 441 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 442 // CHECK1-NEXT: store ptr null, ptr [[TMP59]], align 8 443 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 444 // CHECK1-NEXT: store i64 10, ptr [[TMP60]], align 8 445 // CHECK1-NEXT: [[TMP61:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, ptr [[KERNEL_ARGS]]) 446 // CHECK1-NEXT: [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0 447 // CHECK1-NEXT: br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 448 // CHECK1: omp_offload.failed: 449 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP46]]) #[[ATTR3]] 450 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 451 // CHECK1: omp_offload.cont: 452 // CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[A]], align 4 453 // CHECK1-NEXT: store i32 [[TMP63]], ptr [[A_CASTED8]], align 4 454 // CHECK1-NEXT: [[TMP64:%.*]] = load i64, ptr [[A_CASTED8]], align 8 455 // CHECK1-NEXT: [[TMP65:%.*]] = load i16, ptr [[AA]], align 2 456 // CHECK1-NEXT: store i16 [[TMP65]], ptr [[AA_CASTED9]], align 2 457 // CHECK1-NEXT: [[TMP66:%.*]] = load i64, ptr [[AA_CASTED9]], align 8 458 // CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[N_ADDR]], align 4 459 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP67]], 10 460 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 461 // CHECK1: omp_if.then: 462 // CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 463 // CHECK1-NEXT: store i64 [[TMP64]], ptr [[TMP68]], align 8 464 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 465 // CHECK1-NEXT: store i64 [[TMP64]], ptr [[TMP69]], align 8 466 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 467 // CHECK1-NEXT: store ptr null, ptr [[TMP70]], align 8 468 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 469 // CHECK1-NEXT: store i64 [[TMP66]], ptr [[TMP71]], align 8 470 // CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 471 // CHECK1-NEXT: store i64 [[TMP66]], ptr [[TMP72]], align 8 472 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 473 // CHECK1-NEXT: store ptr null, ptr [[TMP73]], align 8 474 // CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 475 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 476 // CHECK1-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 477 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0 478 // CHECK1-NEXT: store i32 1, ptr [[TMP76]], align 4 479 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1 480 // CHECK1-NEXT: store i32 2, ptr [[TMP77]], align 4 481 // CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2 482 // CHECK1-NEXT: store ptr [[TMP74]], ptr [[TMP78]], align 8 483 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3 484 // CHECK1-NEXT: store ptr [[TMP75]], ptr [[TMP79]], align 8 485 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4 486 // CHECK1-NEXT: store ptr @.offload_sizes.7, ptr [[TMP80]], align 8 487 // CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5 488 // CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP81]], align 8 489 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6 490 // CHECK1-NEXT: store ptr null, ptr [[TMP82]], align 8 491 // CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7 492 // CHECK1-NEXT: store ptr null, ptr [[TMP83]], align 8 493 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8 494 // CHECK1-NEXT: store i64 10, ptr [[TMP84]], align 8 495 // CHECK1-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, ptr [[KERNEL_ARGS14]]) 496 // CHECK1-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 497 // CHECK1-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] 498 // CHECK1: omp_offload.failed15: 499 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP64]], i64 [[TMP66]]) #[[ATTR3]] 500 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT16]] 501 // CHECK1: omp_offload.cont16: 502 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 503 // CHECK1: omp_if.else: 504 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP64]], i64 [[TMP66]]) #[[ATTR3]] 505 // CHECK1-NEXT: br label [[OMP_IF_END]] 506 // CHECK1: omp_if.end: 507 // CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[N_ADDR]], align 4 508 // CHECK1-NEXT: store i32 [[TMP87]], ptr [[DOTCAPTURE_EXPR_17]], align 4 509 // CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[A]], align 4 510 // CHECK1-NEXT: store i32 [[TMP88]], ptr [[A_CASTED18]], align 4 511 // CHECK1-NEXT: [[TMP89:%.*]] = load i64, ptr [[A_CASTED18]], align 8 512 // CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 513 // CHECK1-NEXT: store i32 [[TMP90]], ptr [[DOTCAPTURE_EXPR__CASTED19]], align 4 514 // CHECK1-NEXT: [[TMP91:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED19]], align 8 515 // CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[N_ADDR]], align 4 516 // CHECK1-NEXT: [[CMP20:%.*]] = icmp sgt i32 [[TMP92]], 20 517 // CHECK1-NEXT: br i1 [[CMP20]], label [[OMP_IF_THEN21:%.*]], label [[OMP_IF_ELSE29:%.*]] 518 // CHECK1: omp_if.then21: 519 // CHECK1-NEXT: [[TMP93:%.*]] = mul nuw i64 [[TMP2]], 4 520 // CHECK1-NEXT: [[TMP94:%.*]] = mul nuw i64 5, [[TMP5]] 521 // CHECK1-NEXT: [[TMP95:%.*]] = mul nuw i64 [[TMP94]], 8 522 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.10, i64 80, i1 false) 523 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 524 // CHECK1-NEXT: store i64 [[TMP89]], ptr [[TMP96]], align 8 525 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 526 // CHECK1-NEXT: store i64 [[TMP89]], ptr [[TMP97]], align 8 527 // CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0 528 // CHECK1-NEXT: store ptr null, ptr [[TMP98]], align 8 529 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 530 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP99]], align 8 531 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 532 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP100]], align 8 533 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1 534 // CHECK1-NEXT: store ptr null, ptr [[TMP101]], align 8 535 // CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 536 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP102]], align 8 537 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 538 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP103]], align 8 539 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2 540 // CHECK1-NEXT: store ptr null, ptr [[TMP104]], align 8 541 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 542 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP105]], align 8 543 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 544 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP106]], align 8 545 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 546 // CHECK1-NEXT: store i64 [[TMP93]], ptr [[TMP107]], align 8 547 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3 548 // CHECK1-NEXT: store ptr null, ptr [[TMP108]], align 8 549 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 4 550 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP109]], align 8 551 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 4 552 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP110]], align 8 553 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 4 554 // CHECK1-NEXT: store ptr null, ptr [[TMP111]], align 8 555 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 5 556 // CHECK1-NEXT: store i64 5, ptr [[TMP112]], align 8 557 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 5 558 // CHECK1-NEXT: store i64 5, ptr [[TMP113]], align 8 559 // CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 5 560 // CHECK1-NEXT: store ptr null, ptr [[TMP114]], align 8 561 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 6 562 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP115]], align 8 563 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 6 564 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP116]], align 8 565 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 6 566 // CHECK1-NEXT: store ptr null, ptr [[TMP117]], align 8 567 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 7 568 // CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP118]], align 8 569 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 7 570 // CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP119]], align 8 571 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 572 // CHECK1-NEXT: store i64 [[TMP95]], ptr [[TMP120]], align 8 573 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 7 574 // CHECK1-NEXT: store ptr null, ptr [[TMP121]], align 8 575 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 8 576 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP122]], align 8 577 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 8 578 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP123]], align 8 579 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 8 580 // CHECK1-NEXT: store ptr null, ptr [[TMP124]], align 8 581 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 9 582 // CHECK1-NEXT: store i64 [[TMP91]], ptr [[TMP125]], align 8 583 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 9 584 // CHECK1-NEXT: store i64 [[TMP91]], ptr [[TMP126]], align 8 585 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 9 586 // CHECK1-NEXT: store ptr null, ptr [[TMP127]], align 8 587 // CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 588 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 589 // CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 590 // CHECK1-NEXT: [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 591 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 0 592 // CHECK1-NEXT: store i32 1, ptr [[TMP131]], align 4 593 // CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 1 594 // CHECK1-NEXT: store i32 10, ptr [[TMP132]], align 4 595 // CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 2 596 // CHECK1-NEXT: store ptr [[TMP128]], ptr [[TMP133]], align 8 597 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 3 598 // CHECK1-NEXT: store ptr [[TMP129]], ptr [[TMP134]], align 8 599 // CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 4 600 // CHECK1-NEXT: store ptr [[TMP130]], ptr [[TMP135]], align 8 601 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 5 602 // CHECK1-NEXT: store ptr @.offload_maptypes.11, ptr [[TMP136]], align 8 603 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 6 604 // CHECK1-NEXT: store ptr null, ptr [[TMP137]], align 8 605 // CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 7 606 // CHECK1-NEXT: store ptr null, ptr [[TMP138]], align 8 607 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 8 608 // CHECK1-NEXT: store i64 10, ptr [[TMP139]], align 8 609 // CHECK1-NEXT: [[TMP140:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, ptr [[KERNEL_ARGS26]]) 610 // CHECK1-NEXT: [[TMP141:%.*]] = icmp ne i32 [[TMP140]], 0 611 // CHECK1-NEXT: br i1 [[TMP141]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] 612 // CHECK1: omp_offload.failed27: 613 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP89]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP91]]) #[[ATTR3]] 614 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT28]] 615 // CHECK1: omp_offload.cont28: 616 // CHECK1-NEXT: br label [[OMP_IF_END30:%.*]] 617 // CHECK1: omp_if.else29: 618 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP89]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP91]]) #[[ATTR3]] 619 // CHECK1-NEXT: br label [[OMP_IF_END30]] 620 // CHECK1: omp_if.end30: 621 // CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[A]], align 4 622 // CHECK1-NEXT: [[TMP143:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 623 // CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP143]]) 624 // CHECK1-NEXT: ret i32 [[TMP142]] 625 // 626 // 627 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 628 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 629 // CHECK1-NEXT: entry: 630 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 631 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 632 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 633 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 634 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 635 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 636 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 637 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 638 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 639 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 640 // CHECK1-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 641 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 642 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 643 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 644 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @.omp_outlined., i64 [[TMP4]]) 645 // CHECK1-NEXT: ret void 646 // 647 // 648 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 649 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 650 // CHECK1-NEXT: entry: 651 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 652 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 653 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 654 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 655 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 656 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 657 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 658 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 659 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 660 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 661 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 662 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 663 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 664 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 665 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 666 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 667 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 668 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 669 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 670 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 671 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 672 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 673 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 674 // CHECK1: cond.true: 675 // CHECK1-NEXT: br label [[COND_END:%.*]] 676 // CHECK1: cond.false: 677 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 678 // CHECK1-NEXT: br label [[COND_END]] 679 // CHECK1: cond.end: 680 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 681 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 682 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 683 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 684 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 685 // CHECK1: omp.inner.for.cond: 686 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 687 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 688 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 689 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 690 // CHECK1: omp.inner.for.body: 691 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 692 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 693 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 694 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 695 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 696 // CHECK1: omp.body.continue: 697 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 698 // CHECK1: omp.inner.for.inc: 699 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 700 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 701 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 702 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 703 // CHECK1: omp.inner.for.end: 704 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 705 // CHECK1: omp.loop.exit: 706 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 707 // CHECK1-NEXT: ret void 708 // 709 // 710 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. 711 // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 712 // CHECK1-NEXT: entry: 713 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 714 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 715 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 716 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 717 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8 718 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 719 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 720 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 721 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 722 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 723 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8 724 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0 725 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 726 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 727 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1 728 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 729 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8 730 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2 731 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 732 // CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8 733 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3 734 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 735 // CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8 736 // CHECK1-NEXT: ret void 737 // 738 // 739 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 740 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 741 // CHECK1-NEXT: entry: 742 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 743 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 744 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 745 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 746 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 747 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 748 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 749 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 750 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8 751 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8 752 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 753 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 754 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i64, align 8 755 // CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 756 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 757 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 758 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 759 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 760 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 761 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 762 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 763 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 764 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 765 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 766 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 767 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) 768 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 769 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 770 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 771 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 772 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 773 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 774 // CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 775 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 776 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !21 777 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !21 778 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 779 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 780 // CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 781 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !21 782 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !21 783 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !21 784 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !21 785 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1 786 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2 787 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 788 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP17]], align 4 789 // CHECK1-NEXT: store i32 1, ptr [[KERNEL_ARGS_I]], align 4, !noalias !21 790 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 791 // CHECK1-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias !21 792 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 793 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 8, !noalias !21 794 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 795 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 8, !noalias !21 796 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 797 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 8, !noalias !21 798 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 799 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 8, !noalias !21 800 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 801 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8, !noalias !21 802 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 803 // CHECK1-NEXT: store ptr null, ptr [[TMP26]], align 8, !noalias !21 804 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 805 // CHECK1-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias !21 806 // CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel_nowait(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 [[TMP19]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS_I]], i32 0, ptr null, i32 0, ptr null) 807 // CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 808 // CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 809 // CHECK1: omp_offload.failed.i: 810 // CHECK1-NEXT: [[TMP30:%.*]] = load i16, ptr [[TMP12]], align 2 811 // CHECK1-NEXT: store i16 [[TMP30]], ptr [[AA_CASTED_I]], align 2, !noalias !21 812 // CHECK1-NEXT: [[TMP31:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !21 813 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP16]], align 4 814 // CHECK1-NEXT: store i32 [[TMP32]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21 815 // CHECK1-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !21 816 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP17]], align 4 817 // CHECK1-NEXT: store i32 [[TMP34]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21 818 // CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias !21 819 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP31]], i64 [[TMP33]], i64 [[TMP35]]) #[[ATTR3]] 820 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 821 // CHECK1: .omp_outlined..1.exit: 822 // CHECK1-NEXT: ret i32 0 823 // 824 // 825 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 826 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { 827 // CHECK1-NEXT: entry: 828 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 829 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 830 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 831 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 832 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 833 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 834 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @.omp_outlined..2, i64 [[TMP1]]) 835 // CHECK1-NEXT: ret void 836 // 837 // 838 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 839 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 840 // CHECK1-NEXT: entry: 841 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 842 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 843 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 844 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 845 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 846 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 847 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 848 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 849 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 850 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 851 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 852 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 853 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 854 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 855 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 856 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 857 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 858 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 859 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 860 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 861 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 862 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 863 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 864 // CHECK1: cond.true: 865 // CHECK1-NEXT: br label [[COND_END:%.*]] 866 // CHECK1: cond.false: 867 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 868 // CHECK1-NEXT: br label [[COND_END]] 869 // CHECK1: cond.end: 870 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 871 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 872 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 873 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 874 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 875 // CHECK1: omp.inner.for.cond: 876 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 877 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 878 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 879 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 880 // CHECK1: omp.inner.for.body: 881 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 882 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 883 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 884 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 885 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 886 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 887 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4 888 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 889 // CHECK1: omp.body.continue: 890 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 891 // CHECK1: omp.inner.for.inc: 892 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 893 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 894 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 895 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 896 // CHECK1: omp.inner.for.end: 897 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 898 // CHECK1: omp.loop.exit: 899 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 900 // CHECK1-NEXT: ret void 901 // 902 // 903 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 904 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 905 // CHECK1-NEXT: entry: 906 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 907 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 908 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 909 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 910 // CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 911 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 912 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @.omp_outlined..3, i64 [[TMP1]]) 913 // CHECK1-NEXT: ret void 914 // 915 // 916 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 917 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 918 // CHECK1-NEXT: entry: 919 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 920 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 921 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 922 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 923 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 924 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 925 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 926 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 927 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 928 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 929 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 930 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 931 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 932 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 933 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 934 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 935 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 936 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 937 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 938 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 939 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 940 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 941 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 942 // CHECK1: cond.true: 943 // CHECK1-NEXT: br label [[COND_END:%.*]] 944 // CHECK1: cond.false: 945 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 946 // CHECK1-NEXT: br label [[COND_END]] 947 // CHECK1: cond.end: 948 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 949 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 950 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 951 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 952 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 953 // CHECK1: omp.inner.for.cond: 954 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 955 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 956 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 957 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 958 // CHECK1: omp.inner.for.body: 959 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 960 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 961 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 962 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 963 // CHECK1-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2 964 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 965 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 966 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 967 // CHECK1-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2 968 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 969 // CHECK1: omp.body.continue: 970 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 971 // CHECK1: omp.inner.for.inc: 972 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 973 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 974 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 975 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 976 // CHECK1: omp.inner.for.end: 977 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 978 // CHECK1: omp.loop.exit: 979 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 980 // CHECK1-NEXT: ret void 981 // 982 // 983 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 984 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 985 // CHECK1-NEXT: entry: 986 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 987 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 988 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 989 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 990 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 991 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 992 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 993 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 994 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 995 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 996 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 997 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 998 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..6, i64 [[TMP1]], i64 [[TMP3]]) 999 // CHECK1-NEXT: ret void 1000 // 1001 // 1002 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 1003 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1004 // CHECK1-NEXT: entry: 1005 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1006 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1007 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1008 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1009 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1010 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1011 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1012 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1013 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1014 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1015 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1016 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1017 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1018 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1019 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1020 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1021 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 1022 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1023 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1024 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1025 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 1026 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1027 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1028 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 1029 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1030 // CHECK1: cond.true: 1031 // CHECK1-NEXT: br label [[COND_END:%.*]] 1032 // CHECK1: cond.false: 1033 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1034 // CHECK1-NEXT: br label [[COND_END]] 1035 // CHECK1: cond.end: 1036 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1037 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1038 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1039 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 1040 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1041 // CHECK1: omp.inner.for.cond: 1042 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1043 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1044 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1045 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1046 // CHECK1: omp.inner.for.body: 1047 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1048 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 1049 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1050 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1051 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 1052 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 1053 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4 1054 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1055 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 1056 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 1057 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1058 // CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 1059 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1060 // CHECK1: omp.body.continue: 1061 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1062 // CHECK1: omp.inner.for.inc: 1063 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1064 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 1065 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 1066 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1067 // CHECK1: omp.inner.for.end: 1068 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1069 // CHECK1: omp.loop.exit: 1070 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 1071 // CHECK1-NEXT: ret void 1072 // 1073 // 1074 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 1075 // CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1076 // CHECK1-NEXT: entry: 1077 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1078 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1079 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1080 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 1081 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1082 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1083 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1084 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 1085 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1086 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1087 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1088 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1089 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1090 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1091 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1092 // CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 1093 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1094 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1095 // CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 1096 // CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 1097 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1098 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 1099 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1100 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1101 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 1102 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1103 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1104 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 1105 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 1106 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1107 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 1108 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 1109 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 1110 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 1111 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 1112 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 1113 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..9, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 1114 // CHECK1-NEXT: ret void 1115 // 1116 // 1117 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 1118 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1119 // CHECK1-NEXT: entry: 1120 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1121 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1122 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1123 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1124 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1125 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 1126 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1127 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1128 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1129 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 1130 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 1131 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1132 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1133 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1134 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1135 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1136 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1137 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1138 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1139 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1140 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1141 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1142 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1143 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1144 // CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 1145 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1146 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1147 // CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 1148 // CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 1149 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 1150 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 1151 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1152 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1153 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 1154 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1155 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1156 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 1157 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 1158 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 1159 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1160 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 1161 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1162 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1163 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 1164 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1165 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 1166 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 1167 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1168 // CHECK1: omp.dispatch.cond: 1169 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1170 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 1171 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1172 // CHECK1: cond.true: 1173 // CHECK1-NEXT: br label [[COND_END:%.*]] 1174 // CHECK1: cond.false: 1175 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1176 // CHECK1-NEXT: br label [[COND_END]] 1177 // CHECK1: cond.end: 1178 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1179 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1180 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1181 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 1182 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1183 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1184 // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1185 // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1186 // CHECK1: omp.dispatch.body: 1187 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1188 // CHECK1: omp.inner.for.cond: 1189 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]] 1190 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]] 1191 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 1192 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1193 // CHECK1: omp.inner.for.body: 1194 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] 1195 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 1196 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1197 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] 1198 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] 1199 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 1200 // CHECK1-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] 1201 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 1202 // CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] 1203 // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double 1204 // CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 1205 // CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 1206 // CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] 1207 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 1208 // CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP22]] 1209 // CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 1210 // CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 1211 // CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 1212 // CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP22]] 1213 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 1214 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 1215 // CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP22]] 1216 // CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 1217 // CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP22]] 1218 // CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 1219 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 1220 // CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 1221 // CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP22]] 1222 // CHECK1-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 1223 // CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP22]] 1224 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 1225 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP22]] 1226 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 1227 // CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP22]] 1228 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 1229 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP22]] 1230 // CHECK1-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 1231 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 1232 // CHECK1-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 1233 // CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP22]] 1234 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1235 // CHECK1: omp.body.continue: 1236 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1237 // CHECK1: omp.inner.for.inc: 1238 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] 1239 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 1240 // CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]] 1241 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 1242 // CHECK1: omp.inner.for.end: 1243 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1244 // CHECK1: omp.dispatch.inc: 1245 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1246 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1247 // CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 1248 // CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 1249 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1250 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 1251 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 1252 // CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 1253 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1254 // CHECK1: omp.dispatch.end: 1255 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 1256 // CHECK1-NEXT: ret void 1257 // 1258 // 1259 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1260 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1261 // CHECK1-NEXT: entry: 1262 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1263 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1264 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1265 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1266 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1267 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1268 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1269 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 1270 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1271 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 4 1272 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 1273 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1274 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 1275 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1276 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 1277 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 1278 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1279 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 1280 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1281 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 1282 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 1283 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1284 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 1285 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1286 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 1287 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 1288 // CHECK1-NEXT: ret i32 [[TMP8]] 1289 // 1290 // 1291 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1292 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1293 // CHECK1-NEXT: entry: 1294 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1295 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1296 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1297 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 1298 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1299 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1300 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 1301 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 1302 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 1303 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1304 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1305 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1306 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1307 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1308 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1309 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1310 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4 1311 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 1312 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1313 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() 1314 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8 1315 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1316 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1317 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 1318 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4 1319 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 1320 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 1321 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 1322 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1323 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1324 // CHECK1: omp_if.then: 1325 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 1326 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1327 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1328 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.13, i64 40, i1 false) 1329 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1330 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 8 1331 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1332 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP11]], align 8 1333 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1334 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8 1335 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1336 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 8 1337 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1338 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 8 1339 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1340 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8 1341 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1342 // CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 8 1343 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1344 // CHECK1-NEXT: store i64 2, ptr [[TMP17]], align 8 1345 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1346 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 1347 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1348 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 8 1349 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1350 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 8 1351 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1352 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 1353 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1354 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 8 1355 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1356 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 8 1357 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1358 // CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 8 1359 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1360 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8 1361 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1362 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1363 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1364 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1365 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1366 // CHECK1-NEXT: store i32 1, ptr [[TMP29]], align 4 1367 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1368 // CHECK1-NEXT: store i32 5, ptr [[TMP30]], align 4 1369 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1370 // CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8 1371 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1372 // CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 8 1373 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1374 // CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 8 1375 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1376 // CHECK1-NEXT: store ptr @.offload_maptypes.14, ptr [[TMP34]], align 8 1377 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1378 // CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 8 1379 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1380 // CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 8 1381 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1382 // CHECK1-NEXT: store i64 10, ptr [[TMP37]], align 8 1383 // CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, ptr [[KERNEL_ARGS]]) 1384 // CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 1385 // CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1386 // CHECK1: omp_offload.failed: 1387 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] 1388 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1389 // CHECK1: omp_offload.cont: 1390 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1391 // CHECK1: omp_if.else: 1392 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]] 1393 // CHECK1-NEXT: br label [[OMP_IF_END]] 1394 // CHECK1: omp_if.end: 1395 // CHECK1-NEXT: [[TMP40:%.*]] = mul nsw i64 1, [[TMP2]] 1396 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP40]] 1397 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 1398 // CHECK1-NEXT: [[TMP41:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 1399 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP41]] to i32 1400 // CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[B]], align 4 1401 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP42]] 1402 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 1403 // CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP43]]) 1404 // CHECK1-NEXT: ret i32 [[ADD3]] 1405 // 1406 // 1407 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1408 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1409 // CHECK1-NEXT: entry: 1410 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1411 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1412 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1413 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1414 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1415 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1416 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1417 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1418 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1419 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8 1420 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8 1421 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8 1422 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1423 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1424 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1425 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1426 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1427 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1428 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 1429 // CHECK1-NEXT: store i8 0, ptr [[AAA]], align 1 1430 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 1431 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[N_CASTED]], align 4 1432 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[N_CASTED]], align 8 1433 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 1434 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[A_CASTED]], align 4 1435 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8 1436 // CHECK1-NEXT: [[TMP4:%.*]] = load i16, ptr [[AA]], align 2 1437 // CHECK1-NEXT: store i16 [[TMP4]], ptr [[AA_CASTED]], align 2 1438 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1439 // CHECK1-NEXT: [[TMP6:%.*]] = load i8, ptr [[AAA]], align 1 1440 // CHECK1-NEXT: store i8 [[TMP6]], ptr [[AAA_CASTED]], align 1 1441 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 1442 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 4 1443 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 1444 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1445 // CHECK1: omp_if.then: 1446 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1447 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP9]], align 8 1448 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1449 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP10]], align 8 1450 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1451 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8 1452 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1453 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP12]], align 8 1454 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1455 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP13]], align 8 1456 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1457 // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8 1458 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1459 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP15]], align 8 1460 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1461 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP16]], align 8 1462 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1463 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8 1464 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1465 // CHECK1-NEXT: store i64 [[TMP7]], ptr [[TMP18]], align 8 1466 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1467 // CHECK1-NEXT: store i64 [[TMP7]], ptr [[TMP19]], align 8 1468 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1469 // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 1470 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1471 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP21]], align 8 1472 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1473 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP22]], align 8 1474 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1475 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 1476 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1477 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1478 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 4 1479 // CHECK1-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 4 1480 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 4 1481 // CHECK1-NEXT: store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 4 1482 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 1483 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1484 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]] 1485 // CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 1486 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 1487 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1488 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 1489 // CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4 1490 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 1491 // CHECK1-NEXT: [[ADD5:%.*]] = add i32 [[TMP30]], 1 1492 // CHECK1-NEXT: [[TMP31:%.*]] = zext i32 [[ADD5]] to i64 1493 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1494 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1495 // CHECK1-NEXT: store i32 1, ptr [[TMP32]], align 4 1496 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1497 // CHECK1-NEXT: store i32 5, ptr [[TMP33]], align 4 1498 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1499 // CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP34]], align 8 1500 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1501 // CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP35]], align 8 1502 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1503 // CHECK1-NEXT: store ptr @.offload_sizes.16, ptr [[TMP36]], align 8 1504 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1505 // CHECK1-NEXT: store ptr @.offload_maptypes.17, ptr [[TMP37]], align 8 1506 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1507 // CHECK1-NEXT: store ptr null, ptr [[TMP38]], align 8 1508 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1509 // CHECK1-NEXT: store ptr null, ptr [[TMP39]], align 8 1510 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1511 // CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP40]], align 8 1512 // CHECK1-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, ptr [[KERNEL_ARGS]]) 1513 // CHECK1-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 1514 // CHECK1-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1515 // CHECK1: omp_offload.failed: 1516 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]] 1517 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1518 // CHECK1: omp_offload.cont: 1519 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1520 // CHECK1: omp_if.else: 1521 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]] 1522 // CHECK1-NEXT: br label [[OMP_IF_END]] 1523 // CHECK1: omp_if.end: 1524 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[A]], align 4 1525 // CHECK1-NEXT: ret i32 [[TMP43]] 1526 // 1527 // 1528 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1529 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1530 // CHECK1-NEXT: entry: 1531 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1532 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1533 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1534 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1535 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1536 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1537 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8 1538 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8 1539 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8 1540 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1541 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 1542 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 1543 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2 1544 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 1545 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 1546 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 1547 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 1548 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 1549 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1550 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 1551 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1552 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1553 // CHECK1: omp_if.then: 1554 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1555 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8 1556 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1557 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8 1558 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1559 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8 1560 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1561 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8 1562 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1563 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 8 1564 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1565 // CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8 1566 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1567 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 1568 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1569 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP12]], align 8 1570 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1571 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8 1572 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1573 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1574 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1575 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 1576 // CHECK1-NEXT: store i32 1, ptr [[TMP16]], align 4 1577 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 1578 // CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4 1579 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 1580 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8 1581 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 1582 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8 1583 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 1584 // CHECK1-NEXT: store ptr @.offload_sizes.19, ptr [[TMP20]], align 8 1585 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 1586 // CHECK1-NEXT: store ptr @.offload_maptypes.20, ptr [[TMP21]], align 8 1587 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 1588 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 1589 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 1590 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 1591 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 1592 // CHECK1-NEXT: store i64 10, ptr [[TMP24]], align 8 1593 // CHECK1-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, ptr [[KERNEL_ARGS]]) 1594 // CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 1595 // CHECK1-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1596 // CHECK1: omp_offload.failed: 1597 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] 1598 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1599 // CHECK1: omp_offload.cont: 1600 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1601 // CHECK1: omp_if.else: 1602 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]] 1603 // CHECK1-NEXT: br label [[OMP_IF_END]] 1604 // CHECK1: omp_if.end: 1605 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4 1606 // CHECK1-NEXT: ret i32 [[TMP27]] 1607 // 1608 // 1609 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 1610 // CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1611 // CHECK1-NEXT: entry: 1612 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1613 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1614 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1615 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1616 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1617 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1618 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1619 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 1620 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1621 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1622 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1623 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1624 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1625 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1626 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1627 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 1628 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 1629 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 1630 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..12, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) 1631 // CHECK1-NEXT: ret void 1632 // 1633 // 1634 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 1635 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1636 // CHECK1-NEXT: entry: 1637 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1638 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1639 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 1640 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1641 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1642 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1643 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 1644 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1645 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1646 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1647 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1648 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1649 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1650 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1651 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1652 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1653 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 1654 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 1655 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 1656 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 1657 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 1658 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 1659 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 1660 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 1661 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 1662 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1663 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 1664 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1665 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1666 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1667 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 1668 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1669 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1670 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 1671 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1672 // CHECK1: cond.true: 1673 // CHECK1-NEXT: br label [[COND_END:%.*]] 1674 // CHECK1: cond.false: 1675 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1676 // CHECK1-NEXT: br label [[COND_END]] 1677 // CHECK1: cond.end: 1678 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1679 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1680 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1681 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 1682 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1683 // CHECK1: omp.inner.for.cond: 1684 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1685 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1686 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1687 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1688 // CHECK1: omp.inner.for.body: 1689 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1690 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 1691 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1692 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1693 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4 1694 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 1695 // CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 1696 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 1697 // CHECK1-NEXT: store double [[ADD4]], ptr [[A]], align 8 1698 // CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 1699 // CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 8 1700 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 1701 // CHECK1-NEXT: store double [[INC]], ptr [[A5]], align 8 1702 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 1703 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 1704 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]] 1705 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 1706 // CHECK1-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2 1707 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1708 // CHECK1: omp.body.continue: 1709 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1710 // CHECK1: omp.inner.for.inc: 1711 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1712 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 1713 // CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4 1714 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1715 // CHECK1: omp.inner.for.end: 1716 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1717 // CHECK1: omp.loop.exit: 1718 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 1719 // CHECK1-NEXT: ret void 1720 // 1721 // 1722 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 1723 // CHECK1-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1724 // CHECK1-NEXT: entry: 1725 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1726 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1727 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1728 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1729 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1730 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1731 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1732 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1733 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1734 // CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 1735 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1736 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1737 // CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 1738 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1739 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1740 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 1741 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4 1742 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8 1743 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 1744 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 1745 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 1746 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1747 // CHECK1-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2 1748 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1749 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 1750 // CHECK1-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1 1751 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 1752 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..15, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]]) 1753 // CHECK1-NEXT: ret void 1754 // 1755 // 1756 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..15 1757 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1758 // CHECK1-NEXT: entry: 1759 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1760 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1761 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1762 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1763 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1764 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1765 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1766 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1767 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1768 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1769 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1770 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1771 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1772 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1773 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1774 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1775 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1776 // CHECK1-NEXT: [[I5:%.*]] = alloca i32, align 4 1777 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1778 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1779 // CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 1780 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1781 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1782 // CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 1783 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1784 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1785 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 1786 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 1787 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 1788 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 1789 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 1790 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1791 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 1792 // CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 1793 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 1794 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1795 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 1796 // CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4 1797 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1798 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[I]], align 4 1799 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1800 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 1801 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 1802 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1803 // CHECK1: omp.precond.then: 1804 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1805 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 1806 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4 1807 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1808 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1809 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1810 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 1811 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1812 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1813 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 1814 // CHECK1-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 1815 // CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1816 // CHECK1: cond.true: 1817 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 1818 // CHECK1-NEXT: br label [[COND_END:%.*]] 1819 // CHECK1: cond.false: 1820 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1821 // CHECK1-NEXT: br label [[COND_END]] 1822 // CHECK1: cond.end: 1823 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 1824 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1825 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1826 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 1827 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1828 // CHECK1: omp.inner.for.cond: 1829 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1830 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1831 // CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1 1832 // CHECK1-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]] 1833 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1834 // CHECK1: omp.inner.for.body: 1835 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 1836 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1837 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 1838 // CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]] 1839 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4 1840 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4 1841 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 1842 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4 1843 // CHECK1-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1844 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32 1845 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1 1846 // CHECK1-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16 1847 // CHECK1-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2 1848 // CHECK1-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 1849 // CHECK1-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32 1850 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 1851 // CHECK1-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 1852 // CHECK1-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1 1853 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 1854 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 1855 // CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 1856 // CHECK1-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4 1857 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1858 // CHECK1: omp.body.continue: 1859 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1860 // CHECK1: omp.inner.for.inc: 1861 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1862 // CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1 1863 // CHECK1-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4 1864 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1865 // CHECK1: omp.inner.for.end: 1866 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1867 // CHECK1: omp.loop.exit: 1868 // CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1869 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 1870 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]]) 1871 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 1872 // CHECK1: omp.precond.end: 1873 // CHECK1-NEXT: ret void 1874 // 1875 // 1876 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 1877 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1878 // CHECK1-NEXT: entry: 1879 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1880 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1881 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1882 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1883 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1884 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1885 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1886 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1887 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1888 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 1889 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 1890 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 1891 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1892 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 1893 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 1894 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..18, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 1895 // CHECK1-NEXT: ret void 1896 // 1897 // 1898 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..18 1899 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1900 // CHECK1-NEXT: entry: 1901 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 1902 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 1903 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1904 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1905 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 1906 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1907 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1908 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1909 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1910 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1911 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1912 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1913 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 1914 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 1915 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 1916 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 1917 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 1918 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 1919 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 1920 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 1921 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 1922 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 1923 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 1924 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 1925 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 1926 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1927 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 1928 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1929 // CHECK1: cond.true: 1930 // CHECK1-NEXT: br label [[COND_END:%.*]] 1931 // CHECK1: cond.false: 1932 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1933 // CHECK1-NEXT: br label [[COND_END]] 1934 // CHECK1: cond.end: 1935 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1936 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 1937 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 1938 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 1939 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1940 // CHECK1: omp.inner.for.cond: 1941 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1942 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 1943 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 1944 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1945 // CHECK1: omp.inner.for.body: 1946 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1947 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 1948 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 1949 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 1950 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4 1951 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 1952 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4 1953 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2 1954 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 1955 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 1956 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1957 // CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 1958 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 1959 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 1960 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 1961 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 1962 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1963 // CHECK1: omp.body.continue: 1964 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1965 // CHECK1: omp.inner.for.inc: 1966 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 1967 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 1968 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 1969 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1970 // CHECK1: omp.inner.for.end: 1971 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1972 // CHECK1: omp.loop.exit: 1973 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 1974 // CHECK1-NEXT: ret void 1975 // 1976 // 1977 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1978 // CHECK1-SAME: () #[[ATTR4]] { 1979 // CHECK1-NEXT: entry: 1980 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1981 // CHECK1-NEXT: ret void 1982 // 1983 // 1984 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 1985 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1986 // CHECK3-NEXT: entry: 1987 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1988 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1989 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1990 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1991 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 1992 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1993 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1994 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1995 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 1996 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1997 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1998 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1999 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2000 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 2001 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 2002 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 2003 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 2004 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 2005 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2006 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 2007 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 4 2008 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 4 2009 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 4 2010 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2011 // CHECK3-NEXT: [[A_CASTED8:%.*]] = alloca i32, align 4 2012 // CHECK3-NEXT: [[AA_CASTED9:%.*]] = alloca i32, align 4 2013 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 4 2014 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 4 2015 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 4 2016 // CHECK3-NEXT: [[_TMP13:%.*]] = alloca i32, align 4 2017 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 2018 // CHECK3-NEXT: [[A_CASTED18:%.*]] = alloca i32, align 4 2019 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED19:%.*]] = alloca i32, align 4 2020 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [10 x ptr], align 4 2021 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [10 x ptr], align 4 2022 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [10 x ptr], align 4 2023 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 2024 // CHECK3-NEXT: [[_TMP25:%.*]] = alloca i32, align 4 2025 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 2026 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2027 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 2028 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 2029 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 2030 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 2031 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 2032 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 2033 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 2034 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4 2035 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 2036 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 2037 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4 2038 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 2039 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 2040 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4 2041 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_2]], align 4 2042 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2 2043 // CHECK3-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2 2044 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2045 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2046 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2047 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2048 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 2049 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4 2050 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4 2051 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2052 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[TMP13]], align 4 2053 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2054 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[TMP14]], align 4 2055 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2056 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 2057 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2058 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP16]], align 4 2059 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2060 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP17]], align 4 2061 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2062 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 2063 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2064 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[TMP19]], align 4 2065 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2066 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[TMP20]], align 4 2067 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2068 // CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 2069 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2070 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2071 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 2072 // CHECK3-NEXT: [[TMP25:%.*]] = load i16, ptr [[AA]], align 2 2073 // CHECK3-NEXT: store i16 [[TMP25]], ptr [[TMP24]], align 4 2074 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 2075 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 2076 // CHECK3-NEXT: store i32 [[TMP27]], ptr [[TMP26]], align 4 2077 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2 2078 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 2079 // CHECK3-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4 2080 // CHECK3-NEXT: [[TMP30:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1) 2081 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP30]], i32 0, i32 0 2082 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP31]], i32 0, i32 0 2083 // CHECK3-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP32]], align 4 2084 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP33]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false) 2085 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP30]], i32 0, i32 1 2086 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP34]], i32 0, i32 0 2087 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP35]], ptr align 4 @.offload_sizes, i32 24, i1 false) 2088 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 1 2089 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP36]], ptr align 4 [[TMP22]], i32 12, i1 false) 2090 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 2 2091 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP37]], ptr align 4 [[TMP23]], i32 12, i1 false) 2092 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 3 2093 // CHECK3-NEXT: [[TMP39:%.*]] = load i16, ptr [[AA]], align 2 2094 // CHECK3-NEXT: store i16 [[TMP39]], ptr [[TMP38]], align 4 2095 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP30]]) 2096 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4 2097 // CHECK3-NEXT: store i32 [[TMP41]], ptr [[A_CASTED]], align 4 2098 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[A_CASTED]], align 4 2099 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP42]]) #[[ATTR3:[0-9]+]] 2100 // CHECK3-NEXT: [[TMP43:%.*]] = load i16, ptr [[AA]], align 2 2101 // CHECK3-NEXT: store i16 [[TMP43]], ptr [[AA_CASTED4]], align 2 2102 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, ptr [[AA_CASTED4]], align 4 2103 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2104 // CHECK3-NEXT: store i32 [[TMP44]], ptr [[TMP45]], align 4 2105 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2106 // CHECK3-NEXT: store i32 [[TMP44]], ptr [[TMP46]], align 4 2107 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 2108 // CHECK3-NEXT: store ptr null, ptr [[TMP47]], align 4 2109 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2110 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2111 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2112 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 2113 // CHECK3-NEXT: store i32 1, ptr [[TMP50]], align 4 2114 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 2115 // CHECK3-NEXT: store i32 1, ptr [[TMP51]], align 4 2116 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 2117 // CHECK3-NEXT: store ptr [[TMP48]], ptr [[TMP52]], align 4 2118 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 2119 // CHECK3-NEXT: store ptr [[TMP49]], ptr [[TMP53]], align 4 2120 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 2121 // CHECK3-NEXT: store ptr @.offload_sizes.4, ptr [[TMP54]], align 4 2122 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 2123 // CHECK3-NEXT: store ptr @.offload_maptypes.5, ptr [[TMP55]], align 4 2124 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 2125 // CHECK3-NEXT: store ptr null, ptr [[TMP56]], align 4 2126 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 2127 // CHECK3-NEXT: store ptr null, ptr [[TMP57]], align 4 2128 // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 2129 // CHECK3-NEXT: store i64 10, ptr [[TMP58]], align 8 2130 // CHECK3-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, ptr [[KERNEL_ARGS]]) 2131 // CHECK3-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 2132 // CHECK3-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2133 // CHECK3: omp_offload.failed: 2134 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP44]]) #[[ATTR3]] 2135 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2136 // CHECK3: omp_offload.cont: 2137 // CHECK3-NEXT: [[TMP61:%.*]] = load i32, ptr [[A]], align 4 2138 // CHECK3-NEXT: store i32 [[TMP61]], ptr [[A_CASTED8]], align 4 2139 // CHECK3-NEXT: [[TMP62:%.*]] = load i32, ptr [[A_CASTED8]], align 4 2140 // CHECK3-NEXT: [[TMP63:%.*]] = load i16, ptr [[AA]], align 2 2141 // CHECK3-NEXT: store i16 [[TMP63]], ptr [[AA_CASTED9]], align 2 2142 // CHECK3-NEXT: [[TMP64:%.*]] = load i32, ptr [[AA_CASTED9]], align 4 2143 // CHECK3-NEXT: [[TMP65:%.*]] = load i32, ptr [[N_ADDR]], align 4 2144 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP65]], 10 2145 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2146 // CHECK3: omp_if.then: 2147 // CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 2148 // CHECK3-NEXT: store i32 [[TMP62]], ptr [[TMP66]], align 4 2149 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 2150 // CHECK3-NEXT: store i32 [[TMP62]], ptr [[TMP67]], align 4 2151 // CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 0 2152 // CHECK3-NEXT: store ptr null, ptr [[TMP68]], align 4 2153 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 2154 // CHECK3-NEXT: store i32 [[TMP64]], ptr [[TMP69]], align 4 2155 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 2156 // CHECK3-NEXT: store i32 [[TMP64]], ptr [[TMP70]], align 4 2157 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 1 2158 // CHECK3-NEXT: store ptr null, ptr [[TMP71]], align 4 2159 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 2160 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 2161 // CHECK3-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2162 // CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0 2163 // CHECK3-NEXT: store i32 1, ptr [[TMP74]], align 4 2164 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1 2165 // CHECK3-NEXT: store i32 2, ptr [[TMP75]], align 4 2166 // CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2 2167 // CHECK3-NEXT: store ptr [[TMP72]], ptr [[TMP76]], align 4 2168 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3 2169 // CHECK3-NEXT: store ptr [[TMP73]], ptr [[TMP77]], align 4 2170 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4 2171 // CHECK3-NEXT: store ptr @.offload_sizes.7, ptr [[TMP78]], align 4 2172 // CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5 2173 // CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP79]], align 4 2174 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6 2175 // CHECK3-NEXT: store ptr null, ptr [[TMP80]], align 4 2176 // CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7 2177 // CHECK3-NEXT: store ptr null, ptr [[TMP81]], align 4 2178 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8 2179 // CHECK3-NEXT: store i64 10, ptr [[TMP82]], align 8 2180 // CHECK3-NEXT: [[TMP83:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, ptr [[KERNEL_ARGS14]]) 2181 // CHECK3-NEXT: [[TMP84:%.*]] = icmp ne i32 [[TMP83]], 0 2182 // CHECK3-NEXT: br i1 [[TMP84]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] 2183 // CHECK3: omp_offload.failed15: 2184 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP62]], i32 [[TMP64]]) #[[ATTR3]] 2185 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT16]] 2186 // CHECK3: omp_offload.cont16: 2187 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2188 // CHECK3: omp_if.else: 2189 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP62]], i32 [[TMP64]]) #[[ATTR3]] 2190 // CHECK3-NEXT: br label [[OMP_IF_END]] 2191 // CHECK3: omp_if.end: 2192 // CHECK3-NEXT: [[TMP85:%.*]] = load i32, ptr [[N_ADDR]], align 4 2193 // CHECK3-NEXT: store i32 [[TMP85]], ptr [[DOTCAPTURE_EXPR_17]], align 4 2194 // CHECK3-NEXT: [[TMP86:%.*]] = load i32, ptr [[A]], align 4 2195 // CHECK3-NEXT: store i32 [[TMP86]], ptr [[A_CASTED18]], align 4 2196 // CHECK3-NEXT: [[TMP87:%.*]] = load i32, ptr [[A_CASTED18]], align 4 2197 // CHECK3-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 2198 // CHECK3-NEXT: store i32 [[TMP88]], ptr [[DOTCAPTURE_EXPR__CASTED19]], align 4 2199 // CHECK3-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED19]], align 4 2200 // CHECK3-NEXT: [[TMP90:%.*]] = load i32, ptr [[N_ADDR]], align 4 2201 // CHECK3-NEXT: [[CMP20:%.*]] = icmp sgt i32 [[TMP90]], 20 2202 // CHECK3-NEXT: br i1 [[CMP20]], label [[OMP_IF_THEN21:%.*]], label [[OMP_IF_ELSE29:%.*]] 2203 // CHECK3: omp_if.then21: 2204 // CHECK3-NEXT: [[TMP91:%.*]] = mul nuw i32 [[TMP1]], 4 2205 // CHECK3-NEXT: [[TMP92:%.*]] = sext i32 [[TMP91]] to i64 2206 // CHECK3-NEXT: [[TMP93:%.*]] = mul nuw i32 5, [[TMP3]] 2207 // CHECK3-NEXT: [[TMP94:%.*]] = mul nuw i32 [[TMP93]], 8 2208 // CHECK3-NEXT: [[TMP95:%.*]] = sext i32 [[TMP94]] to i64 2209 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.10, i32 80, i1 false) 2210 // CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 2211 // CHECK3-NEXT: store i32 [[TMP87]], ptr [[TMP96]], align 4 2212 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 2213 // CHECK3-NEXT: store i32 [[TMP87]], ptr [[TMP97]], align 4 2214 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 0 2215 // CHECK3-NEXT: store ptr null, ptr [[TMP98]], align 4 2216 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1 2217 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP99]], align 4 2218 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 1 2219 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP100]], align 4 2220 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 1 2221 // CHECK3-NEXT: store ptr null, ptr [[TMP101]], align 4 2222 // CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2 2223 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP102]], align 4 2224 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 2 2225 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP103]], align 4 2226 // CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 2 2227 // CHECK3-NEXT: store ptr null, ptr [[TMP104]], align 4 2228 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3 2229 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP105]], align 4 2230 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 3 2231 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP106]], align 4 2232 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2233 // CHECK3-NEXT: store i64 [[TMP92]], ptr [[TMP107]], align 4 2234 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 3 2235 // CHECK3-NEXT: store ptr null, ptr [[TMP108]], align 4 2236 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 4 2237 // CHECK3-NEXT: store ptr [[C]], ptr [[TMP109]], align 4 2238 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 4 2239 // CHECK3-NEXT: store ptr [[C]], ptr [[TMP110]], align 4 2240 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 4 2241 // CHECK3-NEXT: store ptr null, ptr [[TMP111]], align 4 2242 // CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 5 2243 // CHECK3-NEXT: store i32 5, ptr [[TMP112]], align 4 2244 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 5 2245 // CHECK3-NEXT: store i32 5, ptr [[TMP113]], align 4 2246 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 5 2247 // CHECK3-NEXT: store ptr null, ptr [[TMP114]], align 4 2248 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 6 2249 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP115]], align 4 2250 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 6 2251 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP116]], align 4 2252 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 6 2253 // CHECK3-NEXT: store ptr null, ptr [[TMP117]], align 4 2254 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 7 2255 // CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP118]], align 4 2256 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 7 2257 // CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP119]], align 4 2258 // CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2259 // CHECK3-NEXT: store i64 [[TMP95]], ptr [[TMP120]], align 4 2260 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 7 2261 // CHECK3-NEXT: store ptr null, ptr [[TMP121]], align 4 2262 // CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 8 2263 // CHECK3-NEXT: store ptr [[D]], ptr [[TMP122]], align 4 2264 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 8 2265 // CHECK3-NEXT: store ptr [[D]], ptr [[TMP123]], align 4 2266 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 8 2267 // CHECK3-NEXT: store ptr null, ptr [[TMP124]], align 4 2268 // CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 9 2269 // CHECK3-NEXT: store i32 [[TMP89]], ptr [[TMP125]], align 4 2270 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 9 2271 // CHECK3-NEXT: store i32 [[TMP89]], ptr [[TMP126]], align 4 2272 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 9 2273 // CHECK3-NEXT: store ptr null, ptr [[TMP127]], align 4 2274 // CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0 2275 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 0 2276 // CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2277 // CHECK3-NEXT: [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2278 // CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 0 2279 // CHECK3-NEXT: store i32 1, ptr [[TMP131]], align 4 2280 // CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 1 2281 // CHECK3-NEXT: store i32 10, ptr [[TMP132]], align 4 2282 // CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 2 2283 // CHECK3-NEXT: store ptr [[TMP128]], ptr [[TMP133]], align 4 2284 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 3 2285 // CHECK3-NEXT: store ptr [[TMP129]], ptr [[TMP134]], align 4 2286 // CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 4 2287 // CHECK3-NEXT: store ptr [[TMP130]], ptr [[TMP135]], align 4 2288 // CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 5 2289 // CHECK3-NEXT: store ptr @.offload_maptypes.11, ptr [[TMP136]], align 4 2290 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 6 2291 // CHECK3-NEXT: store ptr null, ptr [[TMP137]], align 4 2292 // CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 7 2293 // CHECK3-NEXT: store ptr null, ptr [[TMP138]], align 4 2294 // CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 8 2295 // CHECK3-NEXT: store i64 10, ptr [[TMP139]], align 8 2296 // CHECK3-NEXT: [[TMP140:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, ptr [[KERNEL_ARGS26]]) 2297 // CHECK3-NEXT: [[TMP141:%.*]] = icmp ne i32 [[TMP140]], 0 2298 // CHECK3-NEXT: br i1 [[TMP141]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]] 2299 // CHECK3: omp_offload.failed27: 2300 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP87]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP89]]) #[[ATTR3]] 2301 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT28]] 2302 // CHECK3: omp_offload.cont28: 2303 // CHECK3-NEXT: br label [[OMP_IF_END30:%.*]] 2304 // CHECK3: omp_if.else29: 2305 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP87]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP89]]) #[[ATTR3]] 2306 // CHECK3-NEXT: br label [[OMP_IF_END30]] 2307 // CHECK3: omp_if.end30: 2308 // CHECK3-NEXT: [[TMP142:%.*]] = load i32, ptr [[A]], align 4 2309 // CHECK3-NEXT: [[TMP143:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 2310 // CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP143]]) 2311 // CHECK3-NEXT: ret i32 [[TMP142]] 2312 // 2313 // 2314 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 2315 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 2316 // CHECK3-NEXT: entry: 2317 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2318 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2319 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 2320 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2321 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) 2322 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2323 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2324 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 2325 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2326 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 2327 // CHECK3-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 2328 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2329 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 2330 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2331 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @.omp_outlined., i32 [[TMP4]]) 2332 // CHECK3-NEXT: ret void 2333 // 2334 // 2335 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2336 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2337 // CHECK3-NEXT: entry: 2338 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2339 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2340 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2341 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2342 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2343 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2344 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2345 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2346 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2347 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2348 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2349 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2350 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2351 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2352 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 2353 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2354 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2355 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2356 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2357 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2358 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2359 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 2360 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2361 // CHECK3: cond.true: 2362 // CHECK3-NEXT: br label [[COND_END:%.*]] 2363 // CHECK3: cond.false: 2364 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2365 // CHECK3-NEXT: br label [[COND_END]] 2366 // CHECK3: cond.end: 2367 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2368 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2369 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2370 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2371 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2372 // CHECK3: omp.inner.for.cond: 2373 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2374 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2375 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2376 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2377 // CHECK3: omp.inner.for.body: 2378 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2379 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2380 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2381 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2382 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2383 // CHECK3: omp.body.continue: 2384 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2385 // CHECK3: omp.inner.for.inc: 2386 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2387 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2388 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 2389 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2390 // CHECK3: omp.inner.for.end: 2391 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2392 // CHECK3: omp.loop.exit: 2393 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2394 // CHECK3-NEXT: ret void 2395 // 2396 // 2397 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. 2398 // CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 2399 // CHECK3-NEXT: entry: 2400 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 2401 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 2402 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 4 2403 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 4 2404 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 4 2405 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 2406 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 2407 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 4 2408 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 4 2409 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 4 2410 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 4 2411 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0 2412 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 4 2413 // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 4 2414 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1 2415 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 4 2416 // CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 4 2417 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2 2418 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 4 2419 // CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 4 2420 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3 2421 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 2422 // CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 4 2423 // CHECK3-NEXT: ret void 2424 // 2425 // 2426 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2427 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2428 // CHECK3-NEXT: entry: 2429 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2430 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4 2431 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4 2432 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4 2433 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4 2434 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4 2435 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4 2436 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4 2437 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4 2438 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4 2439 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 2440 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 2441 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 2442 // CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2443 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2444 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 2445 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 2446 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 2447 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 2448 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 2449 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 2450 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 2451 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 2452 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 2453 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 2454 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) 2455 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 2456 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 2457 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 2458 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 2459 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 2460 // CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 2461 // CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 2462 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 2463 // CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !22 2464 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !22 2465 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 2466 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 2467 // CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 2468 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !22 2469 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !22 2470 // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !22 2471 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !22 2472 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1 2473 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2 2474 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 2475 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP17]], align 4 2476 // CHECK3-NEXT: store i32 1, ptr [[KERNEL_ARGS_I]], align 4, !noalias !22 2477 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1 2478 // CHECK3-NEXT: store i32 3, ptr [[TMP20]], align 4, !noalias !22 2479 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2 2480 // CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP21]], align 4, !noalias !22 2481 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3 2482 // CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP22]], align 4, !noalias !22 2483 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4 2484 // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP23]], align 4, !noalias !22 2485 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5 2486 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP24]], align 4, !noalias !22 2487 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6 2488 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4, !noalias !22 2489 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7 2490 // CHECK3-NEXT: store ptr null, ptr [[TMP26]], align 4, !noalias !22 2491 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8 2492 // CHECK3-NEXT: store i64 10, ptr [[TMP27]], align 8, !noalias !22 2493 // CHECK3-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_kernel_nowait(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 [[TMP19]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS_I]], i32 0, ptr null, i32 0, ptr null) 2494 // CHECK3-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 2495 // CHECK3-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 2496 // CHECK3: omp_offload.failed.i: 2497 // CHECK3-NEXT: [[TMP30:%.*]] = load i16, ptr [[TMP12]], align 2 2498 // CHECK3-NEXT: store i16 [[TMP30]], ptr [[AA_CASTED_I]], align 2, !noalias !22 2499 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !22 2500 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP16]], align 4 2501 // CHECK3-NEXT: store i32 [[TMP32]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22 2502 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22 2503 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP17]], align 4 2504 // CHECK3-NEXT: store i32 [[TMP34]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22 2505 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22 2506 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP31]], i32 [[TMP33]], i32 [[TMP35]]) #[[ATTR3]] 2507 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 2508 // CHECK3: .omp_outlined..1.exit: 2509 // CHECK3-NEXT: ret i32 0 2510 // 2511 // 2512 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107 2513 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { 2514 // CHECK3-NEXT: entry: 2515 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2516 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2517 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2518 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2519 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 2520 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 2521 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @.omp_outlined..2, i32 [[TMP1]]) 2522 // CHECK3-NEXT: ret void 2523 // 2524 // 2525 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2526 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 2527 // CHECK3-NEXT: entry: 2528 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2529 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2530 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2531 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2532 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2533 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2534 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2535 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2536 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2537 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2538 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2539 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2540 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2541 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2542 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 2543 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2544 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2545 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2546 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2547 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2548 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2549 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 2550 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2551 // CHECK3: cond.true: 2552 // CHECK3-NEXT: br label [[COND_END:%.*]] 2553 // CHECK3: cond.false: 2554 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2555 // CHECK3-NEXT: br label [[COND_END]] 2556 // CHECK3: cond.end: 2557 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2558 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2559 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2560 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2561 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2562 // CHECK3: omp.inner.for.cond: 2563 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2564 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2565 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2566 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2567 // CHECK3: omp.inner.for.body: 2568 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2569 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2570 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2571 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2572 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 2573 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2574 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4 2575 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2576 // CHECK3: omp.body.continue: 2577 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2578 // CHECK3: omp.inner.for.inc: 2579 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2580 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 2581 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 2582 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2583 // CHECK3: omp.inner.for.end: 2584 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2585 // CHECK3: omp.loop.exit: 2586 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2587 // CHECK3-NEXT: ret void 2588 // 2589 // 2590 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 2591 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2592 // CHECK3-NEXT: entry: 2593 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2594 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2595 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2596 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2597 // CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 2598 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2599 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @.omp_outlined..3, i32 [[TMP1]]) 2600 // CHECK3-NEXT: ret void 2601 // 2602 // 2603 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2604 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2605 // CHECK3-NEXT: entry: 2606 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2607 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2608 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2609 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2610 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2611 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2612 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2613 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2614 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2615 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2616 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2617 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2618 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2619 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2620 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 2621 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2622 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2623 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2624 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2625 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2626 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2627 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 2628 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2629 // CHECK3: cond.true: 2630 // CHECK3-NEXT: br label [[COND_END:%.*]] 2631 // CHECK3: cond.false: 2632 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2633 // CHECK3-NEXT: br label [[COND_END]] 2634 // CHECK3: cond.end: 2635 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2636 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2637 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2638 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2639 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2640 // CHECK3: omp.inner.for.cond: 2641 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2642 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2643 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2644 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2645 // CHECK3: omp.inner.for.body: 2646 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2647 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2648 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2649 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2650 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2651 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 2652 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 2653 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 2654 // CHECK3-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2 2655 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2656 // CHECK3: omp.body.continue: 2657 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2658 // CHECK3: omp.inner.for.inc: 2659 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2660 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 2661 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 2662 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2663 // CHECK3: omp.inner.for.end: 2664 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2665 // CHECK3: omp.loop.exit: 2666 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2667 // CHECK3-NEXT: ret void 2668 // 2669 // 2670 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 2671 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2672 // CHECK3-NEXT: entry: 2673 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2674 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2675 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2676 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2677 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2678 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2679 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 2680 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 2681 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 2682 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2683 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 2684 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 2685 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..6, i32 [[TMP1]], i32 [[TMP3]]) 2686 // CHECK3-NEXT: ret void 2687 // 2688 // 2689 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 2690 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2691 // CHECK3-NEXT: entry: 2692 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2693 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2694 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2695 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2696 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2697 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2698 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2699 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2700 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2701 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2702 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2703 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2704 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2705 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2706 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 2707 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2708 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 2709 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2710 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2711 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2712 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 2713 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 2714 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2715 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 2716 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2717 // CHECK3: cond.true: 2718 // CHECK3-NEXT: br label [[COND_END:%.*]] 2719 // CHECK3: cond.false: 2720 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2721 // CHECK3-NEXT: br label [[COND_END]] 2722 // CHECK3: cond.end: 2723 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2724 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2725 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2726 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 2727 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2728 // CHECK3: omp.inner.for.cond: 2729 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2730 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2731 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2732 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2733 // CHECK3: omp.inner.for.body: 2734 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2735 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 2736 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2737 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 2738 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 2739 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2740 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4 2741 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2 2742 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 2743 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 2744 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2745 // CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 2746 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2747 // CHECK3: omp.body.continue: 2748 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2749 // CHECK3: omp.inner.for.inc: 2750 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2751 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 2752 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 2753 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2754 // CHECK3: omp.inner.for.end: 2755 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2756 // CHECK3: omp.loop.exit: 2757 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 2758 // CHECK3-NEXT: ret void 2759 // 2760 // 2761 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 2762 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2763 // CHECK3-NEXT: entry: 2764 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2765 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 2766 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2767 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 2768 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 2769 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2770 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2771 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 2772 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 2773 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2774 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2775 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2776 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2777 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 2778 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2779 // CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 2780 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 2781 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 2782 // CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 2783 // CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 2784 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 2785 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2786 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 2787 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2788 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 2789 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 2790 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 2791 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 2792 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 2793 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 2794 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 2795 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 2796 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 2797 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2798 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2799 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 2800 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..9, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 2801 // CHECK3-NEXT: ret void 2802 // 2803 // 2804 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 2805 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2806 // CHECK3-NEXT: entry: 2807 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 2808 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 2809 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2810 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 2811 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2812 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 2813 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 2814 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2815 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2816 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 2817 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 2818 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2819 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2820 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2821 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2822 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2823 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2824 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2825 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2826 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 2827 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 2828 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 2829 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 2830 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 2831 // CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 2832 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 2833 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 2834 // CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 2835 // CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 2836 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 2837 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2838 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 2839 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 2840 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 2841 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 2842 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 2843 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 2844 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 2845 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 2846 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 2847 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 2848 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 2849 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 2850 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 2851 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 2852 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 2853 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 2854 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2855 // CHECK3: omp.dispatch.cond: 2856 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2857 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 2858 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2859 // CHECK3: cond.true: 2860 // CHECK3-NEXT: br label [[COND_END:%.*]] 2861 // CHECK3: cond.false: 2862 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2863 // CHECK3-NEXT: br label [[COND_END]] 2864 // CHECK3: cond.end: 2865 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2866 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 2867 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2868 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 2869 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 2870 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2871 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2872 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2873 // CHECK3: omp.dispatch.body: 2874 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2875 // CHECK3: omp.inner.for.cond: 2876 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] 2877 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] 2878 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 2879 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2880 // CHECK3: omp.inner.for.body: 2881 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 2882 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 2883 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 2884 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] 2885 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 2886 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 2887 // CHECK3-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] 2888 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 2889 // CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 2890 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double 2891 // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 2892 // CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 2893 // CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 2894 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 2895 // CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 2896 // CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 2897 // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 2898 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 2899 // CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] 2900 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 2901 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 2902 // CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 2903 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 2904 // CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] 2905 // CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 2906 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 2907 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 2908 // CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 2909 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 2910 // CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]] 2911 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 2912 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP23]] 2913 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 2914 // CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP23]] 2915 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 2916 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP23]] 2917 // CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 2918 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 2919 // CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 2920 // CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP23]] 2921 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2922 // CHECK3: omp.body.continue: 2923 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2924 // CHECK3: omp.inner.for.inc: 2925 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 2926 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 2927 // CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 2928 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 2929 // CHECK3: omp.inner.for.end: 2930 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2931 // CHECK3: omp.dispatch.inc: 2932 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 2933 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2934 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 2935 // CHECK3-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 2936 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 2937 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 2938 // CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 2939 // CHECK3-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 2940 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2941 // CHECK3: omp.dispatch.end: 2942 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 2943 // CHECK3-NEXT: ret void 2944 // 2945 // 2946 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2947 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2948 // CHECK3-NEXT: entry: 2949 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2950 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2951 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2952 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2953 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 2954 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2955 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 2956 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4 2957 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2958 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 4 2959 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 2960 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 2961 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4 2962 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2963 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 4 2964 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 2965 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 2966 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 2967 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2968 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 4 2969 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 2970 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 2971 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4 2972 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2973 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 4 2974 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4 2975 // CHECK3-NEXT: ret i32 [[TMP8]] 2976 // 2977 // 2978 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2979 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2980 // CHECK3-NEXT: entry: 2981 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 2982 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2983 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 2984 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4 2985 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2986 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2987 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 2988 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 2989 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 2990 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2991 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2992 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 2993 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 2994 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 2995 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 2996 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2997 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4 2998 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 2999 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave() 3000 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4 3001 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 3002 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 3003 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4 3004 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4 3005 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 3006 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 3007 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4 3008 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 3009 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3010 // CHECK3: omp_if.then: 3011 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0 3012 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 3013 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 3014 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 3015 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.13, i32 40, i1 false) 3016 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3017 // CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 4 3018 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3019 // CHECK3-NEXT: store ptr [[A]], ptr [[TMP11]], align 4 3020 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3021 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4 3022 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3023 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4 3024 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3025 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4 3026 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3027 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4 3028 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3029 // CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 4 3030 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3031 // CHECK3-NEXT: store i32 2, ptr [[TMP17]], align 4 3032 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3033 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4 3034 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3035 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 4 3036 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3037 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 4 3038 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3039 // CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4 3040 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3041 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 4 3042 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3043 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 4 3044 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3045 // CHECK3-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 4 3046 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3047 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4 3048 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3049 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3050 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3051 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3052 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3053 // CHECK3-NEXT: store i32 1, ptr [[TMP29]], align 4 3054 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3055 // CHECK3-NEXT: store i32 5, ptr [[TMP30]], align 4 3056 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3057 // CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 4 3058 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3059 // CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 4 3060 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3061 // CHECK3-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 4 3062 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3063 // CHECK3-NEXT: store ptr @.offload_maptypes.14, ptr [[TMP34]], align 4 3064 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3065 // CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 4 3066 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3067 // CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 4 3068 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3069 // CHECK3-NEXT: store i64 10, ptr [[TMP37]], align 8 3070 // CHECK3-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, ptr [[KERNEL_ARGS]]) 3071 // CHECK3-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 3072 // CHECK3-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3073 // CHECK3: omp_offload.failed: 3074 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] 3075 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3076 // CHECK3: omp_offload.cont: 3077 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3078 // CHECK3: omp_if.else: 3079 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]] 3080 // CHECK3-NEXT: br label [[OMP_IF_END]] 3081 // CHECK3: omp_if.end: 3082 // CHECK3-NEXT: [[TMP40:%.*]] = mul nsw i32 1, [[TMP1]] 3083 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP40]] 3084 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 3085 // CHECK3-NEXT: [[TMP41:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2 3086 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP41]] to i32 3087 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[B]], align 4 3088 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP42]] 3089 // CHECK3-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4 3090 // CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP43]]) 3091 // CHECK3-NEXT: ret i32 [[ADD3]] 3092 // 3093 // 3094 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 3095 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3096 // CHECK3-NEXT: entry: 3097 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3098 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3099 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3100 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 3101 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3102 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 3103 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3104 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3105 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3106 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4 3107 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4 3108 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4 3109 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3110 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3111 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3112 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3113 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3114 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 3115 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 3116 // CHECK3-NEXT: store i8 0, ptr [[AAA]], align 1 3117 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4 3118 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[N_CASTED]], align 4 3119 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_CASTED]], align 4 3120 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 3121 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[A_CASTED]], align 4 3122 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 4 3123 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, ptr [[AA]], align 2 3124 // CHECK3-NEXT: store i16 [[TMP4]], ptr [[AA_CASTED]], align 2 3125 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3126 // CHECK3-NEXT: [[TMP6:%.*]] = load i8, ptr [[AAA]], align 1 3127 // CHECK3-NEXT: store i8 [[TMP6]], ptr [[AAA_CASTED]], align 1 3128 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 3129 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 4 3130 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50 3131 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3132 // CHECK3: omp_if.then: 3133 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3134 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP9]], align 4 3135 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3136 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP10]], align 4 3137 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3138 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4 3139 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3140 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP12]], align 4 3141 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3142 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP13]], align 4 3143 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3144 // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4 3145 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3146 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP15]], align 4 3147 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3148 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP16]], align 4 3149 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3150 // CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 4 3151 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3152 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[TMP18]], align 4 3153 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3154 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[TMP19]], align 4 3155 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3156 // CHECK3-NEXT: store ptr null, ptr [[TMP20]], align 4 3157 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3158 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP21]], align 4 3159 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3160 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP22]], align 4 3161 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3162 // CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 3163 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3164 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3165 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 4 3166 // CHECK3-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 4 3167 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 4 3168 // CHECK3-NEXT: store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 4 3169 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 3170 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 3171 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]] 3172 // CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 3173 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 3174 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3175 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 3176 // CHECK3-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4 3177 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 3178 // CHECK3-NEXT: [[ADD5:%.*]] = add i32 [[TMP30]], 1 3179 // CHECK3-NEXT: [[TMP31:%.*]] = zext i32 [[ADD5]] to i64 3180 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3181 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3182 // CHECK3-NEXT: store i32 1, ptr [[TMP32]], align 4 3183 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3184 // CHECK3-NEXT: store i32 5, ptr [[TMP33]], align 4 3185 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3186 // CHECK3-NEXT: store ptr [[TMP24]], ptr [[TMP34]], align 4 3187 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3188 // CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP35]], align 4 3189 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3190 // CHECK3-NEXT: store ptr @.offload_sizes.16, ptr [[TMP36]], align 4 3191 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3192 // CHECK3-NEXT: store ptr @.offload_maptypes.17, ptr [[TMP37]], align 4 3193 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3194 // CHECK3-NEXT: store ptr null, ptr [[TMP38]], align 4 3195 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3196 // CHECK3-NEXT: store ptr null, ptr [[TMP39]], align 4 3197 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3198 // CHECK3-NEXT: store i64 [[TMP31]], ptr [[TMP40]], align 8 3199 // CHECK3-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, ptr [[KERNEL_ARGS]]) 3200 // CHECK3-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 3201 // CHECK3-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3202 // CHECK3: omp_offload.failed: 3203 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]] 3204 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3205 // CHECK3: omp_offload.cont: 3206 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3207 // CHECK3: omp_if.else: 3208 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]] 3209 // CHECK3-NEXT: br label [[OMP_IF_END]] 3210 // CHECK3: omp_if.end: 3211 // CHECK3-NEXT: [[TMP43:%.*]] = load i32, ptr [[A]], align 4 3212 // CHECK3-NEXT: ret i32 [[TMP43]] 3213 // 3214 // 3215 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3216 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 3217 // CHECK3-NEXT: entry: 3218 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3219 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3220 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3221 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3222 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3223 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3224 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4 3225 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4 3226 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4 3227 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3228 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3229 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4 3230 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2 3231 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 3232 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 3233 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 3234 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2 3235 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 3236 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3237 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 3238 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3239 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3240 // CHECK3: omp_if.then: 3241 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3242 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 3243 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3244 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4 3245 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3246 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4 3247 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3248 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4 3249 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3250 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 4 3251 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3252 // CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4 3253 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3254 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 4 3255 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3256 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP12]], align 4 3257 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3258 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4 3259 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3260 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3261 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3262 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 3263 // CHECK3-NEXT: store i32 1, ptr [[TMP16]], align 4 3264 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1 3265 // CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4 3266 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2 3267 // CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4 3268 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3 3269 // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4 3270 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4 3271 // CHECK3-NEXT: store ptr @.offload_sizes.19, ptr [[TMP20]], align 4 3272 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5 3273 // CHECK3-NEXT: store ptr @.offload_maptypes.20, ptr [[TMP21]], align 4 3274 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6 3275 // CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4 3276 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7 3277 // CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4 3278 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8 3279 // CHECK3-NEXT: store i64 10, ptr [[TMP24]], align 8 3280 // CHECK3-NEXT: [[TMP25:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, ptr [[KERNEL_ARGS]]) 3281 // CHECK3-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0 3282 // CHECK3-NEXT: br i1 [[TMP26]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3283 // CHECK3: omp_offload.failed: 3284 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] 3285 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3286 // CHECK3: omp_offload.cont: 3287 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3288 // CHECK3: omp_if.else: 3289 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]] 3290 // CHECK3-NEXT: br label [[OMP_IF_END]] 3291 // CHECK3: omp_if.end: 3292 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[A]], align 4 3293 // CHECK3-NEXT: ret i32 [[TMP27]] 3294 // 3295 // 3296 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 3297 // CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3298 // CHECK3-NEXT: entry: 3299 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3300 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3301 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3302 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3303 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3304 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3305 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3306 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 3307 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3308 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 3309 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3310 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3311 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3312 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 3313 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3314 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 3315 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 3316 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 3317 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..12, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) 3318 // CHECK3-NEXT: ret void 3319 // 3320 // 3321 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 3322 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3323 // CHECK3-NEXT: entry: 3324 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3325 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3326 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 3327 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3328 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3329 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3330 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 3331 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3332 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3333 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3334 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3335 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3336 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3337 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3338 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3339 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3340 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 3341 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 3342 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 3343 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 3344 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 3345 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 3346 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 3347 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 3348 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 3349 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3350 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 3351 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3352 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3353 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3354 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 3355 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3356 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3357 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 3358 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3359 // CHECK3: cond.true: 3360 // CHECK3-NEXT: br label [[COND_END:%.*]] 3361 // CHECK3: cond.false: 3362 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3363 // CHECK3-NEXT: br label [[COND_END]] 3364 // CHECK3: cond.end: 3365 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3366 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3367 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3368 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 3369 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3370 // CHECK3: omp.inner.for.cond: 3371 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3372 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3373 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3374 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3375 // CHECK3: omp.inner.for.body: 3376 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3377 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 3378 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3379 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 3380 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4 3381 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 3382 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 3383 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 3384 // CHECK3-NEXT: store double [[ADD4]], ptr [[A]], align 4 3385 // CHECK3-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 3386 // CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 4 3387 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 3388 // CHECK3-NEXT: store double [[INC]], ptr [[A5]], align 4 3389 // CHECK3-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 3390 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 3391 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]] 3392 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 3393 // CHECK3-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2 3394 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3395 // CHECK3: omp.body.continue: 3396 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3397 // CHECK3: omp.inner.for.inc: 3398 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3399 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 3400 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4 3401 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3402 // CHECK3: omp.inner.for.end: 3403 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3404 // CHECK3: omp.loop.exit: 3405 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 3406 // CHECK3-NEXT: ret void 3407 // 3408 // 3409 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 3410 // CHECK3-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3411 // CHECK3-NEXT: entry: 3412 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3413 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3414 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3415 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3416 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3417 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 3418 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3419 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3420 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3421 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3422 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3423 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3424 // CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 3425 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3426 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3427 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 3428 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4 3429 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4 3430 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 3431 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 3432 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4 3433 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3434 // CHECK3-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2 3435 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3436 // CHECK3-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 3437 // CHECK3-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1 3438 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 3439 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..15, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]]) 3440 // CHECK3-NEXT: ret void 3441 // 3442 // 3443 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..15 3444 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3445 // CHECK3-NEXT: entry: 3446 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3447 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3448 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3449 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3450 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3451 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3452 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3453 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3454 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3455 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3456 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3457 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3458 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3459 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3460 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3461 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3462 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3463 // CHECK3-NEXT: [[I5:%.*]] = alloca i32, align 4 3464 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3465 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3466 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 3467 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3468 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3469 // CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 3470 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3471 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3472 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3473 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 3474 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 3475 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 3476 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 3477 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 3478 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 3479 // CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 3480 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 3481 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3482 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 3483 // CHECK3-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4 3484 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 3485 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[I]], align 4 3486 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 3487 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 3488 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 3489 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3490 // CHECK3: omp.precond.then: 3491 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3492 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 3493 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4 3494 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3495 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3496 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3497 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 3498 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3499 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3500 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 3501 // CHECK3-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 3502 // CHECK3-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3503 // CHECK3: cond.true: 3504 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 3505 // CHECK3-NEXT: br label [[COND_END:%.*]] 3506 // CHECK3: cond.false: 3507 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3508 // CHECK3-NEXT: br label [[COND_END]] 3509 // CHECK3: cond.end: 3510 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 3511 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3512 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3513 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 3514 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3515 // CHECK3: omp.inner.for.cond: 3516 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3517 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3518 // CHECK3-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1 3519 // CHECK3-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]] 3520 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3521 // CHECK3: omp.inner.for.body: 3522 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 3523 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3524 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 3525 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]] 3526 // CHECK3-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4 3527 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4 3528 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 3529 // CHECK3-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4 3530 // CHECK3-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3531 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32 3532 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1 3533 // CHECK3-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16 3534 // CHECK3-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2 3535 // CHECK3-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 3536 // CHECK3-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32 3537 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 3538 // CHECK3-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 3539 // CHECK3-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1 3540 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 3541 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 3542 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 3543 // CHECK3-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4 3544 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3545 // CHECK3: omp.body.continue: 3546 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3547 // CHECK3: omp.inner.for.inc: 3548 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3549 // CHECK3-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1 3550 // CHECK3-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4 3551 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3552 // CHECK3: omp.inner.for.end: 3553 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3554 // CHECK3: omp.loop.exit: 3555 // CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3556 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 3557 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]]) 3558 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 3559 // CHECK3: omp.precond.end: 3560 // CHECK3-NEXT: ret void 3561 // 3562 // 3563 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 3564 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3565 // CHECK3-NEXT: entry: 3566 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3567 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3568 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3569 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3570 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3571 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3572 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3573 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3574 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3575 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 3576 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 3577 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 3578 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3579 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3580 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 3581 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..18, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 3582 // CHECK3-NEXT: ret void 3583 // 3584 // 3585 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..18 3586 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3587 // CHECK3-NEXT: entry: 3588 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 3589 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 3590 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3591 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3592 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 3593 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3594 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3595 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3596 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3597 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3598 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3599 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3600 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 3601 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 3602 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 3603 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 3604 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 3605 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 3606 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3607 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 3608 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3609 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3610 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 3611 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 3612 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3613 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3614 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 3615 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3616 // CHECK3: cond.true: 3617 // CHECK3-NEXT: br label [[COND_END:%.*]] 3618 // CHECK3: cond.false: 3619 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3620 // CHECK3-NEXT: br label [[COND_END]] 3621 // CHECK3: cond.end: 3622 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 3623 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3624 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3625 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 3626 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3627 // CHECK3: omp.inner.for.cond: 3628 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3629 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3630 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 3631 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3632 // CHECK3: omp.inner.for.body: 3633 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3634 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 3635 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3636 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 3637 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4 3638 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 3639 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4 3640 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3641 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 3642 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 3643 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3644 // CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 3645 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 3646 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 3647 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 3648 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 3649 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3650 // CHECK3: omp.body.continue: 3651 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3652 // CHECK3: omp.inner.for.inc: 3653 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3654 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 3655 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 3656 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3657 // CHECK3: omp.inner.for.end: 3658 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3659 // CHECK3: omp.loop.exit: 3660 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 3661 // CHECK3-NEXT: ret void 3662 // 3663 // 3664 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3665 // CHECK3-SAME: () #[[ATTR4]] { 3666 // CHECK3-NEXT: entry: 3667 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 3668 // CHECK3-NEXT: ret void 3669 // 3670 // 3671 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 3672 // CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 3673 // CHECK9-NEXT: entry: 3674 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3675 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3676 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 3677 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3678 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 3679 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3680 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 3681 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8 3682 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 3683 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 3684 // CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 3685 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3686 // CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 3687 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 3688 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @.omp_outlined., i64 [[TMP4]]) 3689 // CHECK9-NEXT: ret void 3690 // 3691 // 3692 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 3693 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3694 // CHECK9-NEXT: entry: 3695 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3696 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3697 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3698 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3699 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3700 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3701 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3702 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3703 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3704 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3705 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3706 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3707 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3708 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3709 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 3710 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3711 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3712 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3713 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 3714 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3715 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3716 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 3717 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3718 // CHECK9: cond.true: 3719 // CHECK9-NEXT: br label [[COND_END:%.*]] 3720 // CHECK9: cond.false: 3721 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3722 // CHECK9-NEXT: br label [[COND_END]] 3723 // CHECK9: cond.end: 3724 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3725 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3726 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3727 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3728 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3729 // CHECK9: omp.inner.for.cond: 3730 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3731 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3732 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3733 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3734 // CHECK9: omp.inner.for.body: 3735 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3736 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3737 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3738 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 3739 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3740 // CHECK9: omp.body.continue: 3741 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3742 // CHECK9: omp.inner.for.inc: 3743 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3744 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 3745 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 3746 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 3747 // CHECK9: omp.inner.for.end: 3748 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3749 // CHECK9: omp.loop.exit: 3750 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 3751 // CHECK9-NEXT: ret void 3752 // 3753 // 3754 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 3755 // CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3756 // CHECK9-NEXT: entry: 3757 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3758 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3759 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3760 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3761 // CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 3762 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8 3763 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @.omp_outlined..1, i64 [[TMP1]]) 3764 // CHECK9-NEXT: ret void 3765 // 3766 // 3767 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 3768 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3769 // CHECK9-NEXT: entry: 3770 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3771 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3772 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3773 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3774 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3775 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3776 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3777 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3778 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3779 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3780 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3781 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3782 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3783 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3784 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 3785 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3786 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3787 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3788 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 3789 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3790 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3791 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 3792 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3793 // CHECK9: cond.true: 3794 // CHECK9-NEXT: br label [[COND_END:%.*]] 3795 // CHECK9: cond.false: 3796 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3797 // CHECK9-NEXT: br label [[COND_END]] 3798 // CHECK9: cond.end: 3799 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3800 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3801 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3802 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3803 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3804 // CHECK9: omp.inner.for.cond: 3805 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3806 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3807 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3808 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3809 // CHECK9: omp.inner.for.body: 3810 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3811 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3812 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3813 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 3814 // CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3815 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 3816 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 3817 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 3818 // CHECK9-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2 3819 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3820 // CHECK9: omp.body.continue: 3821 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3822 // CHECK9: omp.inner.for.inc: 3823 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3824 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 3825 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 3826 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 3827 // CHECK9: omp.inner.for.end: 3828 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3829 // CHECK9: omp.loop.exit: 3830 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 3831 // CHECK9-NEXT: ret void 3832 // 3833 // 3834 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 3835 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3836 // CHECK9-NEXT: entry: 3837 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3838 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3839 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3840 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3841 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 3842 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3843 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 3844 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 3845 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8 3846 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3847 // CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 3848 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8 3849 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..2, i64 [[TMP1]], i64 [[TMP3]]) 3850 // CHECK9-NEXT: ret void 3851 // 3852 // 3853 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 3854 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3855 // CHECK9-NEXT: entry: 3856 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3857 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3858 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3859 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3860 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3861 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3862 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3863 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3864 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3865 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3866 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3867 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3868 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3869 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 3870 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 3871 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 3872 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 3873 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 3874 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 3875 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 3876 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 3877 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 3878 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3879 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 3880 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3881 // CHECK9: cond.true: 3882 // CHECK9-NEXT: br label [[COND_END:%.*]] 3883 // CHECK9: cond.false: 3884 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3885 // CHECK9-NEXT: br label [[COND_END]] 3886 // CHECK9: cond.end: 3887 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3888 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 3889 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 3890 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 3891 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3892 // CHECK9: omp.inner.for.cond: 3893 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3894 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 3895 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3896 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3897 // CHECK9: omp.inner.for.body: 3898 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3899 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3900 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 3901 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 3902 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 3903 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 3904 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4 3905 // CHECK9-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2 3906 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 3907 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 3908 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3909 // CHECK9-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 3910 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3911 // CHECK9: omp.body.continue: 3912 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3913 // CHECK9: omp.inner.for.inc: 3914 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 3915 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 3916 // CHECK9-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 3917 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 3918 // CHECK9: omp.inner.for.end: 3919 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3920 // CHECK9: omp.loop.exit: 3921 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 3922 // CHECK9-NEXT: ret void 3923 // 3924 // 3925 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 3926 // CHECK9-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 3927 // CHECK9-NEXT: entry: 3928 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3929 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 3930 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3931 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 3932 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 3933 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3934 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 3935 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 3936 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 3937 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3938 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3939 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3940 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 3941 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 3942 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 3943 // CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 3944 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 3945 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 3946 // CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 3947 // CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 3948 // CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 3949 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 3950 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 3951 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 3952 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 3953 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 3954 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 3955 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 3956 // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 3957 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 3958 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 3959 // CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 3960 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8 3961 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 3962 // CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 3963 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 3964 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..3, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]]) 3965 // CHECK9-NEXT: ret void 3966 // 3967 // 3968 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 3969 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 3970 // CHECK9-NEXT: entry: 3971 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 3972 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 3973 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3974 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 3975 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3976 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8 3977 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 3978 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3979 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 3980 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8 3981 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 3982 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3983 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3984 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 3985 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3986 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3987 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3988 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3989 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 3990 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 3991 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 3992 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 3993 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 3994 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 3995 // CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8 3996 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 3997 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 3998 // CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8 3999 // CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8 4000 // CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 4001 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 4002 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4003 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4004 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8 4005 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4006 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4007 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8 4008 // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8 4009 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8 4010 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4011 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 4012 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4013 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4014 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4015 // CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4016 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 4017 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 4018 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4019 // CHECK9: omp.dispatch.cond: 4020 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4021 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 4022 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4023 // CHECK9: cond.true: 4024 // CHECK9-NEXT: br label [[COND_END:%.*]] 4025 // CHECK9: cond.false: 4026 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4027 // CHECK9-NEXT: br label [[COND_END]] 4028 // CHECK9: cond.end: 4029 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4030 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4031 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4032 // CHECK9-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 4033 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4034 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4035 // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4036 // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4037 // CHECK9: omp.dispatch.body: 4038 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4039 // CHECK9: omp.inner.for.cond: 4040 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 4041 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] 4042 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 4043 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4044 // CHECK9: omp.inner.for.body: 4045 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 4046 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 4047 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4048 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] 4049 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]] 4050 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 4051 // CHECK9-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]] 4052 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 4053 // CHECK9-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] 4054 // CHECK9-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double 4055 // CHECK9-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 4056 // CHECK9-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 4057 // CHECK9-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] 4058 // CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3 4059 // CHECK9-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP13]] 4060 // CHECK9-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 4061 // CHECK9-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 4062 // CHECK9-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 4063 // CHECK9-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP13]] 4064 // CHECK9-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 4065 // CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 4066 // CHECK9-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP13]] 4067 // CHECK9-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 4068 // CHECK9-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP13]] 4069 // CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 4070 // CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]] 4071 // CHECK9-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3 4072 // CHECK9-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP13]] 4073 // CHECK9-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 4074 // CHECK9-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP13]] 4075 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 4076 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP13]] 4077 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 4078 // CHECK9-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP13]] 4079 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 4080 // CHECK9-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP13]] 4081 // CHECK9-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 4082 // CHECK9-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 4083 // CHECK9-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 4084 // CHECK9-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP13]] 4085 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4086 // CHECK9: omp.body.continue: 4087 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4088 // CHECK9: omp.inner.for.inc: 4089 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 4090 // CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 4091 // CHECK9-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] 4092 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 4093 // CHECK9: omp.inner.for.end: 4094 // CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4095 // CHECK9: omp.dispatch.inc: 4096 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4097 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4098 // CHECK9-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4099 // CHECK9-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 4100 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4101 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4102 // CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4103 // CHECK9-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 4104 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND]] 4105 // CHECK9: omp.dispatch.end: 4106 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 4107 // CHECK9-NEXT: ret void 4108 // 4109 // 4110 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 4111 // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4112 // CHECK9-NEXT: entry: 4113 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 4114 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4115 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4116 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4117 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4118 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 4119 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4120 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4121 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4122 // CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 4123 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4124 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4125 // CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 4126 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4127 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4128 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 4129 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4 4130 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8 4131 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 4132 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 4133 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 4134 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4135 // CHECK9-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2 4136 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4137 // CHECK9-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 4138 // CHECK9-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1 4139 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 8 4140 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..4, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]]) 4141 // CHECK9-NEXT: ret void 4142 // 4143 // 4144 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 4145 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4146 // CHECK9-NEXT: entry: 4147 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4148 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4149 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 4150 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4151 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4152 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4153 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4154 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4155 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4156 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4157 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4158 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 4159 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4160 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4161 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4162 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4163 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4164 // CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 4 4165 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4166 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4167 // CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 4168 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4169 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4170 // CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8 4171 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4172 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4173 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4174 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 4175 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 4176 // CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 4177 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 4178 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4179 // CHECK9-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 4180 // CHECK9-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 4181 // CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 4182 // CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4183 // CHECK9-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 4184 // CHECK9-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4 4185 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4186 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[I]], align 4 4187 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4188 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 4189 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 4190 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 4191 // CHECK9: omp.precond.then: 4192 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4193 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 4194 // CHECK9-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4 4195 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4196 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4197 // CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4198 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 4199 // CHECK9-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4200 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4201 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 4202 // CHECK9-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 4203 // CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4204 // CHECK9: cond.true: 4205 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 4206 // CHECK9-NEXT: br label [[COND_END:%.*]] 4207 // CHECK9: cond.false: 4208 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4209 // CHECK9-NEXT: br label [[COND_END]] 4210 // CHECK9: cond.end: 4211 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 4212 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4213 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4214 // CHECK9-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 4215 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4216 // CHECK9: omp.inner.for.cond: 4217 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4218 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4219 // CHECK9-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1 4220 // CHECK9-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]] 4221 // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4222 // CHECK9: omp.inner.for.body: 4223 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4224 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4225 // CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 4226 // CHECK9-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]] 4227 // CHECK9-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4 4228 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4 4229 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 4230 // CHECK9-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4 4231 // CHECK9-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4232 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32 4233 // CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1 4234 // CHECK9-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16 4235 // CHECK9-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2 4236 // CHECK9-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 4237 // CHECK9-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32 4238 // CHECK9-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 4239 // CHECK9-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 4240 // CHECK9-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1 4241 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 4242 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 4243 // CHECK9-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 4244 // CHECK9-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4 4245 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4246 // CHECK9: omp.body.continue: 4247 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4248 // CHECK9: omp.inner.for.inc: 4249 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4250 // CHECK9-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1 4251 // CHECK9-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4 4252 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4253 // CHECK9: omp.inner.for.end: 4254 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4255 // CHECK9: omp.loop.exit: 4256 // CHECK9-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4257 // CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 4258 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]]) 4259 // CHECK9-NEXT: br label [[OMP_PRECOND_END]] 4260 // CHECK9: omp.precond.end: 4261 // CHECK9-NEXT: ret void 4262 // 4263 // 4264 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 4265 // CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 4266 // CHECK9-NEXT: entry: 4267 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4268 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4269 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4270 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4271 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4272 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4273 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4274 // CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 4275 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4276 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4277 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4278 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4279 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4280 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4281 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4282 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 4283 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 4284 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8 4285 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..5, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) 4286 // CHECK9-NEXT: ret void 4287 // 4288 // 4289 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 4290 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 4291 // CHECK9-NEXT: entry: 4292 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4293 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4294 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 4295 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4296 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4297 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4298 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 4299 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4300 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4301 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4302 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4303 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4304 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4305 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4306 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4307 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4308 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 4309 // CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 4310 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 4311 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 4312 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 4313 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 4314 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 4315 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 4316 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 4317 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4318 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 4319 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4320 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4321 // CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4322 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 4323 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4324 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4325 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 4326 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4327 // CHECK9: cond.true: 4328 // CHECK9-NEXT: br label [[COND_END:%.*]] 4329 // CHECK9: cond.false: 4330 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4331 // CHECK9-NEXT: br label [[COND_END]] 4332 // CHECK9: cond.end: 4333 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 4334 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4335 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4336 // CHECK9-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 4337 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4338 // CHECK9: omp.inner.for.cond: 4339 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4340 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4341 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 4342 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4343 // CHECK9: omp.inner.for.body: 4344 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4345 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 4346 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4347 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 4348 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4 4349 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 4350 // CHECK9-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 4351 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 4352 // CHECK9-NEXT: store double [[ADD4]], ptr [[A]], align 8 4353 // CHECK9-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 4354 // CHECK9-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 8 4355 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 4356 // CHECK9-NEXT: store double [[INC]], ptr [[A5]], align 8 4357 // CHECK9-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 4358 // CHECK9-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 4359 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]] 4360 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1 4361 // CHECK9-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2 4362 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4363 // CHECK9: omp.body.continue: 4364 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4365 // CHECK9: omp.inner.for.inc: 4366 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4367 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 4368 // CHECK9-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4 4369 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4370 // CHECK9: omp.inner.for.end: 4371 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4372 // CHECK9: omp.loop.exit: 4373 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 4374 // CHECK9-NEXT: ret void 4375 // 4376 // 4377 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 4378 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4379 // CHECK9-NEXT: entry: 4380 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4381 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4382 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4383 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4384 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4385 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4386 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4387 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4388 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4389 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4390 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 4391 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 4392 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4393 // CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 4394 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8 4395 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..6, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]]) 4396 // CHECK9-NEXT: ret void 4397 // 4398 // 4399 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 4400 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4401 // CHECK9-NEXT: entry: 4402 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 4403 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 4404 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4405 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4406 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 4407 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4408 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 4409 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4410 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4411 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4412 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4413 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 4414 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 4415 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 4416 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 4417 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8 4418 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 4419 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 4420 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4421 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 4422 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4423 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4424 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 4425 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 4426 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4427 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4428 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 4429 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4430 // CHECK9: cond.true: 4431 // CHECK9-NEXT: br label [[COND_END:%.*]] 4432 // CHECK9: cond.false: 4433 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4434 // CHECK9-NEXT: br label [[COND_END]] 4435 // CHECK9: cond.end: 4436 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 4437 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4438 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4439 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 4440 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4441 // CHECK9: omp.inner.for.cond: 4442 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4443 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4444 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 4445 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4446 // CHECK9: omp.inner.for.body: 4447 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4448 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 4449 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4450 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 4451 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4 4452 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 4453 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4 4454 // CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4455 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 4456 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 4457 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4458 // CHECK9-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 4459 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 4460 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 4461 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 4462 // CHECK9-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 4463 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4464 // CHECK9: omp.body.continue: 4465 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4466 // CHECK9: omp.inner.for.inc: 4467 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4468 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 4469 // CHECK9-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 4470 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] 4471 // CHECK9: omp.inner.for.end: 4472 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4473 // CHECK9: omp.loop.exit: 4474 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 4475 // CHECK9-NEXT: ret void 4476 // 4477 // 4478 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103 4479 // CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 4480 // CHECK11-NEXT: entry: 4481 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4482 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4483 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 4484 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4485 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) 4486 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4487 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4488 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 4489 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4490 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4 4491 // CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4492 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4493 // CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 4494 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 4495 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @.omp_outlined., i32 [[TMP4]]) 4496 // CHECK11-NEXT: ret void 4497 // 4498 // 4499 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 4500 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4501 // CHECK11-NEXT: entry: 4502 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4503 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4504 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4505 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4506 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4507 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4508 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4509 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4510 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4511 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4512 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4513 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4514 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4515 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4516 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 4517 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4518 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4519 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4520 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 4521 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4522 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4523 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 4524 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4525 // CHECK11: cond.true: 4526 // CHECK11-NEXT: br label [[COND_END:%.*]] 4527 // CHECK11: cond.false: 4528 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4529 // CHECK11-NEXT: br label [[COND_END]] 4530 // CHECK11: cond.end: 4531 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4532 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4533 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4534 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 4535 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4536 // CHECK11: omp.inner.for.cond: 4537 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4538 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4539 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4540 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4541 // CHECK11: omp.inner.for.body: 4542 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4543 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4544 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4545 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 4546 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4547 // CHECK11: omp.body.continue: 4548 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4549 // CHECK11: omp.inner.for.inc: 4550 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4551 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 4552 // CHECK11-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 4553 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4554 // CHECK11: omp.inner.for.end: 4555 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4556 // CHECK11: omp.loop.exit: 4557 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 4558 // CHECK11-NEXT: ret void 4559 // 4560 // 4561 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113 4562 // CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4563 // CHECK11-NEXT: entry: 4564 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4565 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4566 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4567 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4568 // CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2 4569 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4 4570 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @.omp_outlined..1, i32 [[TMP1]]) 4571 // CHECK11-NEXT: ret void 4572 // 4573 // 4574 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 4575 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4576 // CHECK11-NEXT: entry: 4577 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4578 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4579 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4580 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4581 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4582 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4583 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4584 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4585 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4586 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4587 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4588 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4589 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4590 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4591 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 4592 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4593 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4594 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4595 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 4596 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4597 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4598 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 4599 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4600 // CHECK11: cond.true: 4601 // CHECK11-NEXT: br label [[COND_END:%.*]] 4602 // CHECK11: cond.false: 4603 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4604 // CHECK11-NEXT: br label [[COND_END]] 4605 // CHECK11: cond.end: 4606 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4607 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4608 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4609 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 4610 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4611 // CHECK11: omp.inner.for.cond: 4612 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4613 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4614 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4615 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4616 // CHECK11: omp.inner.for.body: 4617 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4618 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4619 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4620 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 4621 // CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4622 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32 4623 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 4624 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 4625 // CHECK11-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2 4626 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4627 // CHECK11: omp.body.continue: 4628 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4629 // CHECK11: omp.inner.for.inc: 4630 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4631 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1 4632 // CHECK11-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 4633 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4634 // CHECK11: omp.inner.for.end: 4635 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4636 // CHECK11: omp.loop.exit: 4637 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 4638 // CHECK11-NEXT: ret void 4639 // 4640 // 4641 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120 4642 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4643 // CHECK11-NEXT: entry: 4644 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4645 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4646 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4647 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4648 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4649 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4650 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 4651 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4 4652 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4 4653 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4654 // CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2 4655 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4 4656 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..2, i32 [[TMP1]], i32 [[TMP3]]) 4657 // CHECK11-NEXT: ret void 4658 // 4659 // 4660 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 4661 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4662 // CHECK11-NEXT: entry: 4663 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4664 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4665 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4666 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4667 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4668 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4669 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4670 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4671 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4672 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4673 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4674 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4675 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4676 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4677 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4678 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4679 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 4680 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4681 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4682 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4683 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 4684 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 4685 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4686 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9 4687 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4688 // CHECK11: cond.true: 4689 // CHECK11-NEXT: br label [[COND_END:%.*]] 4690 // CHECK11: cond.false: 4691 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4692 // CHECK11-NEXT: br label [[COND_END]] 4693 // CHECK11: cond.end: 4694 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4695 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4696 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4697 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 4698 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4699 // CHECK11: omp.inner.for.cond: 4700 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4701 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4702 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4703 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4704 // CHECK11: omp.inner.for.body: 4705 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4706 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4707 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4708 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 4709 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 4710 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 4711 // CHECK11-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4 4712 // CHECK11-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4713 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 4714 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 4715 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4716 // CHECK11-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 4717 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4718 // CHECK11: omp.body.continue: 4719 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4720 // CHECK11: omp.inner.for.inc: 4721 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4722 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1 4723 // CHECK11-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 4724 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4725 // CHECK11: omp.inner.for.end: 4726 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4727 // CHECK11: omp.loop.exit: 4728 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 4729 // CHECK11-NEXT: ret void 4730 // 4731 // 4732 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145 4733 // CHECK11-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 4734 // CHECK11-NEXT: entry: 4735 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4736 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 4737 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4738 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 4739 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 4740 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4741 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4742 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 4743 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 4744 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4745 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4746 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4747 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4748 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 4749 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 4750 // CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 4751 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 4752 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 4753 // CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 4754 // CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 4755 // CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 4756 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4757 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 4758 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 4759 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 4760 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 4761 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 4762 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 4763 // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 4764 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 4765 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 4766 // CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4 4767 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4 4768 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4769 // CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 4770 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 4771 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..3, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]]) 4772 // CHECK11-NEXT: ret void 4773 // 4774 // 4775 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 4776 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 4777 // CHECK11-NEXT: entry: 4778 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4779 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4780 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4781 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 4782 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4783 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4 4784 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 4785 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4786 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4787 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4 4788 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4 4789 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4790 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4791 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4792 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4793 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4794 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4795 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4796 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4797 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4798 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4799 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4800 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 4801 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 4802 // CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4 4803 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 4804 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 4805 // CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4 4806 // CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4 4807 // CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4 4808 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4809 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 4810 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 4811 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4 4812 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 4813 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 4814 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4 4815 // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4 4816 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4 4817 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 4818 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 4819 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 4820 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 4821 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 4822 // CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 4823 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 4824 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 4825 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4826 // CHECK11: omp.dispatch.cond: 4827 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4828 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9 4829 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4830 // CHECK11: cond.true: 4831 // CHECK11-NEXT: br label [[COND_END:%.*]] 4832 // CHECK11: cond.false: 4833 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4834 // CHECK11-NEXT: br label [[COND_END]] 4835 // CHECK11: cond.end: 4836 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4837 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 4838 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4839 // CHECK11-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4 4840 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 4841 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4842 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4843 // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4844 // CHECK11: omp.dispatch.body: 4845 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4846 // CHECK11: omp.inner.for.cond: 4847 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]] 4848 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]] 4849 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 4850 // CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4851 // CHECK11: omp.inner.for.body: 4852 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 4853 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 4854 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4855 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] 4856 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]] 4857 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 4858 // CHECK11-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]] 4859 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 4860 // CHECK11-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] 4861 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double 4862 // CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 4863 // CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 4864 // CHECK11-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] 4865 // CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3 4866 // CHECK11-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]] 4867 // CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 4868 // CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 4869 // CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 4870 // CHECK11-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]] 4871 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 4872 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 4873 // CHECK11-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP14]] 4874 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 4875 // CHECK11-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP14]] 4876 // CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 4877 // CHECK11-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]] 4878 // CHECK11-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3 4879 // CHECK11-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP14]] 4880 // CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 4881 // CHECK11-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP14]] 4882 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0 4883 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]] 4884 // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 4885 // CHECK11-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]] 4886 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1 4887 // CHECK11-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP14]] 4888 // CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 4889 // CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 4890 // CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 4891 // CHECK11-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP14]] 4892 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4893 // CHECK11: omp.body.continue: 4894 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4895 // CHECK11: omp.inner.for.inc: 4896 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 4897 // CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 4898 // CHECK11-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]] 4899 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 4900 // CHECK11: omp.inner.for.end: 4901 // CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4902 // CHECK11: omp.dispatch.inc: 4903 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 4904 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4905 // CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4906 // CHECK11-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4 4907 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 4908 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 4909 // CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4910 // CHECK11-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4 4911 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND]] 4912 // CHECK11: omp.dispatch.end: 4913 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]]) 4914 // CHECK11-NEXT: ret void 4915 // 4916 // 4917 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200 4918 // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4919 // CHECK11-NEXT: entry: 4920 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4921 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4922 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4923 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4924 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 4925 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 4926 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4927 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4928 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4929 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4930 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4931 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4932 // CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 4933 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 4934 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 4935 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4 4936 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4 4937 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4 4938 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4 4939 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 4940 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4 4941 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2 4942 // CHECK11-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2 4943 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4 4944 // CHECK11-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 4945 // CHECK11-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1 4946 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 4 4947 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..4, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]]) 4948 // CHECK11-NEXT: ret void 4949 // 4950 // 4951 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 4952 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4953 // CHECK11-NEXT: entry: 4954 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 4955 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 4956 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4957 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4958 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4959 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4960 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 4961 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4962 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4963 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4964 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4965 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 4966 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4967 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4968 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4969 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4970 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4971 // CHECK11-NEXT: [[I5:%.*]] = alloca i32, align 4 4972 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 4973 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 4974 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 4975 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 4976 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 4977 // CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4 4978 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 4979 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 4980 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 4981 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 4982 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4 4983 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 4984 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 4985 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4986 // CHECK11-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]] 4987 // CHECK11-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 4988 // CHECK11-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1 4989 // CHECK11-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4990 // CHECK11-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 4991 // CHECK11-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4 4992 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4993 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[I]], align 4 4994 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 4995 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 4996 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] 4997 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 4998 // CHECK11: omp.precond.then: 4999 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5000 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 5001 // CHECK11-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4 5002 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5003 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5004 // CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5005 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 5006 // CHECK11-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 5007 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5008 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 5009 // CHECK11-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]] 5010 // CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5011 // CHECK11: cond.true: 5012 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 5013 // CHECK11-NEXT: br label [[COND_END:%.*]] 5014 // CHECK11: cond.false: 5015 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5016 // CHECK11-NEXT: br label [[COND_END]] 5017 // CHECK11: cond.end: 5018 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] 5019 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 5020 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5021 // CHECK11-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 5022 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5023 // CHECK11: omp.inner.for.cond: 5024 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5025 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5026 // CHECK11-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1 5027 // CHECK11-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]] 5028 // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5029 // CHECK11: omp.inner.for.body: 5030 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 5031 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5032 // CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1 5033 // CHECK11-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]] 5034 // CHECK11-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4 5035 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4 5036 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1 5037 // CHECK11-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4 5038 // CHECK11-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5039 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32 5040 // CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1 5041 // CHECK11-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16 5042 // CHECK11-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2 5043 // CHECK11-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1 5044 // CHECK11-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32 5045 // CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 5046 // CHECK11-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 5047 // CHECK11-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1 5048 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 5049 // CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 5050 // CHECK11-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 5051 // CHECK11-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4 5052 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5053 // CHECK11: omp.body.continue: 5054 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5055 // CHECK11: omp.inner.for.inc: 5056 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5057 // CHECK11-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1 5058 // CHECK11-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4 5059 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 5060 // CHECK11: omp.inner.for.end: 5061 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5062 // CHECK11: omp.loop.exit: 5063 // CHECK11-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5064 // CHECK11-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 5065 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]]) 5066 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 5067 // CHECK11: omp.precond.end: 5068 // CHECK11-NEXT: ret void 5069 // 5070 // 5071 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218 5072 // CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 5073 // CHECK11-NEXT: entry: 5074 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 5075 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5076 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5077 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5078 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 5079 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5080 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 5081 // CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 5082 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 5083 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 5084 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 5085 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 5086 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 5087 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 5088 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 5089 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 5090 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4 5091 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4 5092 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..5, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]]) 5093 // CHECK11-NEXT: ret void 5094 // 5095 // 5096 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 5097 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 5098 // CHECK11-NEXT: entry: 5099 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5100 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5101 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 5102 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5103 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5104 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5105 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4 5106 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5107 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 5108 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5109 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5110 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5111 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5112 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 5113 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5114 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5115 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 5116 // CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4 5117 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 5118 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 5119 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4 5120 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 5121 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 5122 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 5123 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4 5124 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5125 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 5126 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5127 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5128 // CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5129 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 5130 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 5131 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5132 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9 5133 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5134 // CHECK11: cond.true: 5135 // CHECK11-NEXT: br label [[COND_END:%.*]] 5136 // CHECK11: cond.false: 5137 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5138 // CHECK11-NEXT: br label [[COND_END]] 5139 // CHECK11: cond.end: 5140 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 5141 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 5142 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5143 // CHECK11-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 5144 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5145 // CHECK11: omp.inner.for.cond: 5146 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5147 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5148 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 5149 // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5150 // CHECK11: omp.inner.for.body: 5151 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5152 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1 5153 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5154 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 5155 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4 5156 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 5157 // CHECK11-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00 5158 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0 5159 // CHECK11-NEXT: store double [[ADD4]], ptr [[A]], align 4 5160 // CHECK11-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0 5161 // CHECK11-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 4 5162 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 5163 // CHECK11-NEXT: store double [[INC]], ptr [[A5]], align 4 5164 // CHECK11-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 5165 // CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 5166 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]] 5167 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1 5168 // CHECK11-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2 5169 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5170 // CHECK11: omp.body.continue: 5171 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5172 // CHECK11: omp.inner.for.inc: 5173 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5174 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 5175 // CHECK11-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4 5176 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 5177 // CHECK11: omp.inner.for.end: 5178 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5179 // CHECK11: omp.loop.exit: 5180 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]]) 5181 // CHECK11-NEXT: ret void 5182 // 5183 // 5184 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183 5185 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5186 // CHECK11-NEXT: entry: 5187 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5188 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5189 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 5190 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5191 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5192 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5193 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5194 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 5195 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 5196 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4 5197 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4 5198 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4 5199 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5200 // CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2 5201 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4 5202 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..6, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]]) 5203 // CHECK11-NEXT: ret void 5204 // 5205 // 5206 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 5207 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5208 // CHECK11-NEXT: entry: 5209 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 5210 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 5211 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5212 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5213 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 5214 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5215 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 5216 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5217 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5218 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5219 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5220 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 5221 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 5222 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 5223 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 5224 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4 5225 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 5226 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 5227 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 5228 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 5229 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 5230 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 5231 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 5232 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 5233 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 5234 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5235 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9 5236 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5237 // CHECK11: cond.true: 5238 // CHECK11-NEXT: br label [[COND_END:%.*]] 5239 // CHECK11: cond.false: 5240 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5241 // CHECK11-NEXT: br label [[COND_END]] 5242 // CHECK11: cond.end: 5243 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 5244 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 5245 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 5246 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 5247 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5248 // CHECK11: omp.inner.for.cond: 5249 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5250 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 5251 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 5252 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5253 // CHECK11: omp.inner.for.body: 5254 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5255 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 5256 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 5257 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 5258 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4 5259 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 5260 // CHECK11-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4 5261 // CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2 5262 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32 5263 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 5264 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5265 // CHECK11-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 5266 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 5267 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 5268 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 5269 // CHECK11-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 5270 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5271 // CHECK11: omp.body.continue: 5272 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5273 // CHECK11: omp.inner.for.inc: 5274 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 5275 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 5276 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 5277 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 5278 // CHECK11: omp.inner.for.end: 5279 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5280 // CHECK11: omp.loop.exit: 5281 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) 5282 // CHECK11-NEXT: ret void 5283 // 5284