1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s 4 // RUN: %clang_cc1 -no-enable-noundef-analysis -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -no-enable-noundef-analysis -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 7 8 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s 10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // expected-no-diagnostics 14 #ifndef HEADER 15 #define HEADER 16 17 struct St { 18 int a, b; 19 St() : a(0), b(0) {} 20 St(const St &st) : a(st.a + st.b), b(0) {} 21 ~St() {} 22 }; 23 24 volatile int g = 1212; 25 26 template <class T> 27 struct S { 28 T f; 29 S(T a) : f(a + g) {} 30 S() : f(g) {} 31 S(const S &s, St t = St()) : f(s.f + t.a) {} 32 operator T() { return T(); } 33 ~S() {} 34 }; 35 36 37 template <typename T> 38 T tmain() { 39 S<T> test; 40 T t_var = T(); 41 T vec[] = {1, 2}; 42 S<T> s_arr[] = {1, 2}; 43 S<T> var(3); 44 #pragma omp parallel 45 #pragma omp single firstprivate(t_var, vec, s_arr, var) 46 { 47 vec[0] = t_var; 48 s_arr[0] = var; 49 } 50 return T(); 51 } 52 53 S<float> test; 54 int t_var = 333; 55 int vec[] = {1, 2}; 56 S<float> s_arr[] = {1, 2}; 57 S<float> var(3); 58 59 int main() { 60 static int sivar; 61 #ifdef LAMBDA 62 [&]() { 63 #pragma omp parallel 64 #pragma omp single firstprivate(g, sivar) 65 { 66 g = 1; 67 sivar = 17; 68 [&]() { 69 g = 2; 70 sivar = 31; 71 }(); 72 } 73 }(); 74 return 0; 75 #elif defined(BLOCKS) 76 ^{ 77 #pragma omp parallel 78 #pragma omp single firstprivate(g, sivar) 79 { 80 g = 1; 81 sivar = 37; 82 ^{ 83 g = 2; 84 sivar = 31; 85 }(); 86 } 87 }(); 88 return 0; 89 #else 90 #pragma omp single firstprivate(t_var, vec, s_arr, var, sivar) nowait 91 { 92 { 93 vec[0] = t_var; 94 s_arr[0] = var; 95 sivar = 41; 96 } 97 } 98 return tmain<int>(); 99 #endif 100 } 101 102 103 // firstprivate t_var(t_var) 104 105 // firstprivate vec(vec) 106 107 // firstprivate s_arr(s_arr) 108 109 // firstprivate var(var) 110 111 // firstprivate isvar 112 // CHEC: [[SIVAR_VAL:%.+]] = load i{{[0-9]+}}, iptr [[SIVAR]], 113 // CHEC: store i{{[0-9]+}} [[SIVAR_VAL]], iptr [[SIVAR_PRIV]], 114 115 // ~(firstprivate var), ~(firstprivate s_arr) 116 117 118 119 120 121 122 123 // firstprivate t_var(t_var) 124 125 // firstprivate vec(vec) 126 127 // firstprivate s_arr(s_arr) 128 129 // firstprivate var(var) 130 131 // ~(firstprivate var), ~(firstprivate s_arr) 132 133 134 #endif 135 136 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 137 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 138 // CHECK1-NEXT: entry: 139 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) @test) 140 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 141 // CHECK1-NEXT: ret void 142 // 143 // 144 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 145 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 146 // CHECK1-NEXT: entry: 147 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 148 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 149 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 150 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) 151 // CHECK1-NEXT: ret void 152 // 153 // 154 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 155 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 156 // CHECK1-NEXT: entry: 157 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 158 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 159 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 160 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 161 // CHECK1-NEXT: ret void 162 // 163 // 164 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 165 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 166 // CHECK1-NEXT: entry: 167 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 168 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 169 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 170 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 171 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 172 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 173 // CHECK1-NEXT: store float [[CONV]], ptr [[F]], align 4 174 // CHECK1-NEXT: ret void 175 // 176 // 177 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 178 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 179 // CHECK1-NEXT: entry: 180 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 181 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 182 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 183 // CHECK1-NEXT: ret void 184 // 185 // 186 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 187 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 188 // CHECK1-NEXT: entry: 189 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @s_arr, float 1.000000e+00) 190 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float 2.000000e+00) 191 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 192 // CHECK1-NEXT: ret void 193 // 194 // 195 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 196 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 197 // CHECK1-NEXT: entry: 198 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 199 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 200 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 201 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 202 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 203 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 204 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 205 // CHECK1-NEXT: ret void 206 // 207 // 208 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 209 // CHECK1-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 210 // CHECK1-NEXT: entry: 211 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 212 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 213 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 214 // CHECK1: arraydestroy.body: 215 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 216 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 217 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 218 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 219 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 220 // CHECK1: arraydestroy.done1: 221 // CHECK1-NEXT: ret void 222 // 223 // 224 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 225 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 226 // CHECK1-NEXT: entry: 227 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 228 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 229 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 230 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 231 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 232 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 233 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 234 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 235 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 236 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 237 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 238 // CHECK1-NEXT: ret void 239 // 240 // 241 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 242 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 243 // CHECK1-NEXT: entry: 244 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 245 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 246 // CHECK1-NEXT: ret void 247 // 248 // 249 // CHECK1-LABEL: define {{[^@]+}}@main 250 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 251 // CHECK1-NEXT: entry: 252 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 253 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 254 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 255 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 256 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 257 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 258 // CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4 259 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 260 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) 261 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 262 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP0]]) 263 // CHECK1-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 264 // CHECK1-NEXT: br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] 265 // CHECK1: omp_if.then: 266 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @t_var, align 4 267 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4 268 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @vec, i64 8, i1 false) 269 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 270 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 271 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP4]] 272 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 273 // CHECK1: omp.arraycpy.body: 274 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @s_arr, [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 275 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 276 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 277 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) 278 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 279 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 280 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 281 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] 282 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] 283 // CHECK1: omp.arraycpy.done1: 284 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) 285 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR]], ptr nonnull align 4 dereferenceable(4) @var, ptr [[AGG_TMP2]]) 286 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] 287 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 288 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR]], align 4 289 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4 290 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 291 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 4 292 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 293 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) 294 // CHECK1-NEXT: store i32 41, ptr [[SIVAR]], align 4 295 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 296 // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 297 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i64 2 298 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 299 // CHECK1: arraydestroy.body: 300 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[OMP_ARRAYCPY_DONE1]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 301 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 302 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 303 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 304 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 305 // CHECK1: arraydestroy.done5: 306 // CHECK1-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP0]]) 307 // CHECK1-NEXT: br label [[OMP_IF_END]] 308 // CHECK1: omp_if.end: 309 // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 310 // CHECK1-NEXT: ret i32 [[CALL]] 311 // 312 // 313 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 314 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 315 // CHECK1-NEXT: entry: 316 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 317 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 318 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 319 // CHECK1-NEXT: call void @_ZN2StC2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) 320 // CHECK1-NEXT: ret void 321 // 322 // 323 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 324 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 325 // CHECK1-NEXT: entry: 326 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 327 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 328 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 329 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 330 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 331 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 332 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) 333 // CHECK1-NEXT: ret void 334 // 335 // 336 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 337 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 338 // CHECK1-NEXT: entry: 339 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 340 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 341 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 342 // CHECK1-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 343 // CHECK1-NEXT: ret void 344 // 345 // 346 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 347 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] { 348 // CHECK1-NEXT: entry: 349 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 350 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 351 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 352 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 353 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 354 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 355 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) 356 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 357 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 358 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 359 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 360 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 361 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 362 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 363 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @.omp_outlined., ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) 364 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 365 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 366 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 367 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 368 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 369 // CHECK1: arraydestroy.body: 370 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 371 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 372 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 373 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 374 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 375 // CHECK1: arraydestroy.done1: 376 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 377 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 378 // CHECK1-NEXT: ret i32 [[TMP1]] 379 // 380 // 381 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 382 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 383 // CHECK1-NEXT: entry: 384 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 385 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 386 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 387 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0 388 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 389 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1 390 // CHECK1-NEXT: store i32 0, ptr [[B]], align 4 391 // CHECK1-NEXT: ret void 392 // 393 // 394 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 395 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 396 // CHECK1-NEXT: entry: 397 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 398 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 399 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 400 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 401 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 402 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 403 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 404 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 405 // CHECK1-NEXT: [[TMP1:%.*]] = load float, ptr [[F2]], align 4 406 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 407 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 408 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 409 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 410 // CHECK1-NEXT: store float [[ADD]], ptr [[F]], align 4 411 // CHECK1-NEXT: ret void 412 // 413 // 414 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 415 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 416 // CHECK1-NEXT: entry: 417 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 418 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 419 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 420 // CHECK1-NEXT: ret void 421 // 422 // 423 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 424 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 425 // CHECK1-NEXT: entry: 426 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 427 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 428 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 429 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) 430 // CHECK1-NEXT: ret void 431 // 432 // 433 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 434 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 435 // CHECK1-NEXT: entry: 436 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 437 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 438 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 439 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 440 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 441 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 442 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 443 // CHECK1-NEXT: ret void 444 // 445 // 446 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 447 // CHECK1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR7:[0-9]+]] { 448 // CHECK1-NEXT: entry: 449 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 450 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 451 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 452 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8 453 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 454 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 455 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 456 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 457 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 458 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 459 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 460 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 461 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 462 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 463 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 464 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 465 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 466 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 467 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 468 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 469 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 470 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 471 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 472 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 473 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP5]]) 474 // CHECK1-NEXT: [[TMP7:%.*]] = icmp ne i32 [[TMP6]], 0 475 // CHECK1-NEXT: br i1 [[TMP7]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] 476 // CHECK1: omp_if.then: 477 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP0]], align 4 478 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[T_VAR1]], align 4 479 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP1]], i64 8, i1 false) 480 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 481 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 482 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP9]] 483 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 484 // CHECK1: omp.arraycpy.body: 485 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 486 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 487 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 488 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) 489 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 490 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 491 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 492 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] 493 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 494 // CHECK1: omp.arraycpy.done4: 495 // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 496 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR5]], ptr nonnull align 4 dereferenceable(4) [[TMP3]], ptr [[AGG_TMP6]]) 497 // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 498 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 499 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 500 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 501 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 502 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR5]], i64 4, i1 false) 503 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] 504 // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 505 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 506 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 507 // CHECK1: arraydestroy.body: 508 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP11]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 509 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 510 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 511 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 512 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 513 // CHECK1: arraydestroy.done9: 514 // CHECK1-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP5]]) 515 // CHECK1-NEXT: br label [[OMP_IF_END]] 516 // CHECK1: omp_if.end: 517 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP5]]) 518 // CHECK1-NEXT: ret void 519 // 520 // 521 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 522 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 523 // CHECK1-NEXT: entry: 524 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 525 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 526 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 527 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 528 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 529 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 530 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[THIS1]], ptr nonnull align 4 dereferenceable(4) [[TMP0]], ptr [[T]]) 531 // CHECK1-NEXT: ret void 532 // 533 // 534 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 535 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 536 // CHECK1-NEXT: entry: 537 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 538 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 539 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 540 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 541 // CHECK1-NEXT: ret void 542 // 543 // 544 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 545 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 546 // CHECK1-NEXT: entry: 547 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 548 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 549 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 550 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 551 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 552 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 553 // CHECK1-NEXT: ret void 554 // 555 // 556 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 557 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 558 // CHECK1-NEXT: entry: 559 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 560 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 561 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 562 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 563 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 564 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 565 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 566 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 567 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 568 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 569 // CHECK1-NEXT: ret void 570 // 571 // 572 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 573 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr nonnull align 4 dereferenceable(4) [[S:%.*]], ptr [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 574 // CHECK1-NEXT: entry: 575 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 576 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca ptr, align 8 577 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 578 // CHECK1-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 579 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 580 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 581 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 582 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 583 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 584 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0 585 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 586 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 587 // CHECK1-NEXT: store i32 [[ADD]], ptr [[F]], align 4 588 // CHECK1-NEXT: ret void 589 // 590 // 591 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 592 // CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 593 // CHECK1-NEXT: entry: 594 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 595 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 596 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 597 // CHECK1-NEXT: ret void 598 // 599 // 600 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp 601 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 602 // CHECK1-NEXT: entry: 603 // CHECK1-NEXT: call void @__cxx_global_var_init() 604 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 605 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 606 // CHECK1-NEXT: ret void 607 // 608 // 609 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 610 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 611 // CHECK3-NEXT: entry: 612 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) @test) 613 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 614 // CHECK3-NEXT: ret void 615 // 616 // 617 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 618 // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 619 // CHECK3-NEXT: entry: 620 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 621 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 622 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 623 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) 624 // CHECK3-NEXT: ret void 625 // 626 // 627 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 628 // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 629 // CHECK3-NEXT: entry: 630 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 631 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 632 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 633 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 634 // CHECK3-NEXT: ret void 635 // 636 // 637 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 638 // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 639 // CHECK3-NEXT: entry: 640 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 641 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 642 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 643 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 644 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 645 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 646 // CHECK3-NEXT: store float [[CONV]], ptr [[F]], align 4 647 // CHECK3-NEXT: ret void 648 // 649 // 650 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 651 // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 652 // CHECK3-NEXT: entry: 653 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 654 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 655 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 656 // CHECK3-NEXT: ret void 657 // 658 // 659 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 660 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 661 // CHECK3-NEXT: entry: 662 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @s_arr, float 1.000000e+00) 663 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float 2.000000e+00) 664 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 665 // CHECK3-NEXT: ret void 666 // 667 // 668 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 669 // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 670 // CHECK3-NEXT: entry: 671 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 672 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 673 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 674 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 675 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 676 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 677 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 678 // CHECK3-NEXT: ret void 679 // 680 // 681 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 682 // CHECK3-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 683 // CHECK3-NEXT: entry: 684 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 685 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 686 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 687 // CHECK3: arraydestroy.body: 688 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 689 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 690 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 691 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 692 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 693 // CHECK3: arraydestroy.done1: 694 // CHECK3-NEXT: ret void 695 // 696 // 697 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 698 // CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 699 // CHECK3-NEXT: entry: 700 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 701 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 702 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 703 // CHECK3-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 704 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 705 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 706 // CHECK3-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 707 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 708 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 709 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 710 // CHECK3-NEXT: store float [[ADD]], ptr [[F]], align 4 711 // CHECK3-NEXT: ret void 712 // 713 // 714 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 715 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 716 // CHECK3-NEXT: entry: 717 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 718 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 719 // CHECK3-NEXT: ret void 720 // 721 // 722 // CHECK3-LABEL: define {{[^@]+}}@main 723 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 724 // CHECK3-NEXT: entry: 725 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 726 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 727 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 728 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 729 // CHECK3-NEXT: store ptr @_ZZ4mainE5sivar, ptr [[TMP0]], align 8 730 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr nonnull align 8 dereferenceable(8) [[REF_TMP]]) 731 // CHECK3-NEXT: ret i32 0 732 // 733 // 734 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 735 // CHECK3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 736 // CHECK3-NEXT: entry: 737 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 738 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 739 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 740 // CHECK3-NEXT: [[G:%.*]] = alloca i32, align 4 741 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 742 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 743 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 744 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 745 // CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 746 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 747 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 748 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 749 // CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]]) 750 // CHECK3-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 751 // CHECK3-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] 752 // CHECK3: omp_if.then: 753 // CHECK3-NEXT: [[TMP5:%.*]] = load volatile i32, ptr @g, align 4 754 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[G]], align 4 755 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 756 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[SIVAR1]], align 4 757 // CHECK3-NEXT: store i32 1, ptr [[G]], align 4 758 // CHECK3-NEXT: store i32 17, ptr [[SIVAR1]], align 4 759 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 760 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP7]], align 8 761 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 762 // CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP8]], align 8 763 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr nonnull align 8 dereferenceable(16) [[REF_TMP]]) 764 // CHECK3-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP2]]) 765 // CHECK3-NEXT: br label [[OMP_IF_END]] 766 // CHECK3: omp_if.end: 767 // CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 768 // CHECK3-NEXT: ret void 769 // 770 // 771 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp 772 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 773 // CHECK3-NEXT: entry: 774 // CHECK3-NEXT: call void @__cxx_global_var_init() 775 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 776 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 777 // CHECK3-NEXT: ret void 778 // 779 // 780 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init 781 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 782 // CHECK4-NEXT: entry: 783 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(ptr nonnull align 4 dereferenceable(4) @test) 784 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]] 785 // CHECK4-NEXT: ret void 786 // 787 // 788 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 789 // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 790 // CHECK4-NEXT: entry: 791 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 792 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 793 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 794 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) 795 // CHECK4-NEXT: ret void 796 // 797 // 798 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 799 // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 800 // CHECK4-NEXT: entry: 801 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 802 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 803 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 804 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 805 // CHECK4-NEXT: ret void 806 // 807 // 808 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 809 // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 810 // CHECK4-NEXT: entry: 811 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 812 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 813 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 814 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 815 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, ptr @g, align 4 816 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 817 // CHECK4-NEXT: store float [[CONV]], ptr [[F]], align 4 818 // CHECK4-NEXT: ret void 819 // 820 // 821 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 822 // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 823 // CHECK4-NEXT: entry: 824 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 825 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 826 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 827 // CHECK4-NEXT: ret void 828 // 829 // 830 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 831 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 832 // CHECK4-NEXT: entry: 833 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @s_arr, float 1.000000e+00) 834 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float 2.000000e+00) 835 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]] 836 // CHECK4-NEXT: ret void 837 // 838 // 839 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 840 // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 841 // CHECK4-NEXT: entry: 842 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 843 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 844 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 845 // CHECK4-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 846 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 847 // CHECK4-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 848 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(ptr nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 849 // CHECK4-NEXT: ret void 850 // 851 // 852 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 853 // CHECK4-SAME: (ptr [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 854 // CHECK4-NEXT: entry: 855 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 856 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 857 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 858 // CHECK4: arraydestroy.body: 859 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 860 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 861 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 862 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr 863 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 864 // CHECK4: arraydestroy.done1: 865 // CHECK4-NEXT: ret void 866 // 867 // 868 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 869 // CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 870 // CHECK4-NEXT: entry: 871 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 872 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 873 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 874 // CHECK4-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 875 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 876 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 877 // CHECK4-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 878 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, ptr @g, align 4 879 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 880 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 881 // CHECK4-NEXT: store float [[ADD]], ptr [[F]], align 4 882 // CHECK4-NEXT: ret void 883 // 884 // 885 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 886 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 887 // CHECK4-NEXT: entry: 888 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(ptr nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 889 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]] 890 // CHECK4-NEXT: ret void 891 // 892 // 893 // CHECK4-LABEL: define {{[^@]+}}@main 894 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 895 // CHECK4-NEXT: entry: 896 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 897 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32 }>, align 8 898 // CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4 899 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0 900 // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 901 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 1 902 // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 903 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 2 904 // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 905 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 3 906 // CHECK4-NEXT: store ptr @__main_block_invoke, ptr [[BLOCK_INVOKE]], align 8 907 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 4 908 // CHECK4-NEXT: store ptr @__block_descriptor_tmp.3, ptr [[BLOCK_DESCRIPTOR]], align 8 909 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5 910 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 911 // CHECK4-NEXT: store i32 [[TMP0]], ptr [[BLOCK_CAPTURED]], align 8 912 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 913 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 914 // CHECK4-NEXT: call void [[TMP2]](ptr [[BLOCK]]) 915 // CHECK4-NEXT: ret i32 0 916 // 917 // 918 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke 919 // CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 920 // CHECK4-NEXT: entry: 921 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 922 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 923 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 924 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 925 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @.omp_outlined., ptr @_ZZ4mainE5sivar) 926 // CHECK4-NEXT: ret void 927 // 928 // 929 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 930 // CHECK4-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]], ptr nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 931 // CHECK4-NEXT: entry: 932 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 933 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 934 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 935 // CHECK4-NEXT: [[G:%.*]] = alloca i32, align 4 936 // CHECK4-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 937 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, align 8 938 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 939 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 940 // CHECK4-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 941 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 942 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 943 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 944 // CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP2]]) 945 // CHECK4-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 946 // CHECK4-NEXT: br i1 [[TMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] 947 // CHECK4: omp_if.then: 948 // CHECK4-NEXT: [[TMP5:%.*]] = load volatile i32, ptr @g, align 4 949 // CHECK4-NEXT: store i32 [[TMP5]], ptr [[G]], align 4 950 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 951 // CHECK4-NEXT: store i32 [[TMP6]], ptr [[SIVAR1]], align 4 952 // CHECK4-NEXT: store i32 1, ptr [[G]], align 4 953 // CHECK4-NEXT: store i32 37, ptr [[SIVAR1]], align 4 954 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 0 955 // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 956 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 1 957 // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 958 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 2 959 // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 960 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 3 961 // CHECK4-NEXT: store ptr @var_block_invoke, ptr [[BLOCK_INVOKE]], align 8 962 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 4 963 // CHECK4-NEXT: store ptr @__block_descriptor_tmp, ptr [[BLOCK_DESCRIPTOR]], align 8 964 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 5 965 // CHECK4-NEXT: [[TMP7:%.*]] = load volatile i32, ptr [[G]], align 4 966 // CHECK4-NEXT: store volatile i32 [[TMP7]], ptr [[BLOCK_CAPTURED]], align 8 967 // CHECK4-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[BLOCK]], i32 0, i32 6 968 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR1]], align 4 969 // CHECK4-NEXT: store i32 [[TMP8]], ptr [[BLOCK_CAPTURED2]], align 4 970 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 971 // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 972 // CHECK4-NEXT: call void [[TMP10]](ptr [[BLOCK]]) 973 // CHECK4-NEXT: call void @__kmpc_end_single(ptr @[[GLOB1]], i32 [[TMP2]]) 974 // CHECK4-NEXT: br label [[OMP_IF_END]] 975 // CHECK4: omp_if.end: 976 // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 977 // CHECK4-NEXT: ret void 978 // 979 // 980 // CHECK4-LABEL: define {{[^@]+}}@var_block_invoke 981 // CHECK4-SAME: (ptr [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 982 // CHECK4-NEXT: entry: 983 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 984 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 985 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 986 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 987 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 988 // CHECK4-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 8 989 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, i32, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 990 // CHECK4-NEXT: store i32 31, ptr [[BLOCK_CAPTURE_ADDR1]], align 4 991 // CHECK4-NEXT: ret void 992 // 993 // 994 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_firstprivate_codegen.cpp 995 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 996 // CHECK4-NEXT: entry: 997 // CHECK4-NEXT: call void @__cxx_global_var_init() 998 // CHECK4-NEXT: call void @__cxx_global_var_init.1() 999 // CHECK4-NEXT: call void @__cxx_global_var_init.2() 1000 // CHECK4-NEXT: ret void 1001 // 1002