1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 7 8 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s 10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // expected-no-diagnostics 14 #ifndef HEADER 15 #define HEADER 16 17 struct St { 18 int a, b; 19 St() : a(0), b(0) {} 20 St(const St &st) : a(st.a + st.b), b(0) {} 21 ~St() {} 22 }; 23 24 volatile int g = 1212; 25 26 template <class T> 27 struct S { 28 T f; 29 S(T a) : f(a + g) {} 30 S() : f(g) {} 31 S(const S &s, St t = St()) : f(s.f + t.a) {} 32 operator T() { return T(); } 33 ~S() {} 34 }; 35 36 37 template <typename T> 38 T tmain() { 39 S<T> test; 40 T t_var = T(); 41 T vec[] = {1, 2}; 42 S<T> s_arr[] = {1, 2}; 43 S<T> var(3); 44 #pragma omp parallel 45 #pragma omp sections firstprivate(t_var, vec, s_arr, var) 46 { 47 vec[0] = t_var; 48 #pragma omp section 49 s_arr[0] = var; 50 } 51 return T(); 52 } 53 54 S<float> test; 55 int t_var = 333; 56 int vec[] = {1, 2}; 57 S<float> s_arr[] = {1, 2}; 58 S<float> var(3); 59 60 int main() { 61 static int sivar; 62 #ifdef LAMBDA 63 [&]() { 64 #pragma omp parallel 65 #pragma omp sections firstprivate(g, sivar) 66 { 67 // Skip temp vars for loop 68 69 70 71 { 72 g = 1; 73 sivar = 10; 74 } 75 #pragma omp section 76 [&]() { 77 g = 2; 78 sivar = 20; 79 }(); 80 } 81 }(); 82 return 0; 83 #elif defined(BLOCKS) 84 ^{ 85 #pragma omp parallel 86 #pragma omp sections firstprivate(g, sivar) 87 { 88 // Skip temp vars for loop 89 90 91 92 { 93 g = 1; 94 sivar = 10; 95 } 96 #pragma omp section 97 ^{ 98 g = 2; 99 sivar = 20; 100 }(); 101 } 102 }(); 103 return 0; 104 #else 105 #pragma omp sections firstprivate(t_var, vec, s_arr, var, sivar) nowait 106 { 107 { 108 vec[0] = t_var; 109 s_arr[0] = var; 110 sivar = 31; 111 } 112 } 113 return tmain<int>(); 114 #endif 115 } 116 117 118 // firstprivate t_var(t_var) 119 120 // firstprivate vec(vec) 121 122 // firstprivate s_arr(s_arr) 123 124 // firstprivate var(var) 125 126 // firstprivate isvar 127 128 129 // ~(firstprivate var), ~(firstprivate s_arr) 130 131 132 133 // Skip temp vars for loop 134 135 136 // firstprivate t_var(t_var) 137 138 // firstprivate vec(vec) 139 140 // firstprivate s_arr(s_arr) 141 142 // firstprivate var(var) 143 144 // No synchronization for initialization. 145 146 147 // ~(firstprivate var), ~(firstprivate s_arr) 148 #endif 149 150 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 151 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 154 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 155 // CHECK1-NEXT: ret void 156 // 157 // 158 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 159 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 160 // CHECK1-NEXT: entry: 161 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 162 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 163 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 164 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 165 // CHECK1-NEXT: ret void 166 // 167 // 168 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 169 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 170 // CHECK1-NEXT: entry: 171 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 172 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 173 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 174 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 175 // CHECK1-NEXT: ret void 176 // 177 // 178 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 179 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 180 // CHECK1-NEXT: entry: 181 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 182 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 183 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 184 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 185 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 186 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 187 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 188 // CHECK1-NEXT: ret void 189 // 190 // 191 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 192 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 193 // CHECK1-NEXT: entry: 194 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 195 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 196 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 197 // CHECK1-NEXT: ret void 198 // 199 // 200 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 201 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 202 // CHECK1-NEXT: entry: 203 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 204 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 205 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 206 // CHECK1-NEXT: ret void 207 // 208 // 209 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 210 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 211 // CHECK1-NEXT: entry: 212 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 213 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 214 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 215 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 216 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 217 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 218 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 219 // CHECK1-NEXT: ret void 220 // 221 // 222 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 223 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 224 // CHECK1-NEXT: entry: 225 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 226 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 227 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 228 // CHECK1: arraydestroy.body: 229 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 230 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 231 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 232 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 233 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 234 // CHECK1: arraydestroy.done1: 235 // CHECK1-NEXT: ret void 236 // 237 // 238 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 239 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 240 // CHECK1-NEXT: entry: 241 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 242 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 243 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 244 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 245 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 246 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 247 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 248 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 249 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 250 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 251 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 252 // CHECK1-NEXT: ret void 253 // 254 // 255 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 256 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 257 // CHECK1-NEXT: entry: 258 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 259 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 260 // CHECK1-NEXT: ret void 261 // 262 // 263 // CHECK1-LABEL: define {{[^@]+}}@main 264 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 265 // CHECK1-NEXT: entry: 266 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 267 // CHECK1-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 268 // CHECK1-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 269 // CHECK1-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 270 // CHECK1-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 271 // CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 272 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 273 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 274 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 275 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 276 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 277 // CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4 278 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 279 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 280 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 281 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 282 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 283 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 284 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 285 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 286 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[T_VAR]], align 4 287 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 288 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 bitcast ([2 x i32]* @vec to i8*), i64 8, i1 false) 289 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 290 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 291 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP3]] 292 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 293 // CHECK1: omp.arraycpy.body: 294 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 295 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 296 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 297 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 298 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 299 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 300 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 301 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 302 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] 303 // CHECK1: omp.arraycpy.done1: 304 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) 305 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], %struct.S* nonnull align 4 dereferenceable(4) @var, %struct.St* [[AGG_TMP2]]) 306 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] 307 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 308 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[SIVAR]], align 4 309 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 310 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 311 // CHECK1-NEXT: [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 0 312 // CHECK1-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP5]], i32 0 313 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 314 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 315 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 316 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 317 // CHECK1: omp.inner.for.cond: 318 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 319 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 320 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 321 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 322 // CHECK1: omp.inner.for.body: 323 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 324 // CHECK1-NEXT: switch i32 [[TMP11]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 325 // CHECK1-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 326 // CHECK1-NEXT: ] 327 // CHECK1: .omp.sections.case: 328 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR]], align 4 329 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 330 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 331 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 332 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* 333 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* 334 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) 335 // CHECK1-NEXT: store i32 31, i32* [[SIVAR]], align 4 336 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 337 // CHECK1: .omp.sections.exit: 338 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 339 // CHECK1: omp.inner.for.inc: 340 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 341 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP15]], 1 342 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 343 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 344 // CHECK1: omp.inner.for.end: 345 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 346 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 347 // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 348 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 349 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 350 // CHECK1: arraydestroy.body: 351 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 352 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 353 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 354 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 355 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 356 // CHECK1: arraydestroy.done5: 357 // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 358 // CHECK1-NEXT: ret i32 [[CALL]] 359 // 360 // 361 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 362 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 363 // CHECK1-NEXT: entry: 364 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 365 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 366 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 367 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 368 // CHECK1-NEXT: ret void 369 // 370 // 371 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 372 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 373 // CHECK1-NEXT: entry: 374 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 375 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 376 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 377 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 378 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 379 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 380 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 381 // CHECK1-NEXT: ret void 382 // 383 // 384 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 385 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 386 // CHECK1-NEXT: entry: 387 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 388 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 389 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 390 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 391 // CHECK1-NEXT: ret void 392 // 393 // 394 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 395 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] { 396 // CHECK1-NEXT: entry: 397 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 398 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 399 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 400 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 401 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 402 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 403 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 404 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 405 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 406 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 407 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 408 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 409 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 410 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 411 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 412 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 413 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 414 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[TMP1]], align 8 415 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 416 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP2]], align 8 417 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 418 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP3]], align 8 419 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 420 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP4]], align 8 421 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.anon* [[OMP_OUTLINED_ARG_AGG_]]) 422 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 423 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 424 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 425 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 426 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 427 // CHECK1: arraydestroy.body: 428 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 429 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 430 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 431 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 432 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 433 // CHECK1: arraydestroy.done1: 434 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 435 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 436 // CHECK1-NEXT: ret i32 [[TMP6]] 437 // 438 // 439 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 440 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 441 // CHECK1-NEXT: entry: 442 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 443 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 444 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 445 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 446 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 447 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 448 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4 449 // CHECK1-NEXT: ret void 450 // 451 // 452 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 453 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 454 // CHECK1-NEXT: entry: 455 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 456 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 457 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 458 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 459 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 460 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 461 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 462 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 463 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 464 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 465 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 466 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 467 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 468 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 469 // CHECK1-NEXT: ret void 470 // 471 // 472 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 473 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 474 // CHECK1-NEXT: entry: 475 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 476 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 477 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 478 // CHECK1-NEXT: ret void 479 // 480 // 481 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 482 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 483 // CHECK1-NEXT: entry: 484 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 485 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 486 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 487 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 488 // CHECK1-NEXT: ret void 489 // 490 // 491 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 492 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 493 // CHECK1-NEXT: entry: 494 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 495 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 496 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 497 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 498 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 499 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 500 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 501 // CHECK1-NEXT: ret void 502 // 503 // 504 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 505 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR6:[0-9]+]] { 506 // CHECK1-NEXT: entry: 507 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 508 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 509 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 510 // CHECK1-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 511 // CHECK1-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 512 // CHECK1-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 513 // CHECK1-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 514 // CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 515 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 516 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 517 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 518 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 519 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 520 // CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4 521 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 522 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 523 // CHECK1-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 524 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 525 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 526 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 8 527 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP0]], i32 0, i32 1 528 // CHECK1-NEXT: [[TMP4:%.*]] = load [2 x i32]*, [2 x i32]** [[TMP3]], align 8 529 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP0]], i32 0, i32 2 530 // CHECK1-NEXT: [[TMP6:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[TMP5]], align 8 531 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP0]], i32 0, i32 3 532 // CHECK1-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP7]], align 8 533 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 534 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 535 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 536 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 537 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP2]], align 4 538 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[T_VAR]], align 4 539 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 540 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast [2 x i32]* [[TMP4]] to i8* 541 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 8, i1 false) 542 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 543 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast [2 x %struct.S.0]* [[TMP6]] to %struct.S.0* 544 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 545 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP13]] 546 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 547 // CHECK1: omp.arraycpy.body: 548 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 549 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 550 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 551 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 552 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 553 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 554 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 555 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP13]] 556 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] 557 // CHECK1: omp.arraycpy.done1: 558 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) 559 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP8]], %struct.St* [[AGG_TMP2]]) 560 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] 561 // CHECK1-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 562 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 563 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 564 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 565 // CHECK1-NEXT: [[TMP17:%.*]] = icmp slt i32 [[TMP16]], 1 566 // CHECK1-NEXT: [[TMP18:%.*]] = select i1 [[TMP17]], i32 [[TMP16]], i32 1 567 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 568 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 569 // CHECK1-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 570 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 571 // CHECK1: omp.inner.for.cond: 572 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 573 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 574 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] 575 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 576 // CHECK1: omp.inner.for.body: 577 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 578 // CHECK1-NEXT: switch i32 [[TMP22]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 579 // CHECK1-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 580 // CHECK1-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE3:%.*]] 581 // CHECK1-NEXT: ] 582 // CHECK1: .omp.sections.case: 583 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR]], align 4 584 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 585 // CHECK1-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 586 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 587 // CHECK1: .omp.sections.case3: 588 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 589 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 590 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 591 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 4, i1 false) 592 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 593 // CHECK1: .omp.sections.exit: 594 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 595 // CHECK1: omp.inner.for.inc: 596 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 597 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP26]], 1 598 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 599 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 600 // CHECK1: omp.inner.for.end: 601 // CHECK1-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 602 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 603 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) 604 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 605 // CHECK1-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 606 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN5]], i64 2 607 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 608 // CHECK1: arraydestroy.body: 609 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 610 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 611 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 612 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 613 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 614 // CHECK1: arraydestroy.done6: 615 // CHECK1-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 616 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 617 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP31]]) 618 // CHECK1-NEXT: ret void 619 // 620 // 621 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 622 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 623 // CHECK1-NEXT: entry: 624 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 625 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 626 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 627 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 628 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 629 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 630 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 631 // CHECK1-NEXT: ret void 632 // 633 // 634 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 635 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 636 // CHECK1-NEXT: entry: 637 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 638 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 639 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 640 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 641 // CHECK1-NEXT: ret void 642 // 643 // 644 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 645 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 646 // CHECK1-NEXT: entry: 647 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 648 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 649 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 650 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 651 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 652 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 653 // CHECK1-NEXT: ret void 654 // 655 // 656 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 657 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 658 // CHECK1-NEXT: entry: 659 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 660 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 661 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 662 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 663 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 664 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 665 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 666 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 667 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 668 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 669 // CHECK1-NEXT: ret void 670 // 671 // 672 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 673 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 674 // CHECK1-NEXT: entry: 675 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 676 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 677 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 678 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 679 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 680 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 681 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 682 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 683 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 684 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 685 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 686 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 687 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 688 // CHECK1-NEXT: ret void 689 // 690 // 691 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 692 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 693 // CHECK1-NEXT: entry: 694 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 695 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 696 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 697 // CHECK1-NEXT: ret void 698 // 699 // 700 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 701 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 702 // CHECK1-NEXT: entry: 703 // CHECK1-NEXT: call void @__cxx_global_var_init() 704 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 705 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 706 // CHECK1-NEXT: ret void 707 // 708 // 709 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init 710 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 711 // CHECK2-NEXT: entry: 712 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 713 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 714 // CHECK2-NEXT: ret void 715 // 716 // 717 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 718 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 719 // CHECK2-NEXT: entry: 720 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 721 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 722 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 723 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 724 // CHECK2-NEXT: ret void 725 // 726 // 727 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 728 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 729 // CHECK2-NEXT: entry: 730 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 731 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 732 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 733 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 734 // CHECK2-NEXT: ret void 735 // 736 // 737 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 738 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 739 // CHECK2-NEXT: entry: 740 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 741 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 742 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 743 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 744 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 745 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 746 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4 747 // CHECK2-NEXT: ret void 748 // 749 // 750 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 751 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 752 // CHECK2-NEXT: entry: 753 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 754 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 755 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 756 // CHECK2-NEXT: ret void 757 // 758 // 759 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 760 // CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 761 // CHECK2-NEXT: entry: 762 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 763 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 764 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 765 // CHECK2-NEXT: ret void 766 // 767 // 768 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 769 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 770 // CHECK2-NEXT: entry: 771 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 772 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 773 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 774 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 775 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 776 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 777 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 778 // CHECK2-NEXT: ret void 779 // 780 // 781 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 782 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 783 // CHECK2-NEXT: entry: 784 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 785 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 786 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 787 // CHECK2: arraydestroy.body: 788 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 789 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 790 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 791 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 792 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 793 // CHECK2: arraydestroy.done1: 794 // CHECK2-NEXT: ret void 795 // 796 // 797 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 798 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 799 // CHECK2-NEXT: entry: 800 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 801 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 802 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 803 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 804 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 805 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 806 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 807 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 808 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 809 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 810 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 811 // CHECK2-NEXT: ret void 812 // 813 // 814 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 815 // CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 816 // CHECK2-NEXT: entry: 817 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 818 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 819 // CHECK2-NEXT: ret void 820 // 821 // 822 // CHECK2-LABEL: define {{[^@]+}}@main 823 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 824 // CHECK2-NEXT: entry: 825 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 826 // CHECK2-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 827 // CHECK2-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 828 // CHECK2-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 829 // CHECK2-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 830 // CHECK2-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 831 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 832 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 833 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 834 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 835 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 836 // CHECK2-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4 837 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 838 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 839 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 840 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 841 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 842 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 843 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 844 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 845 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[T_VAR]], align 4 846 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 847 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 bitcast ([2 x i32]* @vec to i8*), i64 8, i1 false) 848 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 849 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 850 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP3]] 851 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 852 // CHECK2: omp.arraycpy.body: 853 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 854 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 855 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 856 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 857 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 858 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 859 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 860 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 861 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] 862 // CHECK2: omp.arraycpy.done1: 863 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) 864 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], %struct.S* nonnull align 4 dereferenceable(4) @var, %struct.St* [[AGG_TMP2]]) 865 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] 866 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 867 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[SIVAR]], align 4 868 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 869 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 870 // CHECK2-NEXT: [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 0 871 // CHECK2-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP5]], i32 0 872 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 873 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 874 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 875 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 876 // CHECK2: omp.inner.for.cond: 877 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 878 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 879 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 880 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 881 // CHECK2: omp.inner.for.body: 882 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 883 // CHECK2-NEXT: switch i32 [[TMP11]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 884 // CHECK2-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 885 // CHECK2-NEXT: ] 886 // CHECK2: .omp.sections.case: 887 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR]], align 4 888 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 889 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 890 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 891 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* 892 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* 893 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) 894 // CHECK2-NEXT: store i32 31, i32* [[SIVAR]], align 4 895 // CHECK2-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 896 // CHECK2: .omp.sections.exit: 897 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 898 // CHECK2: omp.inner.for.inc: 899 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 900 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP15]], 1 901 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 902 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 903 // CHECK2: omp.inner.for.end: 904 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 905 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 906 // CHECK2-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 907 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 908 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 909 // CHECK2: arraydestroy.body: 910 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 911 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 912 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 913 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 914 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 915 // CHECK2: arraydestroy.done5: 916 // CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 917 // CHECK2-NEXT: ret i32 [[CALL]] 918 // 919 // 920 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev 921 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 922 // CHECK2-NEXT: entry: 923 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 924 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 925 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 926 // CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 927 // CHECK2-NEXT: ret void 928 // 929 // 930 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 931 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 932 // CHECK2-NEXT: entry: 933 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 934 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 935 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 936 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 937 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 938 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 939 // CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 940 // CHECK2-NEXT: ret void 941 // 942 // 943 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev 944 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 945 // CHECK2-NEXT: entry: 946 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 947 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 948 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 949 // CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] 950 // CHECK2-NEXT: ret void 951 // 952 // 953 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 954 // CHECK2-SAME: () #[[ATTR5:[0-9]+]] { 955 // CHECK2-NEXT: entry: 956 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 957 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 958 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 959 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 960 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 961 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 962 // CHECK2-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 963 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 964 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 965 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 966 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 967 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 968 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 969 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 970 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 971 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 972 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 973 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[TMP1]], align 8 974 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 975 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP2]], align 8 976 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 977 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP3]], align 8 978 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 979 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[TMP4]], align 8 980 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.anon* [[OMP_OUTLINED_ARG_AGG_]]) 981 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 982 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 983 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 984 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 985 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 986 // CHECK2: arraydestroy.body: 987 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 988 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 989 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 990 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 991 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 992 // CHECK2: arraydestroy.done1: 993 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] 994 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[RETVAL]], align 4 995 // CHECK2-NEXT: ret i32 [[TMP6]] 996 // 997 // 998 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev 999 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1000 // CHECK2-NEXT: entry: 1001 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1002 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1003 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1004 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 1005 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1006 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 1007 // CHECK2-NEXT: store i32 0, i32* [[B]], align 4 1008 // CHECK2-NEXT: ret void 1009 // 1010 // 1011 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1012 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1013 // CHECK2-NEXT: entry: 1014 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1015 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 1016 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1017 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 1018 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1019 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1020 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 1021 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 1022 // CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 1023 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1024 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1025 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1026 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1027 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 1028 // CHECK2-NEXT: ret void 1029 // 1030 // 1031 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1032 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1033 // CHECK2-NEXT: entry: 1034 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 1035 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 1036 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 1037 // CHECK2-NEXT: ret void 1038 // 1039 // 1040 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1041 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1042 // CHECK2-NEXT: entry: 1043 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1044 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1045 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1046 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1047 // CHECK2-NEXT: ret void 1048 // 1049 // 1050 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1051 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1052 // CHECK2-NEXT: entry: 1053 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1054 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1055 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1056 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1057 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1058 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1059 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 1060 // CHECK2-NEXT: ret void 1061 // 1062 // 1063 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1064 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR6:[0-9]+]] { 1065 // CHECK2-NEXT: entry: 1066 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1067 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1068 // CHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 1069 // CHECK2-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 1070 // CHECK2-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 1071 // CHECK2-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 1072 // CHECK2-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 1073 // CHECK2-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 1074 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1075 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1076 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1077 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1078 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1079 // CHECK2-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4 1080 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1081 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1082 // CHECK2-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 1083 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 1084 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 1085 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 8 1086 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP0]], i32 0, i32 1 1087 // CHECK2-NEXT: [[TMP4:%.*]] = load [2 x i32]*, [2 x i32]** [[TMP3]], align 8 1088 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP0]], i32 0, i32 2 1089 // CHECK2-NEXT: [[TMP6:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[TMP5]], align 8 1090 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP0]], i32 0, i32 3 1091 // CHECK2-NEXT: [[TMP8:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP7]], align 8 1092 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 1093 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1094 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 1095 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 1096 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP2]], align 4 1097 // CHECK2-NEXT: store i32 [[TMP9]], i32* [[T_VAR]], align 4 1098 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1099 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast [2 x i32]* [[TMP4]] to i8* 1100 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 8, i1 false) 1101 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1102 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast [2 x %struct.S.0]* [[TMP6]] to %struct.S.0* 1103 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1104 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP13]] 1105 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1106 // CHECK2: omp.arraycpy.body: 1107 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1108 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1109 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1110 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1111 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1112 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1113 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1114 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP13]] 1115 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] 1116 // CHECK2: omp.arraycpy.done1: 1117 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) 1118 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP8]], %struct.St* [[AGG_TMP2]]) 1119 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] 1120 // CHECK2-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1121 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 1122 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP15]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 1123 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1124 // CHECK2-NEXT: [[TMP17:%.*]] = icmp slt i32 [[TMP16]], 1 1125 // CHECK2-NEXT: [[TMP18:%.*]] = select i1 [[TMP17]], i32 [[TMP16]], i32 1 1126 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 1127 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 1128 // CHECK2-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 1129 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1130 // CHECK2: omp.inner.for.cond: 1131 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1132 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1133 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] 1134 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1135 // CHECK2: omp.inner.for.body: 1136 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1137 // CHECK2-NEXT: switch i32 [[TMP22]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 1138 // CHECK2-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 1139 // CHECK2-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE3:%.*]] 1140 // CHECK2-NEXT: ] 1141 // CHECK2: .omp.sections.case: 1142 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR]], align 4 1143 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 1144 // CHECK2-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 1145 // CHECK2-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1146 // CHECK2: .omp.sections.case3: 1147 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1148 // CHECK2-NEXT: [[TMP24:%.*]] = bitcast %struct.S.0* [[ARRAYIDX4]] to i8* 1149 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 1150 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP24]], i8* align 4 [[TMP25]], i64 4, i1 false) 1151 // CHECK2-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1152 // CHECK2: .omp.sections.exit: 1153 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1154 // CHECK2: omp.inner.for.inc: 1155 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1156 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP26]], 1 1157 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 1158 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1159 // CHECK2: omp.inner.for.end: 1160 // CHECK2-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1161 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[TMP27]], align 4 1162 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP28]]) 1163 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] 1164 // CHECK2-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1165 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN5]], i64 2 1166 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1167 // CHECK2: arraydestroy.body: 1168 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP29]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1169 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1170 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1171 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] 1172 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] 1173 // CHECK2: arraydestroy.done6: 1174 // CHECK2-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1175 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 1176 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP31]]) 1177 // CHECK2-NEXT: ret void 1178 // 1179 // 1180 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1181 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1182 // CHECK2-NEXT: entry: 1183 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1184 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1185 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1186 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1187 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1188 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1189 // CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1190 // CHECK2-NEXT: ret void 1191 // 1192 // 1193 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1194 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1195 // CHECK2-NEXT: entry: 1196 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1197 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1198 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1199 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1200 // CHECK2-NEXT: ret void 1201 // 1202 // 1203 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1204 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1205 // CHECK2-NEXT: entry: 1206 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1207 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1208 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1209 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1210 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1211 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1212 // CHECK2-NEXT: ret void 1213 // 1214 // 1215 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1216 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1217 // CHECK2-NEXT: entry: 1218 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1219 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1220 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1221 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1222 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1223 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1224 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1225 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1226 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1227 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1228 // CHECK2-NEXT: ret void 1229 // 1230 // 1231 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1232 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1233 // CHECK2-NEXT: entry: 1234 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1235 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1236 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1237 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1238 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1239 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1240 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1241 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1242 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1243 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1244 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1245 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1246 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1247 // CHECK2-NEXT: ret void 1248 // 1249 // 1250 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1251 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1252 // CHECK2-NEXT: entry: 1253 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1254 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1255 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1256 // CHECK2-NEXT: ret void 1257 // 1258 // 1259 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 1260 // CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1261 // CHECK2-NEXT: entry: 1262 // CHECK2-NEXT: call void @__cxx_global_var_init() 1263 // CHECK2-NEXT: call void @__cxx_global_var_init.1() 1264 // CHECK2-NEXT: call void @__cxx_global_var_init.2() 1265 // CHECK2-NEXT: ret void 1266 // 1267 // 1268 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 1269 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1270 // CHECK3-NEXT: entry: 1271 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 1272 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1273 // CHECK3-NEXT: ret void 1274 // 1275 // 1276 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1277 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 1278 // CHECK3-NEXT: entry: 1279 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1280 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1281 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1282 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1283 // CHECK3-NEXT: ret void 1284 // 1285 // 1286 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1287 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1288 // CHECK3-NEXT: entry: 1289 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1290 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1291 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1292 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1293 // CHECK3-NEXT: ret void 1294 // 1295 // 1296 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1297 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1298 // CHECK3-NEXT: entry: 1299 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1300 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1301 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1302 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1303 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1304 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1305 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 1306 // CHECK3-NEXT: ret void 1307 // 1308 // 1309 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1310 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1311 // CHECK3-NEXT: entry: 1312 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1313 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1314 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1315 // CHECK3-NEXT: ret void 1316 // 1317 // 1318 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1319 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1320 // CHECK3-NEXT: entry: 1321 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 1322 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 1323 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1324 // CHECK3-NEXT: ret void 1325 // 1326 // 1327 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1328 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1329 // CHECK3-NEXT: entry: 1330 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1331 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1332 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1333 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1334 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1335 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1336 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1337 // CHECK3-NEXT: ret void 1338 // 1339 // 1340 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1341 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1342 // CHECK3-NEXT: entry: 1343 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1344 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1345 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1346 // CHECK3: arraydestroy.body: 1347 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1348 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1349 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1350 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1351 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1352 // CHECK3: arraydestroy.done1: 1353 // CHECK3-NEXT: ret void 1354 // 1355 // 1356 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1357 // CHECK3-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1358 // CHECK3-NEXT: entry: 1359 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1360 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1361 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1362 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1363 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1364 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1365 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1366 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1367 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1368 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1369 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 1370 // CHECK3-NEXT: ret void 1371 // 1372 // 1373 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1374 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1375 // CHECK3-NEXT: entry: 1376 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 1377 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1378 // CHECK3-NEXT: ret void 1379 // 1380 // 1381 // CHECK3-LABEL: define {{[^@]+}}@main 1382 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1383 // CHECK3-NEXT: entry: 1384 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1385 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 1386 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1387 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 1388 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 1389 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) 1390 // CHECK3-NEXT: ret i32 0 1391 // 1392 // 1393 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1394 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR5:[0-9]+]] { 1395 // CHECK3-NEXT: entry: 1396 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1397 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1398 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 1399 // CHECK3-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 1400 // CHECK3-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 1401 // CHECK3-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 1402 // CHECK3-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 1403 // CHECK3-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 1404 // CHECK3-NEXT: [[G:%.*]] = alloca i32, align 4 1405 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1406 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1407 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1408 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1409 // CHECK3-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 1410 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 1411 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 1412 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 8 1413 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 1414 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1415 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 1416 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 1417 // CHECK3-NEXT: [[TMP3:%.*]] = load volatile i32, i32* @g, align 4 1418 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[G]], align 4 1419 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4 1420 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[SIVAR]], align 4 1421 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1422 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 1423 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 1424 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1425 // CHECK3-NEXT: [[TMP8:%.*]] = icmp slt i32 [[TMP7]], 1 1426 // CHECK3-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i32 [[TMP7]], i32 1 1427 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 1428 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 1429 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 1430 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1431 // CHECK3: omp.inner.for.cond: 1432 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1433 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1434 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 1435 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1436 // CHECK3: omp.inner.for.body: 1437 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1438 // CHECK3-NEXT: switch i32 [[TMP13]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 1439 // CHECK3-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 1440 // CHECK3-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE1:%.*]] 1441 // CHECK3-NEXT: ] 1442 // CHECK3: .omp.sections.case: 1443 // CHECK3-NEXT: store i32 1, i32* [[G]], align 4 1444 // CHECK3-NEXT: store i32 10, i32* [[SIVAR]], align 4 1445 // CHECK3-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1446 // CHECK3: .omp.sections.case1: 1447 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 1448 // CHECK3-NEXT: store i32* [[G]], i32** [[TMP14]], align 8 1449 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 1450 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[TMP15]], align 8 1451 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(16) [[REF_TMP]]) 1452 // CHECK3-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1453 // CHECK3: .omp.sections.exit: 1454 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1455 // CHECK3: omp.inner.for.inc: 1456 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1457 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP16]], 1 1458 // CHECK3-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 1459 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1460 // CHECK3: omp.inner.for.end: 1461 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 1462 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]]) 1463 // CHECK3-NEXT: ret void 1464 // 1465 // 1466 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 1467 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1468 // CHECK3-NEXT: entry: 1469 // CHECK3-NEXT: call void @__cxx_global_var_init() 1470 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1471 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1472 // CHECK3-NEXT: ret void 1473 // 1474 // 1475 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init 1476 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1477 // CHECK4-NEXT: entry: 1478 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) @test) 1479 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1480 // CHECK4-NEXT: ret void 1481 // 1482 // 1483 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1484 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 1485 // CHECK4-NEXT: entry: 1486 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1487 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1488 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1489 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1490 // CHECK4-NEXT: ret void 1491 // 1492 // 1493 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1494 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1495 // CHECK4-NEXT: entry: 1496 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1497 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1498 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1499 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1500 // CHECK4-NEXT: ret void 1501 // 1502 // 1503 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1504 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1505 // CHECK4-NEXT: entry: 1506 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1507 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1508 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1509 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1510 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1511 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1512 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4 1513 // CHECK4-NEXT: ret void 1514 // 1515 // 1516 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1517 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1518 // CHECK4-NEXT: entry: 1519 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1520 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1521 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1522 // CHECK4-NEXT: ret void 1523 // 1524 // 1525 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1526 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1527 // CHECK4-NEXT: entry: 1528 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 1529 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 1530 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1531 // CHECK4-NEXT: ret void 1532 // 1533 // 1534 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1535 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1536 // CHECK4-NEXT: entry: 1537 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1538 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1539 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1540 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1541 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1542 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1543 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1544 // CHECK4-NEXT: ret void 1545 // 1546 // 1547 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1548 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1549 // CHECK4-NEXT: entry: 1550 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1551 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1552 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1553 // CHECK4: arraydestroy.body: 1554 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1555 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1556 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1557 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1558 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1559 // CHECK4: arraydestroy.done1: 1560 // CHECK4-NEXT: ret void 1561 // 1562 // 1563 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1564 // CHECK4-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1565 // CHECK4-NEXT: entry: 1566 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1567 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1568 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1569 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1570 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1571 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1572 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1573 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1574 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1575 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1576 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 1577 // CHECK4-NEXT: ret void 1578 // 1579 // 1580 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1581 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1582 // CHECK4-NEXT: entry: 1583 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @var, float 3.000000e+00) 1584 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1585 // CHECK4-NEXT: ret void 1586 // 1587 // 1588 // CHECK4-LABEL: define {{[^@]+}}@main 1589 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 1590 // CHECK4-NEXT: entry: 1591 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1592 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 1593 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 1594 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 1595 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 1596 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 1597 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 1598 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 1599 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 1600 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 1601 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 1602 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 1603 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 1604 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 1605 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1606 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 1607 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* 1608 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* 1609 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 1610 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 1611 // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 1612 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* 1613 // CHECK4-NEXT: call void [[TMP5]](i8* [[TMP3]]) 1614 // CHECK4-NEXT: ret i32 0 1615 // 1616 // 1617 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke 1618 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 1619 // CHECK4-NEXT: entry: 1620 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 1621 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 1622 // CHECK4-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 1623 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 1624 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* 1625 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 1626 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 1627 // CHECK4-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 1628 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.anon* [[OMP_OUTLINED_ARG_AGG_]]) 1629 // CHECK4-NEXT: ret void 1630 // 1631 // 1632 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 1633 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR4:[0-9]+]] { 1634 // CHECK4-NEXT: entry: 1635 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1636 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1637 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 1638 // CHECK4-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 1639 // CHECK4-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 1640 // CHECK4-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 1641 // CHECK4-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 1642 // CHECK4-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 1643 // CHECK4-NEXT: [[G:%.*]] = alloca i32, align 4 1644 // CHECK4-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 1645 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, align 8 1646 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1647 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1648 // CHECK4-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 1649 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 1650 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 1651 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 8 1652 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 1653 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1654 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 1655 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 1656 // CHECK4-NEXT: [[TMP3:%.*]] = load volatile i32, i32* @g, align 4 1657 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[G]], align 4 1658 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4 1659 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[SIVAR]], align 4 1660 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1661 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 1662 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 1663 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1664 // CHECK4-NEXT: [[TMP8:%.*]] = icmp slt i32 [[TMP7]], 1 1665 // CHECK4-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i32 [[TMP7]], i32 1 1666 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 1667 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 1668 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 1669 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1670 // CHECK4: omp.inner.for.cond: 1671 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1672 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1673 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 1674 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1675 // CHECK4: omp.inner.for.body: 1676 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1677 // CHECK4-NEXT: switch i32 [[TMP13]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 1678 // CHECK4-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 1679 // CHECK4-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE1:%.*]] 1680 // CHECK4-NEXT: ] 1681 // CHECK4: .omp.sections.case: 1682 // CHECK4-NEXT: store i32 1, i32* [[G]], align 4 1683 // CHECK4-NEXT: store i32 10, i32* [[SIVAR]], align 4 1684 // CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1685 // CHECK4: .omp.sections.case1: 1686 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 0 1687 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 1688 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 1 1689 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 1690 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 2 1691 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 1692 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 3 1693 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @var_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 1694 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 4 1695 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 1696 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 1697 // CHECK4-NEXT: [[TMP14:%.*]] = load volatile i32, i32* [[G]], align 4 1698 // CHECK4-NEXT: store volatile i32 [[TMP14]], i32* [[BLOCK_CAPTURED]], align 8 1699 // CHECK4-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 1700 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[SIVAR]], align 4 1701 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[BLOCK_CAPTURED2]], align 4 1702 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]] to void ()* 1703 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP16]] to %struct.__block_literal_generic* 1704 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 1705 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 1706 // CHECK4-NEXT: [[TMP19:%.*]] = load i8*, i8** [[TMP17]], align 8 1707 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8* [[TMP19]] to void (i8*)* 1708 // CHECK4-NEXT: call void [[TMP20]](i8* [[TMP18]]) 1709 // CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1710 // CHECK4: .omp.sections.exit: 1711 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1712 // CHECK4: omp.inner.for.inc: 1713 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1714 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP21]], 1 1715 // CHECK4-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 1716 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 1717 // CHECK4: omp.inner.for.end: 1718 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]]) 1719 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP6]]) 1720 // CHECK4-NEXT: ret void 1721 // 1722 // 1723 // CHECK4-LABEL: define {{[^@]+}}@var_block_invoke 1724 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 1725 // CHECK4-NEXT: entry: 1726 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 1727 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 1728 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 1729 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* 1730 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>** [[BLOCK_ADDR]], align 8 1731 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 1732 // CHECK4-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 1733 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 1734 // CHECK4-NEXT: store i32 20, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 1735 // CHECK4-NEXT: ret void 1736 // 1737 // 1738 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 1739 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1740 // CHECK4-NEXT: entry: 1741 // CHECK4-NEXT: call void @__cxx_global_var_init() 1742 // CHECK4-NEXT: call void @__cxx_global_var_init.1() 1743 // CHECK4-NEXT: call void @__cxx_global_var_init.2() 1744 // CHECK4-NEXT: ret void 1745 // 1746