1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-function-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 7 8 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s 10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 11 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 13 // expected-no-diagnostics 14 #ifndef HEADER 15 #define HEADER 16 17 struct St { 18 int a, b; 19 St() : a(0), b(0) {} 20 St(const St &st) : a(st.a + st.b), b(0) {} 21 ~St() {} 22 }; 23 24 volatile int g = 1212; 25 26 template <class T> 27 struct S { 28 T f; 29 S(T a) : f(a + g) {} 30 S() : f(g) {} 31 S(const S &s, St t = St()) : f(s.f + t.a) {} 32 operator T() { return T(); } 33 ~S() {} 34 }; 35 36 37 template <typename T> 38 T tmain() { 39 S<T> test; 40 T t_var = T(); 41 T vec[] = {1, 2}; 42 S<T> s_arr[] = {1, 2}; 43 S<T> var(3); 44 #pragma omp parallel 45 #pragma omp sections firstprivate(t_var, vec, s_arr, var) 46 { 47 vec[0] = t_var; 48 #pragma omp section 49 s_arr[0] = var; 50 } 51 return T(); 52 } 53 54 S<float> test; 55 int t_var = 333; 56 int vec[] = {1, 2}; 57 S<float> s_arr[] = {1, 2}; 58 S<float> var(3); 59 60 int main() { 61 static int sivar; 62 #ifdef LAMBDA 63 [&]() { 64 #pragma omp parallel 65 #pragma omp sections firstprivate(g, sivar) 66 { 67 // Skip temp vars for loop 68 69 70 71 { 72 g = 1; 73 sivar = 10; 74 } 75 #pragma omp section 76 [&]() { 77 g = 2; 78 sivar = 20; 79 }(); 80 } 81 }(); 82 return 0; 83 #elif defined(BLOCKS) 84 ^{ 85 #pragma omp parallel 86 #pragma omp sections firstprivate(g, sivar) 87 { 88 // Skip temp vars for loop 89 90 91 92 { 93 g = 1; 94 sivar = 10; 95 } 96 #pragma omp section 97 ^{ 98 g = 2; 99 sivar = 20; 100 }(); 101 } 102 }(); 103 return 0; 104 #else 105 #pragma omp sections firstprivate(t_var, vec, s_arr, var, sivar) nowait 106 { 107 { 108 vec[0] = t_var; 109 s_arr[0] = var; 110 sivar = 31; 111 } 112 } 113 return tmain<int>(); 114 #endif 115 } 116 117 118 // firstprivate t_var(t_var) 119 120 // firstprivate vec(vec) 121 122 // firstprivate s_arr(s_arr) 123 124 // firstprivate var(var) 125 126 // firstprivate isvar 127 128 129 // ~(firstprivate var), ~(firstprivate s_arr) 130 131 132 133 // Skip temp vars for loop 134 135 136 // firstprivate t_var(t_var) 137 138 // firstprivate vec(vec) 139 140 // firstprivate s_arr(s_arr) 141 142 // firstprivate var(var) 143 144 // No synchronization for initialization. 145 146 147 // ~(firstprivate var), ~(firstprivate s_arr) 148 #endif 149 150 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init 151 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 152 // CHECK1-NEXT: entry: 153 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) 154 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 155 // CHECK1-NEXT: ret void 156 // 157 // 158 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 159 // CHECK1-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 160 // CHECK1-NEXT: entry: 161 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 162 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 163 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 164 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) 165 // CHECK1-NEXT: ret void 166 // 167 // 168 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 169 // CHECK1-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 170 // CHECK1-NEXT: entry: 171 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 172 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 173 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 174 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] 175 // CHECK1-NEXT: ret void 176 // 177 // 178 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 179 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 180 // CHECK1-NEXT: entry: 181 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 182 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 183 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 184 // CHECK1-NEXT: ret void 185 // 186 // 187 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 188 // CHECK1-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 189 // CHECK1-NEXT: entry: 190 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 191 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 192 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 193 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 194 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 195 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 196 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) 197 // CHECK1-NEXT: ret void 198 // 199 // 200 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 201 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 202 // CHECK1-NEXT: entry: 203 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 204 // CHECK1-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 205 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 206 // CHECK1: arraydestroy.body: 207 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 208 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 209 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 210 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 211 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 212 // CHECK1: arraydestroy.done1: 213 // CHECK1-NEXT: ret void 214 // 215 // 216 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 217 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 218 // CHECK1-NEXT: entry: 219 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) 220 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 221 // CHECK1-NEXT: ret void 222 // 223 // 224 // CHECK1-LABEL: define {{[^@]+}}@main 225 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 226 // CHECK1-NEXT: entry: 227 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 228 // CHECK1-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 229 // CHECK1-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 230 // CHECK1-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 231 // CHECK1-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 232 // CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 233 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 234 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 235 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 236 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 237 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 238 // CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4 239 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 240 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 241 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 242 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 243 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 244 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 245 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 246 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 247 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[T_VAR]], align 4 248 // CHECK1-NEXT: [[TMP2:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 249 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 bitcast ([2 x i32]* @vec to i8*), i64 8, i1 false) 250 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 251 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 252 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP3]] 253 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 254 // CHECK1: omp.arraycpy.body: 255 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 256 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 257 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) 258 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 259 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 260 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 261 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 262 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 263 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] 264 // CHECK1: omp.arraycpy.done1: 265 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP2]]) 266 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR]], %struct.S* nonnull align 4 dereferenceable(4) @var, %struct.St* [[AGG_TMP2]]) 267 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] 268 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 269 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[SIVAR]], align 4 270 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 271 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 272 // CHECK1-NEXT: [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 0 273 // CHECK1-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP5]], i32 0 274 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 275 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 276 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 277 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 278 // CHECK1: omp.inner.for.cond: 279 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 280 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 281 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 282 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 283 // CHECK1: omp.inner.for.body: 284 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 285 // CHECK1-NEXT: switch i32 [[TMP11]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 286 // CHECK1-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 287 // CHECK1-NEXT: ] 288 // CHECK1: .omp.sections.case: 289 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR]], align 4 290 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 291 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 292 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 293 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* 294 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* 295 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) 296 // CHECK1-NEXT: store i32 31, i32* [[SIVAR]], align 4 297 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 298 // CHECK1: .omp.sections.exit: 299 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 300 // CHECK1: omp.inner.for.inc: 301 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 302 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP15]], 1 303 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 304 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 305 // CHECK1: omp.inner.for.end: 306 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 307 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] 308 // CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 309 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 310 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 311 // CHECK1: arraydestroy.body: 312 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 313 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 314 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 315 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 316 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 317 // CHECK1: arraydestroy.done5: 318 // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 319 // CHECK1-NEXT: ret i32 [[CALL]] 320 // 321 // 322 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 323 // CHECK1-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 324 // CHECK1-NEXT: entry: 325 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 326 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 327 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 328 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) 329 // CHECK1-NEXT: ret void 330 // 331 // 332 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 333 // CHECK1-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 334 // CHECK1-NEXT: entry: 335 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 336 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 337 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 338 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 339 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 340 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 341 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 342 // CHECK1-NEXT: ret void 343 // 344 // 345 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 346 // CHECK1-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 347 // CHECK1-NEXT: entry: 348 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 349 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 350 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 351 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR2]] 352 // CHECK1-NEXT: ret void 353 // 354 // 355 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 356 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] { 357 // CHECK1-NEXT: entry: 358 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 359 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 360 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 361 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 362 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 363 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 364 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) 365 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 366 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 367 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 368 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 369 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 370 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 371 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 372 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) 373 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) 374 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 375 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] 376 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 377 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 378 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 379 // CHECK1: arraydestroy.body: 380 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 381 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 382 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 383 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 384 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 385 // CHECK1: arraydestroy.done1: 386 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] 387 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 388 // CHECK1-NEXT: ret i32 [[TMP2]] 389 // 390 // 391 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 392 // CHECK1-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 393 // CHECK1-NEXT: entry: 394 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 395 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 396 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 397 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 398 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 399 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 400 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4 401 // CHECK1-NEXT: ret void 402 // 403 // 404 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 405 // CHECK1-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 406 // CHECK1-NEXT: entry: 407 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 408 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 409 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 410 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 411 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 412 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 413 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 414 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 415 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 416 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 417 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 418 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 419 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 420 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 421 // CHECK1-NEXT: ret void 422 // 423 // 424 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 425 // CHECK1-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 426 // CHECK1-NEXT: entry: 427 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 428 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 429 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 430 // CHECK1-NEXT: ret void 431 // 432 // 433 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 434 // CHECK1-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 435 // CHECK1-NEXT: entry: 436 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 437 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 438 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 439 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) 440 // CHECK1-NEXT: ret void 441 // 442 // 443 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 444 // CHECK1-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 445 // CHECK1-NEXT: entry: 446 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 447 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 448 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 449 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 450 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 451 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 452 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 453 // CHECK1-NEXT: ret void 454 // 455 // 456 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 457 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR6:[0-9]+]] { 458 // CHECK1-NEXT: entry: 459 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 460 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 461 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 462 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 463 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 464 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 465 // CHECK1-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 466 // CHECK1-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 467 // CHECK1-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 468 // CHECK1-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 469 // CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 470 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 471 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 472 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 473 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 474 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 475 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 476 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 477 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 478 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 479 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 480 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 481 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 482 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 483 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 484 // CHECK1-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 485 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 486 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 487 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 488 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 489 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 490 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 491 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 4 492 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 493 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* 494 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) 495 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 496 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 497 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 498 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 499 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 500 // CHECK1: omp.arraycpy.body: 501 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 502 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 503 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) 504 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 505 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 506 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 507 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 508 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 509 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 510 // CHECK1: omp.arraycpy.done4: 511 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) 512 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 513 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 514 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 515 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 516 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 517 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 518 // CHECK1-NEXT: [[TMP12:%.*]] = icmp slt i32 [[TMP11]], 1 519 // CHECK1-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP11]], i32 1 520 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 521 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 522 // CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 523 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 524 // CHECK1: omp.inner.for.cond: 525 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 526 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 527 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 528 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 529 // CHECK1: omp.inner.for.body: 530 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 531 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 532 // CHECK1-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 533 // CHECK1-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE7:%.*]] 534 // CHECK1-NEXT: ] 535 // CHECK1: .omp.sections.case: 536 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR1]], align 4 537 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 538 // CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 539 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 540 // CHECK1: .omp.sections.case7: 541 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 542 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* 543 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 544 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) 545 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 546 // CHECK1: .omp.sections.exit: 547 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 548 // CHECK1: omp.inner.for.inc: 549 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 550 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP21]], 1 551 // CHECK1-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 552 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 553 // CHECK1: omp.inner.for.end: 554 // CHECK1-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 555 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 556 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 557 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR2]] 558 // CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 559 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 560 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 561 // CHECK1: arraydestroy.body: 562 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 563 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 564 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 565 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 566 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 567 // CHECK1: arraydestroy.done10: 568 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 569 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 570 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP26]]) 571 // CHECK1-NEXT: ret void 572 // 573 // 574 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 575 // CHECK1-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 576 // CHECK1-NEXT: entry: 577 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 578 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 579 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 580 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 581 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 582 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 583 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 584 // CHECK1-NEXT: ret void 585 // 586 // 587 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 588 // CHECK1-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 589 // CHECK1-NEXT: entry: 590 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 591 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 592 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 593 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] 594 // CHECK1-NEXT: ret void 595 // 596 // 597 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 598 // CHECK1-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 599 // CHECK1-NEXT: entry: 600 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 601 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 602 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 603 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 604 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 605 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 606 // CHECK1-NEXT: ret void 607 // 608 // 609 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 610 // CHECK1-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 611 // CHECK1-NEXT: entry: 612 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 613 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 614 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 615 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 616 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 617 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 618 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 619 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 620 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 621 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 622 // CHECK1-NEXT: ret void 623 // 624 // 625 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 626 // CHECK1-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 627 // CHECK1-NEXT: entry: 628 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 629 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 630 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 631 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 632 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 633 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 634 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 635 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 636 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 637 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 638 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 639 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 640 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 641 // CHECK1-NEXT: ret void 642 // 643 // 644 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 645 // CHECK1-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 646 // CHECK1-NEXT: entry: 647 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 648 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 649 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 650 // CHECK1-NEXT: ret void 651 // 652 // 653 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 654 // CHECK1-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 655 // CHECK1-NEXT: entry: 656 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 657 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 658 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 659 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 660 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 661 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 662 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 663 // CHECK1-NEXT: ret void 664 // 665 // 666 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 667 // CHECK1-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 668 // CHECK1-NEXT: entry: 669 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 670 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 671 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 672 // CHECK1-NEXT: ret void 673 // 674 // 675 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 676 // CHECK1-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 677 // CHECK1-NEXT: entry: 678 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 679 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 680 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 681 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 682 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 683 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 684 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 685 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 686 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 687 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 688 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 689 // CHECK1-NEXT: ret void 690 // 691 // 692 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 693 // CHECK1-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 694 // CHECK1-NEXT: entry: 695 // CHECK1-NEXT: call void @__cxx_global_var_init() 696 // CHECK1-NEXT: call void @__cxx_global_var_init.1() 697 // CHECK1-NEXT: call void @__cxx_global_var_init.2() 698 // CHECK1-NEXT: ret void 699 // 700 // 701 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init 702 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 703 // CHECK2-NEXT: entry: 704 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) 705 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 706 // CHECK2-NEXT: ret void 707 // 708 // 709 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 710 // CHECK2-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 711 // CHECK2-NEXT: entry: 712 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 713 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 714 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 715 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) 716 // CHECK2-NEXT: ret void 717 // 718 // 719 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 720 // CHECK2-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 721 // CHECK2-NEXT: entry: 722 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 723 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 724 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 725 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] 726 // CHECK2-NEXT: ret void 727 // 728 // 729 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 730 // CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 731 // CHECK2-NEXT: entry: 732 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 733 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 734 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 735 // CHECK2-NEXT: ret void 736 // 737 // 738 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 739 // CHECK2-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 740 // CHECK2-NEXT: entry: 741 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 742 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 743 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 744 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 745 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 746 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 747 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) 748 // CHECK2-NEXT: ret void 749 // 750 // 751 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 752 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 753 // CHECK2-NEXT: entry: 754 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 755 // CHECK2-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 756 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 757 // CHECK2: arraydestroy.body: 758 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 759 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 760 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 761 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 762 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 763 // CHECK2: arraydestroy.done1: 764 // CHECK2-NEXT: ret void 765 // 766 // 767 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 768 // CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 769 // CHECK2-NEXT: entry: 770 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) 771 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 772 // CHECK2-NEXT: ret void 773 // 774 // 775 // CHECK2-LABEL: define {{[^@]+}}@main 776 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 777 // CHECK2-NEXT: entry: 778 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 779 // CHECK2-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 780 // CHECK2-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 781 // CHECK2-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 782 // CHECK2-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 783 // CHECK2-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 784 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 785 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 786 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 787 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 788 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 789 // CHECK2-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4 790 // CHECK2-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 791 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 792 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 793 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 794 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_UB_]], align 4 795 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 796 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 797 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* @t_var, align 4 798 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[T_VAR]], align 4 799 // CHECK2-NEXT: [[TMP2:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 800 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 bitcast ([2 x i32]* @vec to i8*), i64 8, i1 false) 801 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 802 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 803 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP3]] 804 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 805 // CHECK2: omp.arraycpy.body: 806 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 807 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 808 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) 809 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 810 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 811 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 812 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 813 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] 814 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] 815 // CHECK2: omp.arraycpy.done1: 816 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP2]]) 817 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[VAR]], %struct.S* nonnull align 4 dereferenceable(4) @var, %struct.St* [[AGG_TMP2]]) 818 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] 819 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 820 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[SIVAR]], align 4 821 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 822 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 823 // CHECK2-NEXT: [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 0 824 // CHECK2-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP5]], i32 0 825 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 826 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 827 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 828 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 829 // CHECK2: omp.inner.for.cond: 830 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 831 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 832 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 833 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 834 // CHECK2: omp.inner.for.body: 835 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 836 // CHECK2-NEXT: switch i32 [[TMP11]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 837 // CHECK2-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 838 // CHECK2-NEXT: ] 839 // CHECK2: .omp.sections.case: 840 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[T_VAR]], align 4 841 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 842 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX]], align 4 843 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 844 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast %struct.S* [[ARRAYIDX3]] to i8* 845 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR]] to i8* 846 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) 847 // CHECK2-NEXT: store i32 31, i32* [[SIVAR]], align 4 848 // CHECK2-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 849 // CHECK2: .omp.sections.exit: 850 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 851 // CHECK2: omp.inner.for.inc: 852 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 853 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP15]], 1 854 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 855 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 856 // CHECK2: omp.inner.for.end: 857 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 858 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] 859 // CHECK2-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 860 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN4]], i64 2 861 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 862 // CHECK2: arraydestroy.body: 863 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP16]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 864 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 865 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 866 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] 867 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] 868 // CHECK2: arraydestroy.done5: 869 // CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 870 // CHECK2-NEXT: ret i32 [[CALL]] 871 // 872 // 873 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev 874 // CHECK2-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 875 // CHECK2-NEXT: entry: 876 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 877 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 878 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 879 // CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) 880 // CHECK2-NEXT: ret void 881 // 882 // 883 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 884 // CHECK2-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 885 // CHECK2-NEXT: entry: 886 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 887 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 888 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 889 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 890 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 891 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 892 // CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 893 // CHECK2-NEXT: ret void 894 // 895 // 896 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev 897 // CHECK2-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 898 // CHECK2-NEXT: entry: 899 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 900 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 901 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 902 // CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull dereferenceable(8) [[THIS1]]) #[[ATTR2]] 903 // CHECK2-NEXT: ret void 904 // 905 // 906 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 907 // CHECK2-SAME: () #[[ATTR5:[0-9]+]] { 908 // CHECK2-NEXT: entry: 909 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 910 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 911 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 912 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 913 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 914 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 915 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) 916 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 917 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 918 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 919 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 920 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 921 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 922 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 923 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) 924 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) 925 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 926 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] 927 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 928 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 929 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 930 // CHECK2: arraydestroy.body: 931 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 932 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 933 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 934 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 935 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 936 // CHECK2: arraydestroy.done1: 937 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] 938 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 939 // CHECK2-NEXT: ret i32 [[TMP2]] 940 // 941 // 942 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev 943 // CHECK2-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 944 // CHECK2-NEXT: entry: 945 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 946 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 947 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 948 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 949 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 950 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 951 // CHECK2-NEXT: store i32 0, i32* [[B]], align 4 952 // CHECK2-NEXT: ret void 953 // 954 // 955 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 956 // CHECK2-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 957 // CHECK2-NEXT: entry: 958 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 959 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 960 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 961 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 962 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 963 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 964 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 965 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 966 // CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 967 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 968 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 969 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 970 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 971 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 972 // CHECK2-NEXT: ret void 973 // 974 // 975 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev 976 // CHECK2-SAME: (%struct.St* nonnull dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 977 // CHECK2-NEXT: entry: 978 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 979 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 980 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 981 // CHECK2-NEXT: ret void 982 // 983 // 984 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 985 // CHECK2-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 986 // CHECK2-NEXT: entry: 987 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 988 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 989 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 990 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) 991 // CHECK2-NEXT: ret void 992 // 993 // 994 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 995 // CHECK2-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 996 // CHECK2-NEXT: entry: 997 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 998 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 999 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1000 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1001 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1002 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1003 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 1004 // CHECK2-NEXT: ret void 1005 // 1006 // 1007 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1008 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR6:[0-9]+]] { 1009 // CHECK2-NEXT: entry: 1010 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1011 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1012 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 1013 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 1014 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 1015 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 1016 // CHECK2-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 1017 // CHECK2-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 1018 // CHECK2-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 1019 // CHECK2-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 1020 // CHECK2-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 1021 // CHECK2-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 1022 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 1023 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 1024 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1025 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1026 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1027 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1028 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1029 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 1030 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 1031 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1032 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 1033 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 1034 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 1035 // CHECK2-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 1036 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 1037 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 1038 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1039 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 1040 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 1041 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP0]], align 4 1042 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 4 1043 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1044 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* 1045 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP5]], i8* align 4 [[TMP6]], i64 8, i1 false) 1046 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1047 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 1048 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1049 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 1050 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1051 // CHECK2: omp.arraycpy.body: 1052 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1053 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1054 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) 1055 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1056 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] 1057 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1058 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1059 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 1060 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1061 // CHECK2: omp.arraycpy.done4: 1062 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) 1063 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 1064 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] 1065 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1066 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1067 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 1068 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1069 // CHECK2-NEXT: [[TMP12:%.*]] = icmp slt i32 [[TMP11]], 1 1070 // CHECK2-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP11]], i32 1 1071 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 1072 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 1073 // CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 1074 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1075 // CHECK2: omp.inner.for.cond: 1076 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1077 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1078 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] 1079 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1080 // CHECK2: omp.inner.for.body: 1081 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1082 // CHECK2-NEXT: switch i32 [[TMP17]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 1083 // CHECK2-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 1084 // CHECK2-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE7:%.*]] 1085 // CHECK2-NEXT: ] 1086 // CHECK2: .omp.sections.case: 1087 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[T_VAR1]], align 4 1088 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 1089 // CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX]], align 4 1090 // CHECK2-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1091 // CHECK2: .omp.sections.case7: 1092 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 1093 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast %struct.S.0* [[ARRAYIDX8]] to i8* 1094 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 1095 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP19]], i8* align 4 [[TMP20]], i64 4, i1 false) 1096 // CHECK2-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1097 // CHECK2: .omp.sections.exit: 1098 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1099 // CHECK2: omp.inner.for.inc: 1100 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1101 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP21]], 1 1102 // CHECK2-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 1103 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1104 // CHECK2: omp.inner.for.end: 1105 // CHECK2-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1106 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 1107 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 1108 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR5]]) #[[ATTR2]] 1109 // CHECK2-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1110 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN9]], i64 2 1111 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1112 // CHECK2: arraydestroy.body: 1113 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP24]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1114 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1115 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1116 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] 1117 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] 1118 // CHECK2: arraydestroy.done10: 1119 // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1120 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 1121 // CHECK2-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP26]]) 1122 // CHECK2-NEXT: ret void 1123 // 1124 // 1125 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1126 // CHECK2-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1127 // CHECK2-NEXT: entry: 1128 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1129 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1130 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1131 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1132 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1133 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1134 // CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1135 // CHECK2-NEXT: ret void 1136 // 1137 // 1138 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1139 // CHECK2-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1140 // CHECK2-NEXT: entry: 1141 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1142 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1143 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1144 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1145 // CHECK2-NEXT: ret void 1146 // 1147 // 1148 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1149 // CHECK2-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1150 // CHECK2-NEXT: entry: 1151 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1152 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1153 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1154 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1155 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1156 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1157 // CHECK2-NEXT: ret void 1158 // 1159 // 1160 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1161 // CHECK2-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1162 // CHECK2-NEXT: entry: 1163 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1164 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1165 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1166 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1167 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1168 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1169 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1170 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1171 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1172 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1173 // CHECK2-NEXT: ret void 1174 // 1175 // 1176 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1177 // CHECK2-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1178 // CHECK2-NEXT: entry: 1179 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1180 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 1181 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1182 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 1183 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1184 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1185 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 1186 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1187 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1188 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1189 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1190 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1191 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1192 // CHECK2-NEXT: ret void 1193 // 1194 // 1195 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1196 // CHECK2-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1197 // CHECK2-NEXT: entry: 1198 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1199 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1200 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1201 // CHECK2-NEXT: ret void 1202 // 1203 // 1204 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1205 // CHECK2-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1206 // CHECK2-NEXT: entry: 1207 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1208 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1209 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1210 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1211 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1212 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1213 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4 1214 // CHECK2-NEXT: ret void 1215 // 1216 // 1217 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1218 // CHECK2-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1219 // CHECK2-NEXT: entry: 1220 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1221 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1222 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1223 // CHECK2-NEXT: ret void 1224 // 1225 // 1226 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1227 // CHECK2-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1228 // CHECK2-NEXT: entry: 1229 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1230 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1231 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1232 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1233 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1234 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1235 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1236 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1237 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1238 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1239 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 1240 // CHECK2-NEXT: ret void 1241 // 1242 // 1243 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 1244 // CHECK2-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1245 // CHECK2-NEXT: entry: 1246 // CHECK2-NEXT: call void @__cxx_global_var_init() 1247 // CHECK2-NEXT: call void @__cxx_global_var_init.1() 1248 // CHECK2-NEXT: call void @__cxx_global_var_init.2() 1249 // CHECK2-NEXT: ret void 1250 // 1251 // 1252 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init 1253 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1254 // CHECK3-NEXT: entry: 1255 // CHECK3-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) 1256 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1257 // CHECK3-NEXT: ret void 1258 // 1259 // 1260 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1261 // CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 1262 // CHECK3-NEXT: entry: 1263 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1264 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1265 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1266 // CHECK3-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) 1267 // CHECK3-NEXT: ret void 1268 // 1269 // 1270 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1271 // CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1272 // CHECK3-NEXT: entry: 1273 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1274 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1275 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1276 // CHECK3-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1277 // CHECK3-NEXT: ret void 1278 // 1279 // 1280 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1281 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1282 // CHECK3-NEXT: entry: 1283 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 1284 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 1285 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1286 // CHECK3-NEXT: ret void 1287 // 1288 // 1289 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1290 // CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1291 // CHECK3-NEXT: entry: 1292 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1293 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1294 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1295 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1296 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1297 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1298 // CHECK3-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) 1299 // CHECK3-NEXT: ret void 1300 // 1301 // 1302 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1303 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1304 // CHECK3-NEXT: entry: 1305 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1306 // CHECK3-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1307 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1308 // CHECK3: arraydestroy.body: 1309 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1310 // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1311 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1312 // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1313 // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1314 // CHECK3: arraydestroy.done1: 1315 // CHECK3-NEXT: ret void 1316 // 1317 // 1318 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1319 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1320 // CHECK3-NEXT: entry: 1321 // CHECK3-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) 1322 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1323 // CHECK3-NEXT: ret void 1324 // 1325 // 1326 // CHECK3-LABEL: define {{[^@]+}}@main 1327 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1328 // CHECK3-NEXT: entry: 1329 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1330 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 1331 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1332 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 1333 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 1334 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) 1335 // CHECK3-NEXT: ret i32 0 1336 // 1337 // 1338 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1339 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] { 1340 // CHECK3-NEXT: entry: 1341 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1342 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1343 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 1344 // CHECK3-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 1345 // CHECK3-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 1346 // CHECK3-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 1347 // CHECK3-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 1348 // CHECK3-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 1349 // CHECK3-NEXT: [[G:%.*]] = alloca i32, align 4 1350 // CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 1351 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 1352 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1353 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1354 // CHECK3-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 1355 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 1356 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 1357 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1358 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 1359 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 1360 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1361 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[G]], align 4 1362 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP0]], align 4 1363 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[SIVAR1]], align 4 1364 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1365 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 1366 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 1367 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1368 // CHECK3-NEXT: [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 1 1369 // CHECK3-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP5]], i32 1 1370 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 1371 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 1372 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 1373 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1374 // CHECK3: omp.inner.for.cond: 1375 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1376 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1377 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1378 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1379 // CHECK3: omp.inner.for.body: 1380 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1381 // CHECK3-NEXT: switch i32 [[TMP11]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 1382 // CHECK3-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 1383 // CHECK3-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE2:%.*]] 1384 // CHECK3-NEXT: ] 1385 // CHECK3: .omp.sections.case: 1386 // CHECK3-NEXT: store i32 1, i32* [[G]], align 4 1387 // CHECK3-NEXT: store i32 10, i32* [[SIVAR1]], align 4 1388 // CHECK3-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1389 // CHECK3: .omp.sections.case2: 1390 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 1391 // CHECK3-NEXT: store i32* [[G]], i32** [[TMP12]], align 8 1392 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 1393 // CHECK3-NEXT: store i32* [[SIVAR1]], i32** [[TMP13]], align 8 1394 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull dereferenceable(16) [[REF_TMP]]) 1395 // CHECK3-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1396 // CHECK3: .omp.sections.exit: 1397 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1398 // CHECK3: omp.inner.for.inc: 1399 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1400 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 1401 // CHECK3-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 1402 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 1403 // CHECK3: omp.inner.for.end: 1404 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) 1405 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]]) 1406 // CHECK3-NEXT: ret void 1407 // 1408 // 1409 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1410 // CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1411 // CHECK3-NEXT: entry: 1412 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1413 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1414 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1415 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1416 // CHECK3-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1417 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1418 // CHECK3-NEXT: store float [[CONV]], float* [[F]], align 4 1419 // CHECK3-NEXT: ret void 1420 // 1421 // 1422 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1423 // CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1424 // CHECK3-NEXT: entry: 1425 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1426 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1427 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1428 // CHECK3-NEXT: ret void 1429 // 1430 // 1431 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1432 // CHECK3-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1433 // CHECK3-NEXT: entry: 1434 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1435 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1436 // CHECK3-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1437 // CHECK3-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1438 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1439 // CHECK3-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1440 // CHECK3-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1441 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1442 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1443 // CHECK3-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1444 // CHECK3-NEXT: store float [[ADD]], float* [[F]], align 4 1445 // CHECK3-NEXT: ret void 1446 // 1447 // 1448 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 1449 // CHECK3-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1450 // CHECK3-NEXT: entry: 1451 // CHECK3-NEXT: call void @__cxx_global_var_init() 1452 // CHECK3-NEXT: call void @__cxx_global_var_init.1() 1453 // CHECK3-NEXT: call void @__cxx_global_var_init.2() 1454 // CHECK3-NEXT: ret void 1455 // 1456 // 1457 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init 1458 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1459 // CHECK4-NEXT: entry: 1460 // CHECK4-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) 1461 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1462 // CHECK4-NEXT: ret void 1463 // 1464 // 1465 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1466 // CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 1467 // CHECK4-NEXT: entry: 1468 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1469 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1470 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1471 // CHECK4-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) 1472 // CHECK4-NEXT: ret void 1473 // 1474 // 1475 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1476 // CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1477 // CHECK4-NEXT: entry: 1478 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1479 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1480 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1481 // CHECK4-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1482 // CHECK4-NEXT: ret void 1483 // 1484 // 1485 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1486 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1487 // CHECK4-NEXT: entry: 1488 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 1489 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 1490 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1491 // CHECK4-NEXT: ret void 1492 // 1493 // 1494 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1495 // CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1496 // CHECK4-NEXT: entry: 1497 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1498 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1499 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1500 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1501 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1502 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1503 // CHECK4-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) 1504 // CHECK4-NEXT: ret void 1505 // 1506 // 1507 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1508 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1509 // CHECK4-NEXT: entry: 1510 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1511 // CHECK4-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1512 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1513 // CHECK4: arraydestroy.body: 1514 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1515 // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1516 // CHECK4-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1517 // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1518 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1519 // CHECK4: arraydestroy.done1: 1520 // CHECK4-NEXT: ret void 1521 // 1522 // 1523 // CHECK4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1524 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1525 // CHECK4-NEXT: entry: 1526 // CHECK4-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) 1527 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1528 // CHECK4-NEXT: ret void 1529 // 1530 // 1531 // CHECK4-LABEL: define {{[^@]+}}@main 1532 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 1533 // CHECK4-NEXT: entry: 1534 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1535 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 1536 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 1537 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 1538 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 1539 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 1540 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 1541 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 1542 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 1543 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 1544 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 1545 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 1546 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 1547 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 1548 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1549 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 1550 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* 1551 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* 1552 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 1553 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 1554 // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 1555 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* 1556 // CHECK4-NEXT: call void [[TMP5]](i8* [[TMP3]]) 1557 // CHECK4-NEXT: ret i32 0 1558 // 1559 // 1560 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke 1561 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 1562 // CHECK4-NEXT: entry: 1563 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 1564 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 1565 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 1566 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* 1567 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 1568 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5sivar) 1569 // CHECK4-NEXT: ret void 1570 // 1571 // 1572 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 1573 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] { 1574 // CHECK4-NEXT: entry: 1575 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1576 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1577 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32*, align 8 1578 // CHECK4-NEXT: [[DOTOMP_SECTIONS_LB_:%.*]] = alloca i32, align 4 1579 // CHECK4-NEXT: [[DOTOMP_SECTIONS_UB_:%.*]] = alloca i32, align 4 1580 // CHECK4-NEXT: [[DOTOMP_SECTIONS_ST_:%.*]] = alloca i32, align 4 1581 // CHECK4-NEXT: [[DOTOMP_SECTIONS_IL_:%.*]] = alloca i32, align 4 1582 // CHECK4-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 1583 // CHECK4-NEXT: [[G:%.*]] = alloca i32, align 4 1584 // CHECK4-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 1585 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, align 8 1586 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1587 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1588 // CHECK4-NEXT: store i32* [[SIVAR]], i32** [[SIVAR_ADDR]], align 8 1589 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[SIVAR_ADDR]], align 8 1590 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_LB_]], align 4 1591 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1592 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_SECTIONS_ST_]], align 4 1593 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_SECTIONS_IL_]], align 4 1594 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1595 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[G]], align 4 1596 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP0]], align 4 1597 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[SIVAR1]], align 4 1598 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1599 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 1600 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 34, i32* [[DOTOMP_SECTIONS_IL_]], i32* [[DOTOMP_SECTIONS_LB_]], i32* [[DOTOMP_SECTIONS_UB_]], i32* [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) 1601 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1602 // CHECK4-NEXT: [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 1 1603 // CHECK4-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP5]], i32 1 1604 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_SECTIONS_UB_]], align 4 1605 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_LB_]], align 4 1606 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 1607 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1608 // CHECK4: omp.inner.for.cond: 1609 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1610 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_UB_]], align 4 1611 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1612 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1613 // CHECK4: omp.inner.for.body: 1614 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1615 // CHECK4-NEXT: switch i32 [[TMP11]], label [[DOTOMP_SECTIONS_EXIT:%.*]] [ 1616 // CHECK4-NEXT: i32 0, label [[DOTOMP_SECTIONS_CASE:%.*]] 1617 // CHECK4-NEXT: i32 1, label [[DOTOMP_SECTIONS_CASE2:%.*]] 1618 // CHECK4-NEXT: ] 1619 // CHECK4: .omp.sections.case: 1620 // CHECK4-NEXT: store i32 1, i32* [[G]], align 4 1621 // CHECK4-NEXT: store i32 10, i32* [[SIVAR1]], align 4 1622 // CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1623 // CHECK4: .omp.sections.case2: 1624 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 0 1625 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 1626 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 1 1627 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 1628 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 2 1629 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 1630 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 3 1631 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @var_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 1632 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 4 1633 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 1634 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 1635 // CHECK4-NEXT: [[TMP12:%.*]] = load volatile i32, i32* [[G]], align 4 1636 // CHECK4-NEXT: store volatile i32 [[TMP12]], i32* [[BLOCK_CAPTURED]], align 8 1637 // CHECK4-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 1638 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[SIVAR1]], align 4 1639 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[BLOCK_CAPTURED3]], align 4 1640 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]] to void ()* 1641 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP14]] to %struct.__block_literal_generic* 1642 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 1643 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 1644 // CHECK4-NEXT: [[TMP17:%.*]] = load i8*, i8** [[TMP15]], align 8 1645 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8* [[TMP17]] to void (i8*)* 1646 // CHECK4-NEXT: call void [[TMP18]](i8* [[TMP16]]) 1647 // CHECK4-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] 1648 // CHECK4: .omp.sections.exit: 1649 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1650 // CHECK4: omp.inner.for.inc: 1651 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_SECTIONS_IV_]], align 4 1652 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP19]], 1 1653 // CHECK4-NEXT: store i32 [[INC]], i32* [[DOTOMP_SECTIONS_IV_]], align 4 1654 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 1655 // CHECK4: omp.inner.for.end: 1656 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) 1657 // CHECK4-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP4]]) 1658 // CHECK4-NEXT: ret void 1659 // 1660 // 1661 // CHECK4-LABEL: define {{[^@]+}}@var_block_invoke 1662 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 1663 // CHECK4-NEXT: entry: 1664 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 1665 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 1666 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 1667 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* 1668 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>** [[BLOCK_ADDR]], align 8 1669 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 1670 // CHECK4-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 1671 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 1672 // CHECK4-NEXT: store i32 20, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 1673 // CHECK4-NEXT: ret void 1674 // 1675 // 1676 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1677 // CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1678 // CHECK4-NEXT: entry: 1679 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1680 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1681 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1682 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1683 // CHECK4-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1684 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1685 // CHECK4-NEXT: store float [[CONV]], float* [[F]], align 4 1686 // CHECK4-NEXT: ret void 1687 // 1688 // 1689 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1690 // CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1691 // CHECK4-NEXT: entry: 1692 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1693 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1694 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1695 // CHECK4-NEXT: ret void 1696 // 1697 // 1698 // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1699 // CHECK4-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1700 // CHECK4-NEXT: entry: 1701 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1702 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1703 // CHECK4-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1704 // CHECK4-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1705 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1706 // CHECK4-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1707 // CHECK4-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1708 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1709 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1710 // CHECK4-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1711 // CHECK4-NEXT: store float [[ADD]], float* [[F]], align 4 1712 // CHECK4-NEXT: ret void 1713 // 1714 // 1715 // CHECK4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 1716 // CHECK4-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1717 // CHECK4-NEXT: entry: 1718 // CHECK4-NEXT: call void @__cxx_global_var_init() 1719 // CHECK4-NEXT: call void @__cxx_global_var_init.1() 1720 // CHECK4-NEXT: call void @__cxx_global_var_init.2() 1721 // CHECK4-NEXT: ret void 1722 // 1723 // 1724 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init 1725 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1726 // CHECK5-NEXT: entry: 1727 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) 1728 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1729 // CHECK5-NEXT: ret void 1730 // 1731 // 1732 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1733 // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 1734 // CHECK5-NEXT: entry: 1735 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1736 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1737 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1738 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) 1739 // CHECK5-NEXT: ret void 1740 // 1741 // 1742 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1743 // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1744 // CHECK5-NEXT: entry: 1745 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1746 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1747 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1748 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1749 // CHECK5-NEXT: ret void 1750 // 1751 // 1752 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 1753 // CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1754 // CHECK5-NEXT: entry: 1755 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 1756 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 1757 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 1758 // CHECK5-NEXT: ret void 1759 // 1760 // 1761 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1762 // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1763 // CHECK5-NEXT: entry: 1764 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1765 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1766 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1767 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1768 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1769 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1770 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) 1771 // CHECK5-NEXT: ret void 1772 // 1773 // 1774 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 1775 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1776 // CHECK5-NEXT: entry: 1777 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 1778 // CHECK5-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 1779 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1780 // CHECK5: arraydestroy.body: 1781 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1782 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1783 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1784 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 1785 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1786 // CHECK5: arraydestroy.done1: 1787 // CHECK5-NEXT: ret void 1788 // 1789 // 1790 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 1791 // CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1792 // CHECK5-NEXT: entry: 1793 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) 1794 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 1795 // CHECK5-NEXT: ret void 1796 // 1797 // 1798 // CHECK5-LABEL: define {{[^@]+}}@main 1799 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 1800 // CHECK5-NEXT: entry: 1801 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1802 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 1803 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 1804 // CHECK5-NEXT: store i32 [[TMP0]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @vec, i64 0, i64 0), align 4 1805 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x %struct.S]* @s_arr to i8*), i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) 1806 // CHECK5-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 1807 // CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 1808 // CHECK5-NEXT: ret i32 [[CALL]] 1809 // 1810 // 1811 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1812 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] { 1813 // CHECK5-NEXT: entry: 1814 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1815 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1816 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 1817 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 1818 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 1819 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 1820 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) 1821 // CHECK5-NEXT: store i32 0, i32* [[T_VAR]], align 4 1822 // CHECK5-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1823 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 1824 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1825 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 1826 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 1827 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 1828 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) 1829 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 1830 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 1831 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 1832 // CHECK5-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 1833 // CHECK5-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 1834 // CHECK5-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 1835 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) 1836 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 1837 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] 1838 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1839 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 1840 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1841 // CHECK5: arraydestroy.body: 1842 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1843 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 1844 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 1845 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1846 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 1847 // CHECK5: arraydestroy.done2: 1848 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] 1849 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 1850 // CHECK5-NEXT: ret i32 [[TMP5]] 1851 // 1852 // 1853 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1854 // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1855 // CHECK5-NEXT: entry: 1856 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1857 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1858 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1859 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1860 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1861 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1862 // CHECK5-NEXT: store float [[CONV]], float* [[F]], align 4 1863 // CHECK5-NEXT: ret void 1864 // 1865 // 1866 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1867 // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1868 // CHECK5-NEXT: entry: 1869 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1870 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1871 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1872 // CHECK5-NEXT: ret void 1873 // 1874 // 1875 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1876 // CHECK5-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1877 // CHECK5-NEXT: entry: 1878 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1879 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1880 // CHECK5-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1881 // CHECK5-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1882 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1883 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1884 // CHECK5-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1885 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1886 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1887 // CHECK5-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1888 // CHECK5-NEXT: store float [[ADD]], float* [[F]], align 4 1889 // CHECK5-NEXT: ret void 1890 // 1891 // 1892 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1893 // CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1894 // CHECK5-NEXT: entry: 1895 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1896 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1897 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1898 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) 1899 // CHECK5-NEXT: ret void 1900 // 1901 // 1902 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1903 // CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1904 // CHECK5-NEXT: entry: 1905 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1906 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1907 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1908 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1909 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1910 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1911 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 1912 // CHECK5-NEXT: ret void 1913 // 1914 // 1915 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1916 // CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1917 // CHECK5-NEXT: entry: 1918 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1919 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1920 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1921 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1922 // CHECK5-NEXT: ret void 1923 // 1924 // 1925 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1926 // CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1927 // CHECK5-NEXT: entry: 1928 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1929 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1930 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1931 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1932 // CHECK5-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 1933 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1934 // CHECK5-NEXT: ret void 1935 // 1936 // 1937 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1938 // CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1939 // CHECK5-NEXT: entry: 1940 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1941 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1942 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1943 // CHECK5-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1944 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1945 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1946 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1947 // CHECK5-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 1948 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1949 // CHECK5-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1950 // CHECK5-NEXT: ret void 1951 // 1952 // 1953 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1954 // CHECK5-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1955 // CHECK5-NEXT: entry: 1956 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 1957 // CHECK5-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 1958 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 1959 // CHECK5-NEXT: ret void 1960 // 1961 // 1962 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 1963 // CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1964 // CHECK5-NEXT: entry: 1965 // CHECK5-NEXT: call void @__cxx_global_var_init() 1966 // CHECK5-NEXT: call void @__cxx_global_var_init.1() 1967 // CHECK5-NEXT: call void @__cxx_global_var_init.2() 1968 // CHECK5-NEXT: ret void 1969 // 1970 // 1971 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init 1972 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 1973 // CHECK6-NEXT: entry: 1974 // CHECK6-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) 1975 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 1976 // CHECK6-NEXT: ret void 1977 // 1978 // 1979 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 1980 // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 1981 // CHECK6-NEXT: entry: 1982 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1983 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1984 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1985 // CHECK6-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) 1986 // CHECK6-NEXT: ret void 1987 // 1988 // 1989 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1990 // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 1991 // CHECK6-NEXT: entry: 1992 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 1993 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 1994 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 1995 // CHECK6-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] 1996 // CHECK6-NEXT: ret void 1997 // 1998 // 1999 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2000 // CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2001 // CHECK6-NEXT: entry: 2002 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 2003 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 2004 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2005 // CHECK6-NEXT: ret void 2006 // 2007 // 2008 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2009 // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2010 // CHECK6-NEXT: entry: 2011 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2012 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2013 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2014 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2015 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2016 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2017 // CHECK6-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) 2018 // CHECK6-NEXT: ret void 2019 // 2020 // 2021 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2022 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2023 // CHECK6-NEXT: entry: 2024 // CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2025 // CHECK6-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2026 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2027 // CHECK6: arraydestroy.body: 2028 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2029 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2030 // CHECK6-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2031 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2032 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2033 // CHECK6: arraydestroy.done1: 2034 // CHECK6-NEXT: ret void 2035 // 2036 // 2037 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2038 // CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2039 // CHECK6-NEXT: entry: 2040 // CHECK6-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) 2041 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2042 // CHECK6-NEXT: ret void 2043 // 2044 // 2045 // CHECK6-LABEL: define {{[^@]+}}@main 2046 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] { 2047 // CHECK6-NEXT: entry: 2048 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2049 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 2050 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* @t_var, align 4 2051 // CHECK6-NEXT: store i32 [[TMP0]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @vec, i64 0, i64 0), align 4 2052 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x %struct.S]* @s_arr to i8*), i8* align 4 bitcast (%struct.S* @var to i8*), i64 4, i1 false) 2053 // CHECK6-NEXT: store i32 31, i32* @_ZZ4mainE5sivar, align 4 2054 // CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 2055 // CHECK6-NEXT: ret i32 [[CALL]] 2056 // 2057 // 2058 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2059 // CHECK6-SAME: () #[[ATTR5:[0-9]+]] { 2060 // CHECK6-NEXT: entry: 2061 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2062 // CHECK6-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2063 // CHECK6-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2064 // CHECK6-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2065 // CHECK6-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 2066 // CHECK6-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 2067 // CHECK6-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) 2068 // CHECK6-NEXT: store i32 0, i32* [[T_VAR]], align 4 2069 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2070 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 2071 // CHECK6-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 2072 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2073 // CHECK6-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 2074 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2075 // CHECK6-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull dereferenceable(4) [[VAR]], i32 3) 2076 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 2077 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 2078 // CHECK6-NEXT: store i32 [[TMP1]], i32* [[ARRAYIDX]], align 4 2079 // CHECK6-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 2080 // CHECK6-NEXT: [[TMP2:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* 2081 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* 2082 // CHECK6-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP2]], i8* align 4 [[TMP3]], i64 4, i1 false) 2083 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 2084 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[VAR]]) #[[ATTR2]] 2085 // CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2086 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 2087 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2088 // CHECK6: arraydestroy.body: 2089 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2090 // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2091 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2092 // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2093 // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 2094 // CHECK6: arraydestroy.done2: 2095 // CHECK6-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull dereferenceable(4) [[TEST]]) #[[ATTR2]] 2096 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4 2097 // CHECK6-NEXT: ret i32 [[TMP5]] 2098 // 2099 // 2100 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2101 // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2102 // CHECK6-NEXT: entry: 2103 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2104 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2105 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2106 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2107 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2108 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2109 // CHECK6-NEXT: store float [[CONV]], float* [[F]], align 4 2110 // CHECK6-NEXT: ret void 2111 // 2112 // 2113 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2114 // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2115 // CHECK6-NEXT: entry: 2116 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2117 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2118 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2119 // CHECK6-NEXT: ret void 2120 // 2121 // 2122 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2123 // CHECK6-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2124 // CHECK6-NEXT: entry: 2125 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2126 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2127 // CHECK6-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2128 // CHECK6-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2129 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2130 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2131 // CHECK6-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2132 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2133 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2134 // CHECK6-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2135 // CHECK6-NEXT: store float [[ADD]], float* [[F]], align 4 2136 // CHECK6-NEXT: ret void 2137 // 2138 // 2139 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2140 // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2141 // CHECK6-NEXT: entry: 2142 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2143 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2144 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2145 // CHECK6-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) 2146 // CHECK6-NEXT: ret void 2147 // 2148 // 2149 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2150 // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2151 // CHECK6-NEXT: entry: 2152 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2153 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2154 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2155 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2156 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2157 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2158 // CHECK6-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 2159 // CHECK6-NEXT: ret void 2160 // 2161 // 2162 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2163 // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2164 // CHECK6-NEXT: entry: 2165 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2166 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2167 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2168 // CHECK6-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2169 // CHECK6-NEXT: ret void 2170 // 2171 // 2172 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2173 // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2174 // CHECK6-NEXT: entry: 2175 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2176 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2177 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2178 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2179 // CHECK6-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2180 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2181 // CHECK6-NEXT: ret void 2182 // 2183 // 2184 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2185 // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2186 // CHECK6-NEXT: entry: 2187 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2188 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2189 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2190 // CHECK6-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2191 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2192 // CHECK6-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2193 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2194 // CHECK6-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2195 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2196 // CHECK6-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2197 // CHECK6-NEXT: ret void 2198 // 2199 // 2200 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2201 // CHECK6-SAME: (%struct.S.0* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2202 // CHECK6-NEXT: entry: 2203 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2204 // CHECK6-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2205 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2206 // CHECK6-NEXT: ret void 2207 // 2208 // 2209 // CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 2210 // CHECK6-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2211 // CHECK6-NEXT: entry: 2212 // CHECK6-NEXT: call void @__cxx_global_var_init() 2213 // CHECK6-NEXT: call void @__cxx_global_var_init.1() 2214 // CHECK6-NEXT: call void @__cxx_global_var_init.2() 2215 // CHECK6-NEXT: ret void 2216 // 2217 // 2218 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init 2219 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2220 // CHECK7-NEXT: entry: 2221 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) 2222 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2223 // CHECK7-NEXT: ret void 2224 // 2225 // 2226 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2227 // CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 2228 // CHECK7-NEXT: entry: 2229 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2230 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2231 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2232 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) 2233 // CHECK7-NEXT: ret void 2234 // 2235 // 2236 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2237 // CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2238 // CHECK7-NEXT: entry: 2239 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2240 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2241 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2242 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2243 // CHECK7-NEXT: ret void 2244 // 2245 // 2246 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2247 // CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2248 // CHECK7-NEXT: entry: 2249 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 2250 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 2251 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2252 // CHECK7-NEXT: ret void 2253 // 2254 // 2255 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2256 // CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2257 // CHECK7-NEXT: entry: 2258 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2259 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2260 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2261 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2262 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2263 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2264 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) 2265 // CHECK7-NEXT: ret void 2266 // 2267 // 2268 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2269 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2270 // CHECK7-NEXT: entry: 2271 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2272 // CHECK7-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2273 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2274 // CHECK7: arraydestroy.body: 2275 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2276 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2277 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2278 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2279 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2280 // CHECK7: arraydestroy.done1: 2281 // CHECK7-NEXT: ret void 2282 // 2283 // 2284 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2285 // CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2286 // CHECK7-NEXT: entry: 2287 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) 2288 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2289 // CHECK7-NEXT: ret void 2290 // 2291 // 2292 // CHECK7-LABEL: define {{[^@]+}}@main 2293 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 2294 // CHECK7-NEXT: entry: 2295 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2296 // CHECK7-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 2297 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 2298 // CHECK7-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 2299 // CHECK7-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 2300 // CHECK7-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull dereferenceable(8) [[REF_TMP]]) 2301 // CHECK7-NEXT: ret i32 0 2302 // 2303 // 2304 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2305 // CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2306 // CHECK7-NEXT: entry: 2307 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2308 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2309 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2310 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2311 // CHECK7-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2312 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2313 // CHECK7-NEXT: store float [[CONV]], float* [[F]], align 4 2314 // CHECK7-NEXT: ret void 2315 // 2316 // 2317 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2318 // CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2319 // CHECK7-NEXT: entry: 2320 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2321 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2322 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2323 // CHECK7-NEXT: ret void 2324 // 2325 // 2326 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2327 // CHECK7-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2328 // CHECK7-NEXT: entry: 2329 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2330 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2331 // CHECK7-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2332 // CHECK7-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2333 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2334 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2335 // CHECK7-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2336 // CHECK7-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2337 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2338 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2339 // CHECK7-NEXT: store float [[ADD]], float* [[F]], align 4 2340 // CHECK7-NEXT: ret void 2341 // 2342 // 2343 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 2344 // CHECK7-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2345 // CHECK7-NEXT: entry: 2346 // CHECK7-NEXT: call void @__cxx_global_var_init() 2347 // CHECK7-NEXT: call void @__cxx_global_var_init.1() 2348 // CHECK7-NEXT: call void @__cxx_global_var_init.2() 2349 // CHECK7-NEXT: ret void 2350 // 2351 // 2352 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init 2353 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2354 // CHECK8-NEXT: entry: 2355 // CHECK8-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull dereferenceable(4) @test) 2356 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @test to i8*), i8* @__dso_handle) #[[ATTR2:[0-9]+]] 2357 // CHECK8-NEXT: ret void 2358 // 2359 // 2360 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2361 // CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { 2362 // CHECK8-NEXT: entry: 2363 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2364 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2365 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2366 // CHECK8-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) 2367 // CHECK8-NEXT: ret void 2368 // 2369 // 2370 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2371 // CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2372 // CHECK8-NEXT: entry: 2373 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2374 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2375 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2376 // CHECK8-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull dereferenceable(4) [[THIS1]]) #[[ATTR2]] 2377 // CHECK8-NEXT: ret void 2378 // 2379 // 2380 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 2381 // CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2382 // CHECK8-NEXT: entry: 2383 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 0), float 1.000000e+00) 2384 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i64 0, i64 1), float 2.000000e+00) 2385 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR2]] 2386 // CHECK8-NEXT: ret void 2387 // 2388 // 2389 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2390 // CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2391 // CHECK8-NEXT: entry: 2392 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2393 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2394 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2395 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2396 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2397 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2398 // CHECK8-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull dereferenceable(4) [[THIS1]], float [[TMP0]]) 2399 // CHECK8-NEXT: ret void 2400 // 2401 // 2402 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_array_dtor 2403 // CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2404 // CHECK8-NEXT: entry: 2405 // CHECK8-NEXT: [[DOTADDR:%.*]] = alloca i8*, align 8 2406 // CHECK8-NEXT: store i8* [[TMP0]], i8** [[DOTADDR]], align 8 2407 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2408 // CHECK8: arraydestroy.body: 2409 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2410 // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2411 // CHECK8-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] 2412 // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @s_arr, i32 0, i32 0) 2413 // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2414 // CHECK8: arraydestroy.done1: 2415 // CHECK8-NEXT: ret void 2416 // 2417 // 2418 // CHECK8-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 2419 // CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2420 // CHECK8-NEXT: entry: 2421 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull dereferenceable(4) @var, float 3.000000e+00) 2422 // CHECK8-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @var to i8*), i8* @__dso_handle) #[[ATTR2]] 2423 // CHECK8-NEXT: ret void 2424 // 2425 // 2426 // CHECK8-LABEL: define {{[^@]+}}@main 2427 // CHECK8-SAME: () #[[ATTR3:[0-9]+]] { 2428 // CHECK8-NEXT: entry: 2429 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2430 // CHECK8-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 2431 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 2432 // CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 2433 // CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 2434 // CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 2435 // CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 2436 // CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 2437 // CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 2438 // CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 2439 // CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 2440 // CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 2441 // CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.3 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 2442 // CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 2443 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 2444 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 2445 // CHECK8-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* 2446 // CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* 2447 // CHECK8-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 2448 // CHECK8-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 2449 // CHECK8-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 2450 // CHECK8-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* 2451 // CHECK8-NEXT: call void [[TMP5]](i8* [[TMP3]]) 2452 // CHECK8-NEXT: ret i32 0 2453 // 2454 // 2455 // CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke 2456 // CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 2457 // CHECK8-NEXT: entry: 2458 // CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 2459 // CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 2460 // CHECK8-NEXT: [[BLOCK1:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, align 8 2461 // CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 2462 // CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* 2463 // CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 2464 // CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 2465 // CHECK8-NEXT: store i32 1, i32* @g, align 4 2466 // CHECK8-NEXT: store i32 10, i32* [[BLOCK_CAPTURE_ADDR]], align 8 2467 // CHECK8-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 0 2468 // CHECK8-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 2469 // CHECK8-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 1 2470 // CHECK8-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 2471 // CHECK8-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 2 2472 // CHECK8-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 2473 // CHECK8-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 3 2474 // CHECK8-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 2475 // CHECK8-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 4 2476 // CHECK8-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 2477 // CHECK8-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 5 2478 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2479 // CHECK8-NEXT: store volatile i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 2480 // CHECK8-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]], i32 0, i32 6 2481 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR]], align 8 2482 // CHECK8-NEXT: store i32 [[TMP1]], i32* [[BLOCK_CAPTURED2]], align 4 2483 // CHECK8-NEXT: [[TMP2:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK1]] to void ()* 2484 // CHECK8-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP2]] to %struct.__block_literal_generic* 2485 // CHECK8-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 2486 // CHECK8-NEXT: [[TMP4:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 2487 // CHECK8-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP3]], align 8 2488 // CHECK8-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to void (i8*)* 2489 // CHECK8-NEXT: call void [[TMP6]](i8* [[TMP4]]) 2490 // CHECK8-NEXT: ret void 2491 // 2492 // 2493 // CHECK8-LABEL: define {{[^@]+}}@__main_block_invoke_2 2494 // CHECK8-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 2495 // CHECK8-NEXT: entry: 2496 // CHECK8-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 2497 // CHECK8-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>*, align 8 2498 // CHECK8-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 2499 // CHECK8-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* 2500 // CHECK8-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>** [[BLOCK_ADDR]], align 8 2501 // CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 5 2502 // CHECK8-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 8 2503 // CHECK8-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, i32 }>* [[BLOCK]], i32 0, i32 6 2504 // CHECK8-NEXT: store i32 20, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 2505 // CHECK8-NEXT: ret void 2506 // 2507 // 2508 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2509 // CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2510 // CHECK8-NEXT: entry: 2511 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2512 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2513 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2514 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2515 // CHECK8-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 4 2516 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2517 // CHECK8-NEXT: store float [[CONV]], float* [[F]], align 4 2518 // CHECK8-NEXT: ret void 2519 // 2520 // 2521 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2522 // CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2523 // CHECK8-NEXT: entry: 2524 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2525 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2526 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2527 // CHECK8-NEXT: ret void 2528 // 2529 // 2530 // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2531 // CHECK8-SAME: (%struct.S* nonnull dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { 2532 // CHECK8-NEXT: entry: 2533 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2534 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2535 // CHECK8-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2536 // CHECK8-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2537 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2538 // CHECK8-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2539 // CHECK8-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2540 // CHECK8-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 4 2541 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2542 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2543 // CHECK8-NEXT: store float [[ADD]], float* [[F]], align 4 2544 // CHECK8-NEXT: ret void 2545 // 2546 // 2547 // CHECK8-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_sections_firstprivate_codegen.cpp 2548 // CHECK8-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" { 2549 // CHECK8-NEXT: entry: 2550 // CHECK8-NEXT: call void @__cxx_global_var_init() 2551 // CHECK8-NEXT: call void @__cxx_global_var_init.1() 2552 // CHECK8-NEXT: call void @__cxx_global_var_init.2() 2553 // CHECK8-NEXT: ret void 2554 // 2555