1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-function-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 5 6 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux -emit-llvm %s -disable-O0-optnone -o - | FileCheck %s --check-prefix=CHECK5 11 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 12 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s 13 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7 14 15 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8 16 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s 17 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 18 19 // expected-no-diagnostics 20 #ifndef HEADER 21 #define HEADER 22 23 void fn1(); 24 void fn2(); 25 void fn3(); 26 void fn4(); 27 void fn5(); 28 void fn6(); 29 30 int Arg; 31 32 void gtid_test() { 33 #pragma omp parallel 34 #pragma omp parallel if (parallel: false) 35 gtid_test(); 36 } 37 38 39 40 template <typename T> 41 int tmain(T Arg) { 42 #pragma omp parallel if (true) 43 fn1(); 44 #pragma omp parallel if (false) 45 fn2(); 46 #pragma omp parallel if (parallel: Arg) 47 fn3(); 48 return 0; 49 } 50 51 int main() { 52 #pragma omp parallel if (true) 53 fn4(); 54 #pragma omp parallel if (false) 55 fn5(); 56 57 #pragma omp parallel if (Arg) 58 fn6(); 59 return tmain(Arg); 60 } 61 62 63 64 65 66 67 68 69 #endif 70 // CHECK1-LABEL: define {{[^@]+}}@_Z9gtid_testv 71 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 72 // CHECK1-NEXT: entry: 73 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 74 // CHECK1-NEXT: ret void 75 // 76 // 77 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 78 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 79 // CHECK1-NEXT: entry: 80 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 81 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 82 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 83 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 84 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 85 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 86 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 87 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 88 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 89 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 90 // CHECK1-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] 91 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 92 // CHECK1-NEXT: ret void 93 // 94 // 95 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 96 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 97 // CHECK1-NEXT: entry: 98 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 99 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 100 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 101 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 102 // CHECK1-NEXT: call void @_Z9gtid_testv() 103 // CHECK1-NEXT: ret void 104 // 105 // 106 // CHECK1-LABEL: define {{[^@]+}}@main 107 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 108 // CHECK1-NEXT: entry: 109 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 110 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 111 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 112 // CHECK1-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 113 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 114 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 115 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 116 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 117 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 118 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) 119 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 120 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 121 // CHECK1-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] 122 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 123 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4 124 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 125 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 126 // CHECK1: omp_if.then: 127 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 128 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 129 // CHECK1: omp_if.else: 130 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 131 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 132 // CHECK1-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] 133 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 134 // CHECK1-NEXT: br label [[OMP_IF_END]] 135 // CHECK1: omp_if.end: 136 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 137 // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) 138 // CHECK1-NEXT: ret i32 [[CALL]] 139 // 140 // 141 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 142 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 143 // CHECK1-NEXT: entry: 144 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 145 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 146 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 147 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 148 // CHECK1-NEXT: call void @_Z3fn4v() 149 // CHECK1-NEXT: ret void 150 // 151 // 152 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 153 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 154 // CHECK1-NEXT: entry: 155 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 156 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 157 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 158 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 159 // CHECK1-NEXT: call void @_Z3fn5v() 160 // CHECK1-NEXT: ret void 161 // 162 // 163 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 164 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 165 // CHECK1-NEXT: entry: 166 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 167 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 168 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 169 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 170 // CHECK1-NEXT: call void @_Z3fn6v() 171 // CHECK1-NEXT: ret void 172 // 173 // 174 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ 175 // CHECK1-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { 176 // CHECK1-NEXT: entry: 177 // CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 178 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 179 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 180 // CHECK1-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 181 // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 182 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 183 // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 184 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 185 // CHECK1-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 186 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*)) 187 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 188 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 189 // CHECK1-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] 190 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 191 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 192 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 193 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 194 // CHECK1: omp_if.then: 195 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 196 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 197 // CHECK1: omp_if.else: 198 // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 199 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 200 // CHECK1-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] 201 // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 202 // CHECK1-NEXT: br label [[OMP_IF_END]] 203 // CHECK1: omp_if.end: 204 // CHECK1-NEXT: ret i32 0 205 // 206 // 207 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 208 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 209 // CHECK1-NEXT: entry: 210 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 211 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 212 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 213 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 214 // CHECK1-NEXT: call void @_Z3fn1v() 215 // CHECK1-NEXT: ret void 216 // 217 // 218 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 219 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 220 // CHECK1-NEXT: entry: 221 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 222 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 223 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 224 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 225 // CHECK1-NEXT: call void @_Z3fn2v() 226 // CHECK1-NEXT: ret void 227 // 228 // 229 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 230 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 231 // CHECK1-NEXT: entry: 232 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 233 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 234 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 235 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 236 // CHECK1-NEXT: call void @_Z3fn3v() 237 // CHECK1-NEXT: ret void 238 // 239 // 240 // CHECK2-LABEL: define {{[^@]+}}@_Z9gtid_testv 241 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 242 // CHECK2-NEXT: entry: 243 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 244 // CHECK2-NEXT: ret void 245 // 246 // 247 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 248 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 249 // CHECK2-NEXT: entry: 250 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 251 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 252 // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 253 // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 254 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 255 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 256 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 257 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 258 // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 259 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 260 // CHECK2-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] 261 // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 262 // CHECK2-NEXT: ret void 263 // 264 // 265 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 266 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 267 // CHECK2-NEXT: entry: 268 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 269 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 270 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 271 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 272 // CHECK2-NEXT: call void @_Z9gtid_testv() 273 // CHECK2-NEXT: ret void 274 // 275 // 276 // CHECK2-LABEL: define {{[^@]+}}@main 277 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 278 // CHECK2-NEXT: entry: 279 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 280 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 281 // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 282 // CHECK2-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 283 // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 284 // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 285 // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 286 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 287 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 288 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) 289 // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 290 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 291 // CHECK2-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] 292 // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 293 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4 294 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 295 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 296 // CHECK2: omp_if.then: 297 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 298 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 299 // CHECK2: omp_if.else: 300 // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 301 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 302 // CHECK2-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] 303 // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 304 // CHECK2-NEXT: br label [[OMP_IF_END]] 305 // CHECK2: omp_if.end: 306 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 307 // CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) 308 // CHECK2-NEXT: ret i32 [[CALL]] 309 // 310 // 311 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 312 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 313 // CHECK2-NEXT: entry: 314 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 315 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 316 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 317 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 318 // CHECK2-NEXT: call void @_Z3fn4v() 319 // CHECK2-NEXT: ret void 320 // 321 // 322 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 323 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 324 // CHECK2-NEXT: entry: 325 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 326 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 327 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 328 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 329 // CHECK2-NEXT: call void @_Z3fn5v() 330 // CHECK2-NEXT: ret void 331 // 332 // 333 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 334 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 335 // CHECK2-NEXT: entry: 336 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 337 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 338 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 339 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 340 // CHECK2-NEXT: call void @_Z3fn6v() 341 // CHECK2-NEXT: ret void 342 // 343 // 344 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ 345 // CHECK2-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { 346 // CHECK2-NEXT: entry: 347 // CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 348 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 349 // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 350 // CHECK2-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 351 // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 352 // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 353 // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 354 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 355 // CHECK2-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 356 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*)) 357 // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 358 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 359 // CHECK2-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] 360 // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 361 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 362 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 363 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 364 // CHECK2: omp_if.then: 365 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 366 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 367 // CHECK2: omp_if.else: 368 // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 369 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 370 // CHECK2-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] 371 // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 372 // CHECK2-NEXT: br label [[OMP_IF_END]] 373 // CHECK2: omp_if.end: 374 // CHECK2-NEXT: ret i32 0 375 // 376 // 377 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 378 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 379 // CHECK2-NEXT: entry: 380 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 381 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 382 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 383 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 384 // CHECK2-NEXT: call void @_Z3fn1v() 385 // CHECK2-NEXT: ret void 386 // 387 // 388 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 389 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 390 // CHECK2-NEXT: entry: 391 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 392 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 393 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 394 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 395 // CHECK2-NEXT: call void @_Z3fn2v() 396 // CHECK2-NEXT: ret void 397 // 398 // 399 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 400 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 401 // CHECK2-NEXT: entry: 402 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 403 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 404 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 405 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 406 // CHECK2-NEXT: call void @_Z3fn3v() 407 // CHECK2-NEXT: ret void 408 // 409 // 410 // CHECK3-LABEL: define {{[^@]+}}@_Z9gtid_testv 411 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 412 // CHECK3-NEXT: entry: 413 // CHECK3-NEXT: call void @_Z9gtid_testv() 414 // CHECK3-NEXT: ret void 415 // 416 // 417 // CHECK3-LABEL: define {{[^@]+}}@main 418 // CHECK3-SAME: () #[[ATTR1:[0-9]+]] { 419 // CHECK3-NEXT: entry: 420 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 421 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 422 // CHECK3-NEXT: call void @_Z3fn4v() 423 // CHECK3-NEXT: call void @_Z3fn5v() 424 // CHECK3-NEXT: call void @_Z3fn6v() 425 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 426 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) 427 // CHECK3-NEXT: ret i32 [[CALL]] 428 // 429 // 430 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ 431 // CHECK3-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { 432 // CHECK3-NEXT: entry: 433 // CHECK3-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 434 // CHECK3-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 435 // CHECK3-NEXT: call void @_Z3fn1v() 436 // CHECK3-NEXT: call void @_Z3fn2v() 437 // CHECK3-NEXT: call void @_Z3fn3v() 438 // CHECK3-NEXT: ret i32 0 439 // 440 // 441 // CHECK4-LABEL: define {{[^@]+}}@_Z9gtid_testv 442 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 443 // CHECK4-NEXT: entry: 444 // CHECK4-NEXT: call void @_Z9gtid_testv() 445 // CHECK4-NEXT: ret void 446 // 447 // 448 // CHECK4-LABEL: define {{[^@]+}}@main 449 // CHECK4-SAME: () #[[ATTR1:[0-9]+]] { 450 // CHECK4-NEXT: entry: 451 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 452 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 453 // CHECK4-NEXT: call void @_Z3fn4v() 454 // CHECK4-NEXT: call void @_Z3fn5v() 455 // CHECK4-NEXT: call void @_Z3fn6v() 456 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 457 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) 458 // CHECK4-NEXT: ret i32 [[CALL]] 459 // 460 // 461 // CHECK4-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ 462 // CHECK4-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { 463 // CHECK4-NEXT: entry: 464 // CHECK4-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 465 // CHECK4-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 466 // CHECK4-NEXT: call void @_Z3fn1v() 467 // CHECK4-NEXT: call void @_Z3fn2v() 468 // CHECK4-NEXT: call void @_Z3fn3v() 469 // CHECK4-NEXT: ret i32 0 470 // 471 // 472 // CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv 473 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 474 // CHECK5-NEXT: entry: 475 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 476 // CHECK5-NEXT: ret void 477 // 478 // 479 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. 480 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 481 // CHECK5-NEXT: entry: 482 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 483 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 484 // CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 485 // CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 486 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 487 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 488 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 489 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 490 // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 491 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 492 // CHECK5-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] 493 // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 494 // CHECK5-NEXT: ret void 495 // 496 // 497 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 498 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 499 // CHECK5-NEXT: entry: 500 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 501 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 502 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 503 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 504 // CHECK5-NEXT: call void @_Z9gtid_testv() 505 // CHECK5-NEXT: ret void 506 // 507 // 508 // CHECK5-LABEL: define {{[^@]+}}@main 509 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { 510 // CHECK5-NEXT: entry: 511 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 512 // CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 513 // CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 514 // CHECK5-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 515 // CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 516 // CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 517 // CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 518 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 519 // CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4 520 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) 521 // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 522 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 523 // CHECK5-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] 524 // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 525 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4 526 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 527 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 528 // CHECK5: omp_if.then: 529 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 530 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 531 // CHECK5: omp_if.else: 532 // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 533 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 534 // CHECK5-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] 535 // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 536 // CHECK5-NEXT: br label [[OMP_IF_END]] 537 // CHECK5: omp_if.end: 538 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 539 // CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) 540 // CHECK5-NEXT: ret i32 [[CALL]] 541 // 542 // 543 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 544 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 545 // CHECK5-NEXT: entry: 546 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 547 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 548 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 549 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 550 // CHECK5-NEXT: call void @_Z3fn4v() 551 // CHECK5-NEXT: ret void 552 // 553 // 554 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 555 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 556 // CHECK5-NEXT: entry: 557 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 558 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 559 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 560 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 561 // CHECK5-NEXT: call void @_Z3fn5v() 562 // CHECK5-NEXT: ret void 563 // 564 // 565 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 566 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 567 // CHECK5-NEXT: entry: 568 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 569 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 570 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 571 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 572 // CHECK5-NEXT: call void @_Z3fn6v() 573 // CHECK5-NEXT: ret void 574 // 575 // 576 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ 577 // CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { 578 // CHECK5-NEXT: entry: 579 // CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 580 // CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 581 // CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 582 // CHECK5-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 583 // CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 584 // CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 585 // CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 586 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 587 // CHECK5-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 588 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*)) 589 // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 590 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 591 // CHECK5-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] 592 // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 593 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 594 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 595 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 596 // CHECK5: omp_if.then: 597 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 598 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 599 // CHECK5: omp_if.else: 600 // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 601 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 602 // CHECK5-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] 603 // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 604 // CHECK5-NEXT: br label [[OMP_IF_END]] 605 // CHECK5: omp_if.end: 606 // CHECK5-NEXT: ret i32 0 607 // 608 // 609 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 610 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 611 // CHECK5-NEXT: entry: 612 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 613 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 614 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 615 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 616 // CHECK5-NEXT: call void @_Z3fn1v() 617 // CHECK5-NEXT: ret void 618 // 619 // 620 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 621 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 622 // CHECK5-NEXT: entry: 623 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 624 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 625 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 626 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 627 // CHECK5-NEXT: call void @_Z3fn2v() 628 // CHECK5-NEXT: ret void 629 // 630 // 631 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 632 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 633 // CHECK5-NEXT: entry: 634 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 635 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 636 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 637 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 638 // CHECK5-NEXT: call void @_Z3fn3v() 639 // CHECK5-NEXT: ret void 640 // 641 // 642 // CHECK6-LABEL: define {{[^@]+}}@_Z9gtid_testv 643 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 644 // CHECK6-NEXT: entry: 645 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 646 // CHECK6-NEXT: ret void 647 // 648 // 649 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. 650 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 651 // CHECK6-NEXT: entry: 652 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 653 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 654 // CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 655 // CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 656 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 657 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 658 // CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 659 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 660 // CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 661 // CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 662 // CHECK6-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] 663 // CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 664 // CHECK6-NEXT: ret void 665 // 666 // 667 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 668 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 669 // CHECK6-NEXT: entry: 670 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 671 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 672 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 673 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 674 // CHECK6-NEXT: call void @_Z9gtid_testv() 675 // CHECK6-NEXT: ret void 676 // 677 // 678 // CHECK6-LABEL: define {{[^@]+}}@main 679 // CHECK6-SAME: () #[[ATTR3:[0-9]+]] { 680 // CHECK6-NEXT: entry: 681 // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 682 // CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 683 // CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 684 // CHECK6-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 685 // CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 686 // CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 687 // CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 688 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 689 // CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4 690 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) 691 // CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 692 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 693 // CHECK6-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] 694 // CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 695 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4 696 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 697 // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 698 // CHECK6: omp_if.then: 699 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 700 // CHECK6-NEXT: br label [[OMP_IF_END:%.*]] 701 // CHECK6: omp_if.else: 702 // CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 703 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 704 // CHECK6-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] 705 // CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 706 // CHECK6-NEXT: br label [[OMP_IF_END]] 707 // CHECK6: omp_if.end: 708 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 709 // CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) 710 // CHECK6-NEXT: ret i32 [[CALL]] 711 // 712 // 713 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 714 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 715 // CHECK6-NEXT: entry: 716 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 717 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 718 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 719 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 720 // CHECK6-NEXT: call void @_Z3fn4v() 721 // CHECK6-NEXT: ret void 722 // 723 // 724 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 725 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 726 // CHECK6-NEXT: entry: 727 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 728 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 729 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 730 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 731 // CHECK6-NEXT: call void @_Z3fn5v() 732 // CHECK6-NEXT: ret void 733 // 734 // 735 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 736 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 737 // CHECK6-NEXT: entry: 738 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 739 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 740 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 741 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 742 // CHECK6-NEXT: call void @_Z3fn6v() 743 // CHECK6-NEXT: ret void 744 // 745 // 746 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ 747 // CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { 748 // CHECK6-NEXT: entry: 749 // CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 750 // CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 751 // CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 752 // CHECK6-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 753 // CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 754 // CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 755 // CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 756 // CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 757 // CHECK6-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 758 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*)) 759 // CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 760 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 761 // CHECK6-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] 762 // CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 763 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 764 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 765 // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 766 // CHECK6: omp_if.then: 767 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 768 // CHECK6-NEXT: br label [[OMP_IF_END:%.*]] 769 // CHECK6: omp_if.else: 770 // CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 771 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 772 // CHECK6-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] 773 // CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 774 // CHECK6-NEXT: br label [[OMP_IF_END]] 775 // CHECK6: omp_if.end: 776 // CHECK6-NEXT: ret i32 0 777 // 778 // 779 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 780 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 781 // CHECK6-NEXT: entry: 782 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 783 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 784 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 785 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 786 // CHECK6-NEXT: call void @_Z3fn1v() 787 // CHECK6-NEXT: ret void 788 // 789 // 790 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 791 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 792 // CHECK6-NEXT: entry: 793 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 794 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 795 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 796 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 797 // CHECK6-NEXT: call void @_Z3fn2v() 798 // CHECK6-NEXT: ret void 799 // 800 // 801 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 802 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 803 // CHECK6-NEXT: entry: 804 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 805 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 806 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 807 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 808 // CHECK6-NEXT: call void @_Z3fn3v() 809 // CHECK6-NEXT: ret void 810 // 811 // 812 // CHECK7-LABEL: define {{[^@]+}}@_Z9gtid_testv 813 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 814 // CHECK7-NEXT: entry: 815 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 816 // CHECK7-NEXT: ret void 817 // 818 // 819 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. 820 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 821 // CHECK7-NEXT: entry: 822 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 823 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 824 // CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 825 // CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 826 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 827 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 828 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 829 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 830 // CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 831 // CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 832 // CHECK7-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] 833 // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 834 // CHECK7-NEXT: ret void 835 // 836 // 837 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1 838 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 839 // CHECK7-NEXT: entry: 840 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 841 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 842 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 843 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 844 // CHECK7-NEXT: call void @_Z9gtid_testv() 845 // CHECK7-NEXT: ret void 846 // 847 // 848 // CHECK7-LABEL: define {{[^@]+}}@main 849 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] { 850 // CHECK7-NEXT: entry: 851 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 852 // CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 853 // CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 854 // CHECK7-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 855 // CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 856 // CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 857 // CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 858 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 859 // CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4 860 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*)) 861 // CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 862 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 863 // CHECK7-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] 864 // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 865 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4 866 // CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 867 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 868 // CHECK7: omp_if.then: 869 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 870 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 871 // CHECK7: omp_if.else: 872 // CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 873 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 874 // CHECK7-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] 875 // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 876 // CHECK7-NEXT: br label [[OMP_IF_END]] 877 // CHECK7: omp_if.end: 878 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4 879 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]]) 880 // CHECK7-NEXT: ret i32 [[CALL]] 881 // 882 // 883 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 884 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 885 // CHECK7-NEXT: entry: 886 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 887 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 888 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 889 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 890 // CHECK7-NEXT: call void @_Z3fn4v() 891 // CHECK7-NEXT: ret void 892 // 893 // 894 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 895 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 896 // CHECK7-NEXT: entry: 897 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 898 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 899 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 900 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 901 // CHECK7-NEXT: call void @_Z3fn5v() 902 // CHECK7-NEXT: ret void 903 // 904 // 905 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 906 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 907 // CHECK7-NEXT: entry: 908 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 909 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 910 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 911 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 912 // CHECK7-NEXT: call void @_Z3fn6v() 913 // CHECK7-NEXT: ret void 914 // 915 // 916 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ 917 // CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { 918 // CHECK7-NEXT: entry: 919 // CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 920 // CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 921 // CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 922 // CHECK7-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4 923 // CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4 924 // CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4 925 // CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 926 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 927 // CHECK7-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 928 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*)) 929 // CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 930 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 931 // CHECK7-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]] 932 // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 933 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4 934 // CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0 935 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 936 // CHECK7: omp_if.then: 937 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 938 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 939 // CHECK7: omp_if.else: 940 // CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 941 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4 942 // CHECK7-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]] 943 // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 944 // CHECK7-NEXT: br label [[OMP_IF_END]] 945 // CHECK7: omp_if.end: 946 // CHECK7-NEXT: ret i32 0 947 // 948 // 949 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5 950 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 951 // CHECK7-NEXT: entry: 952 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 953 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 954 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 955 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 956 // CHECK7-NEXT: call void @_Z3fn1v() 957 // CHECK7-NEXT: ret void 958 // 959 // 960 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6 961 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 962 // CHECK7-NEXT: entry: 963 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 964 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 965 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 966 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 967 // CHECK7-NEXT: call void @_Z3fn2v() 968 // CHECK7-NEXT: ret void 969 // 970 // 971 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 972 // CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 973 // CHECK7-NEXT: entry: 974 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 975 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 976 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 977 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 978 // CHECK7-NEXT: call void @_Z3fn3v() 979 // CHECK7-NEXT: ret void 980 // 981 // 982 // CHECK8-LABEL: define {{[^@]+}}@_Z9gtid_testv 983 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 984 // CHECK8-NEXT: entry: 985 // CHECK8-NEXT: call void @_Z9gtid_testv() 986 // CHECK8-NEXT: ret void 987 // 988 // 989 // CHECK8-LABEL: define {{[^@]+}}@main 990 // CHECK8-SAME: () #[[ATTR1:[0-9]+]] { 991 // CHECK8-NEXT: entry: 992 // CHECK8-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 993 // CHECK8-NEXT: store i32 0, i32* [[RETVAL]], align 4 994 // CHECK8-NEXT: call void @_Z3fn4v() 995 // CHECK8-NEXT: call void @_Z3fn5v() 996 // CHECK8-NEXT: call void @_Z3fn6v() 997 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 998 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) 999 // CHECK8-NEXT: ret i32 [[CALL]] 1000 // 1001 // 1002 // CHECK8-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ 1003 // CHECK8-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { 1004 // CHECK8-NEXT: entry: 1005 // CHECK8-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 1006 // CHECK8-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 1007 // CHECK8-NEXT: call void @_Z3fn1v() 1008 // CHECK8-NEXT: call void @_Z3fn2v() 1009 // CHECK8-NEXT: call void @_Z3fn3v() 1010 // CHECK8-NEXT: ret i32 0 1011 // 1012 // 1013 // CHECK9-LABEL: define {{[^@]+}}@_Z9gtid_testv 1014 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 1015 // CHECK9-NEXT: entry: 1016 // CHECK9-NEXT: call void @_Z9gtid_testv() 1017 // CHECK9-NEXT: ret void 1018 // 1019 // 1020 // CHECK9-LABEL: define {{[^@]+}}@main 1021 // CHECK9-SAME: () #[[ATTR1:[0-9]+]] { 1022 // CHECK9-NEXT: entry: 1023 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1024 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 1025 // CHECK9-NEXT: call void @_Z3fn4v() 1026 // CHECK9-NEXT: call void @_Z3fn5v() 1027 // CHECK9-NEXT: call void @_Z3fn6v() 1028 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* @Arg, align 4 1029 // CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP0]]) 1030 // CHECK9-NEXT: ret i32 [[CALL]] 1031 // 1032 // 1033 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ 1034 // CHECK9-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat { 1035 // CHECK9-NEXT: entry: 1036 // CHECK9-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 1037 // CHECK9-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4 1038 // CHECK9-NEXT: call void @_Z3fn1v() 1039 // CHECK9-NEXT: call void @_Z3fn2v() 1040 // CHECK9-NEXT: call void @_Z3fn3v() 1041 // CHECK9-NEXT: ret i32 0 1042 // 1043