1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK2 4 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 6 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 7 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 9 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 10 11 // RUN: %clang_cc1 -no-opaque-pointers -verify -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -gno-column-info -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -no-opaque-pointers -verify -triple x86_64-apple-darwin10 -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 13 14 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 16 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 17 // RUN: %clang_cc1 -no-opaque-pointers -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 18 // RUN: %clang_cc1 -no-opaque-pointers -verify -triple x86_64-apple-darwin10 -fopenmp-simd -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 19 // expected-no-diagnostics 20 21 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11 22 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 23 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 26 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 27 #ifndef HEADER 28 #define HEADER 29 30 #ifndef OMP5 31 32 void with_var_schedule() { 33 double a = 5; 34 35 #pragma omp parallel for schedule(static, char(a)) private(a) 36 for (unsigned long long i = 1; i < 2 + a; ++i) { 37 } 38 } 39 40 void without_schedule_clause(float *a, float *b, float *c, float *d) { 41 #pragma omp parallel for 42 // UB = min(UB, GlobalUB) 43 // Loop header 44 for (int i = 33; i < 32000000; i += 7) { 45 // Start of body: calculate i from IV: 46 // ... loop body ... 47 // End of body: store into a[i]: 48 a[i] = b[i] * c[i] * d[i]; 49 } 50 } 51 52 void static_not_chunked(float *a, float *b, float *c, float *d) { 53 #pragma omp parallel for schedule(static) 54 // UB = min(UB, GlobalUB) 55 // Loop header 56 for (int i = 32000000; i > 33; i += -7) { 57 // Start of body: calculate i from IV: 58 // ... loop body ... 59 // End of body: store into a[i]: 60 a[i] = b[i] * c[i] * d[i]; 61 } 62 } 63 64 void static_chunked(float *a, float *b, float *c, float *d) { 65 #pragma omp parallel for schedule(static, 5) 66 // UB = min(UB, GlobalUB) 67 68 // Outer loop header 69 70 // Loop header 71 for (unsigned i = 131071; i <= 2147483647; i += 127) { 72 // Start of body: calculate i from IV: 73 // ... loop body ... 74 // End of body: store into a[i]: 75 a[i] = b[i] * c[i] * d[i]; 76 } 77 // Update the counters, adding stride 78 79 } 80 81 void dynamic1(float *a, float *b, float *c, float *d) { 82 #pragma omp parallel for schedule(dynamic) 83 84 // Loop header 85 86 for (unsigned long long i = 131071; i < 2147483647; i += 127) { 87 // Start of body: calculate i from IV: 88 // ... loop body ... 89 // End of body: store into a[i]: 90 a[i] = b[i] * c[i] * d[i]; 91 } 92 } 93 94 void guided7(float *a, float *b, float *c, float *d) { 95 #pragma omp parallel for schedule(guided, 7) 96 97 // Loop header 98 99 for (unsigned long long i = 131071; i < 2147483647; i += 127) { 100 // Start of body: calculate i from IV: 101 // ... loop body ... 102 // End of body: store into a[i]: 103 a[i] = b[i] * c[i] * d[i]; 104 } 105 } 106 107 void test_auto(float *a, float *b, float *c, float *d) { 108 unsigned int x = 0; 109 unsigned int y = 0; 110 #pragma omp parallel for schedule(auto) collapse(2) 111 112 // Loop header 113 114 // FIXME: When the iteration count of some nested loop is not a known constant, 115 // we should pre-calculate it, like we do for the total number of iterations! 116 for (char i = static_cast<char>(y); i <= '9'; ++i) 117 for (x = 11; x > 0; --x) { 118 // Start of body: indices are calculated from IV: 119 // ... loop body ... 120 // End of body: store into a[i]: 121 a[i] = b[i] * c[i] * d[i]; 122 } 123 } 124 125 void runtime(float *a, float *b, float *c, float *d) { 126 int x = 0; 127 #pragma omp parallel for collapse(2) schedule(runtime) 128 129 // Loop header 130 131 for (unsigned char i = '0' ; i <= '9'; ++i) 132 for (x = -10; x < 10; ++x) { 133 // Start of body: indices are calculated from IV: 134 // ... loop body ... 135 // End of body: store into a[i]: 136 a[i] = b[i] * c[i] * d[i]; 137 } 138 } 139 140 int foo() { extern void mayThrow(); mayThrow(); return 0; }; 141 142 void parallel_for(float *a, const int n) { 143 float arr[n]; 144 #pragma omp parallel for schedule(static, 5) private(arr) default(none) firstprivate(n) shared(a) 145 for (unsigned i = 131071; i <= 2147483647; i += 127) 146 a[i] += foo() + arr[i] + n; 147 } 148 // Check source line corresponds to "#pragma omp parallel for schedule(static, 5)" above: 149 150 #else // OMP5 151 int increment () { 152 #pragma omp for 153 // Determine UB = min(UB, GlobalUB) 154 155 // Loop header 156 157 for (int i = 0 ; i != 5; ++i) 158 // Start of body: calculate i from IV: 159 ; 160 return 0; 161 } 162 163 int decrement_nowait () { 164 #pragma omp for nowait 165 // Determine UB = min(UB, GlobalUB) 166 167 // Loop header 168 for (int j = 5 ; j != 0; --j) 169 // Start of body: calculate i from IV: 170 ; 171 return 0; 172 } 173 174 void range_for_single() { 175 int arr[10] = {0}; 176 #pragma omp parallel for 177 for (auto &a : arr) 178 (void)a; 179 } 180 181 182 // __range = arr; 183 184 // __end = end(_range); 185 186 187 // calculate number of elements. 188 189 // __begin = begin(range); 190 191 // __begin >= __end ? goto then : goto exit; 192 193 194 // lb = 0; 195 196 // ub = number of elements 197 198 // stride = 1; 199 200 // is_last = 0; 201 202 // loop. 203 204 // ub = (ub > number_of_elems ? number_of_elems : ub); 205 206 207 208 // OMP%: store i64 [[MIN]], i64* [[UB]], 209 210 // iv = lb; 211 212 // goto loop; 213 // loop: 214 215 216 // iv <= ub ? goto body : goto end; 217 218 // body: 219 // __begin = begin(arr) + iv * 1; 220 221 // a = *__begin; 222 223 // (void)a; 224 225 // iv += 1; 226 227 // goto loop; 228 229 // end: 230 // exit: 231 232 void range_for_collapsed() { 233 int arr[10] = {0}; 234 #pragma omp parallel for collapse(2) 235 for (auto &a : arr) 236 for (auto b : arr) 237 a = b; 238 } 239 #endif // OMP5 240 241 #endif // HEADER 242 243 // CHECK1-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 244 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 245 // CHECK1-NEXT: entry: 246 // CHECK1-NEXT: [[A:%.*]] = alloca double, align 8 247 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 248 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 249 // CHECK1-NEXT: store double 5.000000e+00, double* [[A]], align 8 250 // CHECK1-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 251 // CHECK1-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 252 // CHECK1-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 253 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 254 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 255 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 256 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 257 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]]) 258 // CHECK1-NEXT: ret void 259 // 260 // 261 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 262 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 263 // CHECK1-NEXT: entry: 264 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 265 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 266 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 267 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 268 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 269 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 270 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 271 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 272 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 273 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 274 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 275 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 276 // CHECK1-NEXT: [[A:%.*]] = alloca double, align 8 277 // CHECK1-NEXT: [[I5:%.*]] = alloca i64, align 8 278 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 279 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 280 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 281 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 282 // CHECK1-NEXT: [[TMP0:%.*]] = load double, double* undef, align 8 283 // CHECK1-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]] 284 // CHECK1-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8 285 // CHECK1-NEXT: [[TMP1:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 286 // CHECK1-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00 287 // CHECK1-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00 288 // CHECK1-NEXT: [[CONV3:%.*]] = fptoui double [[DIV]] to i64 289 // CHECK1-NEXT: [[SUB4:%.*]] = sub i64 [[CONV3]], 1 290 // CHECK1-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_2]], align 8 291 // CHECK1-NEXT: store i64 1, i64* [[I]], align 8 292 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 293 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]] 294 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 295 // CHECK1: omp.precond.then: 296 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 297 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 298 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 299 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 300 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 301 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 302 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64 303 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 304 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 305 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]) 306 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 307 // CHECK1: omp.dispatch.cond: 308 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 309 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 310 // CHECK1-NEXT: [[CMP7:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]] 311 // CHECK1-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 312 // CHECK1: cond.true: 313 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 314 // CHECK1-NEXT: br label [[COND_END:%.*]] 315 // CHECK1: cond.false: 316 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 317 // CHECK1-NEXT: br label [[COND_END]] 318 // CHECK1: cond.end: 319 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 320 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 321 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 322 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 323 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 324 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 325 // CHECK1-NEXT: [[ADD8:%.*]] = add i64 [[TMP13]], 1 326 // CHECK1-NEXT: [[CMP9:%.*]] = icmp ult i64 [[TMP12]], [[ADD8]] 327 // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 328 // CHECK1: omp.dispatch.body: 329 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 330 // CHECK1: omp.inner.for.cond: 331 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 332 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 333 // CHECK1-NEXT: [[ADD10:%.*]] = add i64 [[TMP15]], 1 334 // CHECK1-NEXT: [[CMP11:%.*]] = icmp ult i64 [[TMP14]], [[ADD10]] 335 // CHECK1-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 336 // CHECK1: omp.inner.for.body: 337 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 338 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1 339 // CHECK1-NEXT: [[ADD12:%.*]] = add i64 1, [[MUL]] 340 // CHECK1-NEXT: store i64 [[ADD12]], i64* [[I5]], align 8 341 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 342 // CHECK1: omp.body.continue: 343 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 344 // CHECK1: omp.inner.for.inc: 345 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 346 // CHECK1-NEXT: [[ADD13:%.*]] = add i64 [[TMP17]], 1 347 // CHECK1-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_IV]], align 8 348 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 349 // CHECK1: omp.inner.for.end: 350 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 351 // CHECK1: omp.dispatch.inc: 352 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 353 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 354 // CHECK1-NEXT: [[ADD14:%.*]] = add i64 [[TMP18]], [[TMP19]] 355 // CHECK1-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_LB]], align 8 356 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 357 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 358 // CHECK1-NEXT: [[ADD15:%.*]] = add i64 [[TMP20]], [[TMP21]] 359 // CHECK1-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_UB]], align 8 360 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 361 // CHECK1: omp.dispatch.end: 362 // CHECK1-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 363 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 364 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 365 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 366 // CHECK1: omp.precond.end: 367 // CHECK1-NEXT: ret void 368 // 369 // 370 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 371 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 372 // CHECK1-NEXT: entry: 373 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 374 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 375 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 376 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 377 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 378 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 379 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 380 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 381 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 382 // CHECK1-NEXT: ret void 383 // 384 // 385 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 386 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 387 // CHECK1-NEXT: entry: 388 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 389 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 390 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 391 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 392 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 393 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 394 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 395 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 396 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 397 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 398 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 399 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 400 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 401 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 402 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 403 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 404 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 405 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 406 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 407 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 408 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 409 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 410 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 411 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 412 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 413 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 414 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 415 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 416 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 417 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 418 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 419 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 420 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 421 // CHECK1: cond.true: 422 // CHECK1-NEXT: br label [[COND_END:%.*]] 423 // CHECK1: cond.false: 424 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 425 // CHECK1-NEXT: br label [[COND_END]] 426 // CHECK1: cond.end: 427 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 428 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 429 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 430 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 431 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 432 // CHECK1: omp.inner.for.cond: 433 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 434 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 435 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 436 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 437 // CHECK1: omp.inner.for.body: 438 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 439 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 440 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 441 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 442 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 443 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 444 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 445 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 446 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 447 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 448 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 449 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 450 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 451 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 452 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 453 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 454 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 455 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 456 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 457 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 458 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 459 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 460 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 461 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 462 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 463 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 464 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 465 // CHECK1: omp.body.continue: 466 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 467 // CHECK1: omp.inner.for.inc: 468 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 469 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 470 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 471 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 472 // CHECK1: omp.inner.for.end: 473 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 474 // CHECK1: omp.loop.exit: 475 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 476 // CHECK1-NEXT: ret void 477 // 478 // 479 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 480 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 481 // CHECK1-NEXT: entry: 482 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 483 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 484 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 485 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 486 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 487 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 488 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 489 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 490 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 491 // CHECK1-NEXT: ret void 492 // 493 // 494 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 495 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 496 // CHECK1-NEXT: entry: 497 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 498 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 499 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 500 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 501 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 502 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 503 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 504 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 505 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 506 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 507 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 508 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 509 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 510 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 511 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 512 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 513 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 514 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 515 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 516 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 517 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 518 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 519 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 520 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 521 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 522 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 523 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 524 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 525 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 526 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 527 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 528 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 529 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 530 // CHECK1: cond.true: 531 // CHECK1-NEXT: br label [[COND_END:%.*]] 532 // CHECK1: cond.false: 533 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 534 // CHECK1-NEXT: br label [[COND_END]] 535 // CHECK1: cond.end: 536 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 537 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 538 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 539 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 540 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 541 // CHECK1: omp.inner.for.cond: 542 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 543 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 544 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 545 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 546 // CHECK1: omp.inner.for.body: 547 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 548 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 549 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 550 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4 551 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 552 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 553 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 554 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 555 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 556 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 557 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 558 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 559 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 560 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 561 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 562 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 563 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 564 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 565 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 566 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 567 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 568 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 569 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 570 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 571 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 572 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 573 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 574 // CHECK1: omp.body.continue: 575 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 576 // CHECK1: omp.inner.for.inc: 577 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 578 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 579 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 580 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 581 // CHECK1: omp.inner.for.end: 582 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 583 // CHECK1: omp.loop.exit: 584 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 585 // CHECK1-NEXT: ret void 586 // 587 // 588 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 589 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 590 // CHECK1-NEXT: entry: 591 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 592 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 593 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 594 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 595 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 596 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 597 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 598 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 599 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 600 // CHECK1-NEXT: ret void 601 // 602 // 603 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 604 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 605 // CHECK1-NEXT: entry: 606 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 607 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 608 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 609 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 610 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 611 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 612 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 613 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 614 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 615 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 616 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 617 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 618 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 619 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 620 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 621 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 622 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 623 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 624 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 625 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 626 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 627 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 628 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 629 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 630 // CHECK1-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 631 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 632 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 633 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 634 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 635 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 636 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 637 // CHECK1: omp.dispatch.cond: 638 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 639 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 640 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 641 // CHECK1: cond.true: 642 // CHECK1-NEXT: br label [[COND_END:%.*]] 643 // CHECK1: cond.false: 644 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 645 // CHECK1-NEXT: br label [[COND_END]] 646 // CHECK1: cond.end: 647 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 648 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 649 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 650 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 651 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 652 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 653 // CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 654 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 655 // CHECK1: omp.dispatch.body: 656 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 657 // CHECK1: omp.inner.for.cond: 658 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 659 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 660 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 661 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 662 // CHECK1: omp.inner.for.body: 663 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 664 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 665 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 666 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 667 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8 668 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 669 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 670 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 671 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4 672 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8 673 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 674 // CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 675 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 676 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4 677 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 678 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8 679 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 680 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 681 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 682 // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4 683 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 684 // CHECK1-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8 685 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 686 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 687 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 688 // CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 689 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 690 // CHECK1: omp.body.continue: 691 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 692 // CHECK1: omp.inner.for.inc: 693 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 694 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 695 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 696 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 697 // CHECK1: omp.inner.for.end: 698 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 699 // CHECK1: omp.dispatch.inc: 700 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 701 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 702 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 703 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 704 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 705 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 706 // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 707 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 708 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 709 // CHECK1: omp.dispatch.end: 710 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 711 // CHECK1-NEXT: ret void 712 // 713 // 714 // CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 715 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 716 // CHECK1-NEXT: entry: 717 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 718 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 719 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 720 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 721 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 722 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 723 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 724 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 725 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 726 // CHECK1-NEXT: ret void 727 // 728 // 729 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 730 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 731 // CHECK1-NEXT: entry: 732 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 733 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 734 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 735 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 736 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 737 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 738 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 739 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 740 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 741 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 742 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 743 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 744 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 745 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 746 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 747 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 748 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 749 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 750 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 751 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 752 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 753 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 754 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 755 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 756 // CHECK1-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 757 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 758 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 759 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 760 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 761 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1) 762 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 763 // CHECK1: omp.dispatch.cond: 764 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 765 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 766 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 767 // CHECK1: omp.dispatch.body: 768 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 769 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 770 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 771 // CHECK1: omp.inner.for.cond: 772 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 773 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 774 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 775 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 776 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 777 // CHECK1: omp.inner.for.body: 778 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 779 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 780 // CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 781 // CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5 782 // CHECK1-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !5 783 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 784 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 785 // CHECK1-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !5 786 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !5 787 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 788 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 789 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !5 790 // CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 791 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !5 792 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 793 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 794 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !5 795 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 796 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !5 797 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 798 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 799 // CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5 800 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 801 // CHECK1: omp.body.continue: 802 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 803 // CHECK1: omp.inner.for.inc: 804 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 805 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 806 // CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 807 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 808 // CHECK1: omp.inner.for.end: 809 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 810 // CHECK1: omp.dispatch.inc: 811 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 812 // CHECK1: omp.dispatch.end: 813 // CHECK1-NEXT: ret void 814 // 815 // 816 // CHECK1-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 817 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 818 // CHECK1-NEXT: entry: 819 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 820 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 821 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 822 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 823 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 824 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 825 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 826 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 827 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..5 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 828 // CHECK1-NEXT: ret void 829 // 830 // 831 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 832 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 833 // CHECK1-NEXT: entry: 834 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 835 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 836 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 837 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 838 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 839 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 840 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 841 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 842 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 843 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 844 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 845 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 846 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 847 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 848 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 849 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 850 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 851 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 852 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 853 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 854 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 855 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 856 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 857 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 858 // CHECK1-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 859 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 860 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 861 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 862 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 863 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7) 864 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 865 // CHECK1: omp.dispatch.cond: 866 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 867 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 868 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 869 // CHECK1: omp.dispatch.body: 870 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 871 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 872 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 873 // CHECK1: omp.inner.for.cond: 874 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 875 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !8 876 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 877 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 878 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 879 // CHECK1: omp.inner.for.body: 880 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 881 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 882 // CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 883 // CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8 884 // CHECK1-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !8 885 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 886 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 887 // CHECK1-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8 888 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8 889 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 890 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 891 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !8 892 // CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 893 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !8 894 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 895 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 896 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !8 897 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 898 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !8 899 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 900 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 901 // CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8 902 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 903 // CHECK1: omp.body.continue: 904 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 905 // CHECK1: omp.inner.for.inc: 906 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 907 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 908 // CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 909 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 910 // CHECK1: omp.inner.for.end: 911 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 912 // CHECK1: omp.dispatch.inc: 913 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 914 // CHECK1: omp.dispatch.end: 915 // CHECK1-NEXT: ret void 916 // 917 // 918 // CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 919 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 920 // CHECK1-NEXT: entry: 921 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 922 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 923 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 924 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 925 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 926 // CHECK1-NEXT: [[Y:%.*]] = alloca i32, align 4 927 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 928 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 929 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 930 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 931 // CHECK1-NEXT: store i32 0, i32* [[X]], align 4 932 // CHECK1-NEXT: store i32 0, i32* [[Y]], align 4 933 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[Y]], float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 934 // CHECK1-NEXT: ret void 935 // 936 // 937 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 938 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 939 // CHECK1-NEXT: entry: 940 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 941 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 942 // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 943 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 944 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 945 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 946 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 947 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 948 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 949 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 950 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 951 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 952 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 953 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 954 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 955 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 956 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 957 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 958 // CHECK1-NEXT: [[I7:%.*]] = alloca i8, align 1 959 // CHECK1-NEXT: [[X8:%.*]] = alloca i32, align 4 960 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 961 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 962 // CHECK1-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8 963 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 964 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 965 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 966 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 967 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[Y_ADDR]], align 8 968 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[A_ADDR]], align 8 969 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[B_ADDR]], align 8 970 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[C_ADDR]], align 8 971 // CHECK1-NEXT: [[TMP4:%.*]] = load float**, float*** [[D_ADDR]], align 8 972 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 973 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8 974 // CHECK1-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 975 // CHECK1-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 976 // CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32 977 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 978 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 979 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 980 // CHECK1-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 981 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 982 // CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 983 // CHECK1-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 984 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 985 // CHECK1-NEXT: store i8 [[TMP7]], i8* [[I]], align 1 986 // CHECK1-NEXT: store i32 11, i32* [[X]], align 4 987 // CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 988 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32 989 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57 990 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 991 // CHECK1: omp.precond.then: 992 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 993 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 994 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 995 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 996 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 997 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 998 // CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 999 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1000 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1) 1001 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1002 // CHECK1: omp.dispatch.cond: 1003 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1004 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 1005 // CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1006 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 1007 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1008 // CHECK1: omp.dispatch.body: 1009 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1010 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 1011 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1012 // CHECK1: omp.inner.for.cond: 1013 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 1014 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !11 1015 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 1016 // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1017 // CHECK1: omp.inner.for.body: 1018 // CHECK1-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11 1019 // CHECK1-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64 1020 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 1021 // CHECK1-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11 1022 // CHECK1-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1 1023 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]] 1024 // CHECK1-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8 1025 // CHECK1-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11 1026 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 1027 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 1028 // CHECK1-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11 1029 // CHECK1-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11 1030 // CHECK1-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]] 1031 // CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1 1032 // CHECK1-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]] 1033 // CHECK1-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32 1034 // CHECK1-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11 1035 // CHECK1-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !11 1036 // CHECK1-NEXT: [[TMP24:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 1037 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64 1038 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM]] 1039 // CHECK1-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 1040 // CHECK1-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !11 1041 // CHECK1-NEXT: [[TMP27:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 1042 // CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64 1043 // CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM21]] 1044 // CHECK1-NEXT: [[TMP28:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !llvm.access.group !11 1045 // CHECK1-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]] 1046 // CHECK1-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !11 1047 // CHECK1-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 1048 // CHECK1-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64 1049 // CHECK1-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM24]] 1050 // CHECK1-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !llvm.access.group !11 1051 // CHECK1-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]] 1052 // CHECK1-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !11 1053 // CHECK1-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 1054 // CHECK1-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64 1055 // CHECK1-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM27]] 1056 // CHECK1-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11 1057 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1058 // CHECK1: omp.body.continue: 1059 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1060 // CHECK1: omp.inner.for.inc: 1061 // CHECK1-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 1062 // CHECK1-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1 1063 // CHECK1-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 1064 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 1065 // CHECK1: omp.inner.for.end: 1066 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1067 // CHECK1: omp.dispatch.inc: 1068 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1069 // CHECK1: omp.dispatch.end: 1070 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 1071 // CHECK1: omp.precond.end: 1072 // CHECK1-NEXT: ret void 1073 // 1074 // 1075 // CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 1076 // CHECK1-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1077 // CHECK1-NEXT: entry: 1078 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1079 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1080 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1081 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1082 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 1083 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1084 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1085 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1086 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1087 // CHECK1-NEXT: store i32 0, i32* [[X]], align 4 1088 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1089 // CHECK1-NEXT: ret void 1090 // 1091 // 1092 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 1093 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1094 // CHECK1-NEXT: entry: 1095 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1096 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1097 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1098 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1099 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1100 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1101 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1102 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 1103 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1104 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1105 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1106 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1107 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1108 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 1109 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 1110 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1111 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1112 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1113 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1114 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1115 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1116 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1117 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1118 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1119 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1120 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1121 // CHECK1-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 1122 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1123 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1124 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1125 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1126 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1) 1127 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1128 // CHECK1: omp.dispatch.cond: 1129 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1130 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 1131 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1132 // CHECK1: omp.dispatch.body: 1133 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1134 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 1135 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1136 // CHECK1: omp.inner.for.cond: 1137 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1138 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 1139 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 1140 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1141 // CHECK1: omp.inner.for.body: 1142 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1143 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20 1144 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1145 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 1146 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 1147 // CHECK1-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14 1148 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1149 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1150 // CHECK1-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20 1151 // CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20 1152 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]] 1153 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 1154 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]] 1155 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14 1156 // CHECK1-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !14 1157 // CHECK1-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 1158 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64 1159 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] 1160 // CHECK1-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !14 1161 // CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !14 1162 // CHECK1-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 1163 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64 1164 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM6]] 1165 // CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !14 1166 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]] 1167 // CHECK1-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !14 1168 // CHECK1-NEXT: [[TMP20:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 1169 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64 1170 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM9]] 1171 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 1172 // CHECK1-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]] 1173 // CHECK1-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !14 1174 // CHECK1-NEXT: [[TMP23:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 1175 // CHECK1-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64 1176 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM12]] 1177 // CHECK1-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14 1178 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1179 // CHECK1: omp.body.continue: 1180 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1181 // CHECK1: omp.inner.for.inc: 1182 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1183 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1 1184 // CHECK1-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1185 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 1186 // CHECK1: omp.inner.for.end: 1187 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1188 // CHECK1: omp.dispatch.inc: 1189 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1190 // CHECK1: omp.dispatch.end: 1191 // CHECK1-NEXT: ret void 1192 // 1193 // 1194 // CHECK1-LABEL: define {{[^@]+}}@_Z3foov 1195 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 1196 // CHECK1-NEXT: entry: 1197 // CHECK1-NEXT: call void @_Z8mayThrowv() 1198 // CHECK1-NEXT: ret i32 0 1199 // 1200 // 1201 // CHECK1-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 1202 // CHECK1-SAME: (float* noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] { 1203 // CHECK1-NEXT: entry: 1204 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1205 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1206 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1207 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1208 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1209 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1210 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1211 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1212 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1213 // CHECK1-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1214 // CHECK1-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 1215 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 1216 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1217 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1218 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1219 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 1220 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 1221 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), float** [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]) 1222 // CHECK1-NEXT: [[TMP5:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1223 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP5]]) 1224 // CHECK1-NEXT: ret void 1225 // 1226 // 1227 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 1228 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { 1229 // CHECK1-NEXT: entry: 1230 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1231 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1232 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1233 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1234 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1235 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1236 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1237 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1238 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1239 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1240 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1241 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1242 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1243 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1244 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1245 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1246 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1247 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1248 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1249 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1250 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1251 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1252 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1253 // CHECK1-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 1254 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1255 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1256 // CHECK1-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1257 // CHECK1-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 1258 // CHECK1-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16 1259 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1260 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1261 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 1262 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 1263 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1264 // CHECK1: omp.dispatch.cond: 1265 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1266 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288 1267 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1268 // CHECK1: cond.true: 1269 // CHECK1-NEXT: br label [[COND_END:%.*]] 1270 // CHECK1: cond.false: 1271 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1272 // CHECK1-NEXT: br label [[COND_END]] 1273 // CHECK1: cond.end: 1274 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 1275 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1276 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1277 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 1278 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1279 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1280 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]] 1281 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]] 1282 // CHECK1: omp.dispatch.cleanup: 1283 // CHECK1-NEXT: br label [[OMP_DISPATCH_END:%.*]] 1284 // CHECK1: omp.dispatch.body: 1285 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1286 // CHECK1: omp.inner.for.cond: 1287 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1288 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1289 // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]] 1290 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1291 // CHECK1: omp.inner.for.cond.cleanup: 1292 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1293 // CHECK1: omp.inner.for.body: 1294 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1295 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127 1296 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 1297 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1298 // CHECK1-NEXT: [[CALL:%.*]] = invoke noundef i32 @_Z3foov() 1299 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1300 // CHECK1: invoke.cont: 1301 // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float 1302 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1303 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 1304 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] 1305 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1306 // CHECK1-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]] 1307 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4 1308 // CHECK1-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float 1309 // CHECK1-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] 1310 // CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8 1311 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 1312 // CHECK1-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64 1313 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]] 1314 // CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4 1315 // CHECK1-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]] 1316 // CHECK1-NEXT: store float [[ADD10]], float* [[ARRAYIDX9]], align 4 1317 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1318 // CHECK1: omp.body.continue: 1319 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1320 // CHECK1: omp.inner.for.inc: 1321 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1322 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP19]], 1 1323 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 1324 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1325 // CHECK1: omp.inner.for.end: 1326 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1327 // CHECK1: omp.dispatch.inc: 1328 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1329 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1330 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP20]], [[TMP21]] 1331 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 1332 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1333 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1334 // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP22]], [[TMP23]] 1335 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 1336 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1337 // CHECK1: omp.dispatch.end: 1338 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) 1339 // CHECK1-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1340 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) 1341 // CHECK1-NEXT: ret void 1342 // CHECK1: terminate.lpad: 1343 // CHECK1-NEXT: [[TMP25:%.*]] = landingpad { i8*, i32 } 1344 // CHECK1-NEXT: catch i8* null 1345 // CHECK1-NEXT: [[TMP26:%.*]] = extractvalue { i8*, i32 } [[TMP25]], 0 1346 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP26]]) #[[ATTR7:[0-9]+]] 1347 // CHECK1-NEXT: unreachable 1348 // 1349 // 1350 // CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate 1351 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 1352 // CHECK1-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 1353 // CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 1354 // CHECK1-NEXT: unreachable 1355 // 1356 // 1357 // CHECK2-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 1358 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 1359 // CHECK2-NEXT: entry: 1360 // CHECK2-NEXT: [[A:%.*]] = alloca double, align 8 1361 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1362 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1363 // CHECK2-NEXT: store double 5.000000e+00, double* [[A]], align 8 1364 // CHECK2-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 1365 // CHECK2-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 1366 // CHECK2-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 1367 // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1368 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 1369 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 1370 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 1371 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]]) 1372 // CHECK2-NEXT: ret void 1373 // 1374 // 1375 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1376 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 1377 // CHECK2-NEXT: entry: 1378 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1379 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1380 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1381 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1382 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 1383 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 1384 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 1385 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 1386 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1387 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1388 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1389 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1390 // CHECK2-NEXT: [[A:%.*]] = alloca double, align 8 1391 // CHECK2-NEXT: [[I5:%.*]] = alloca i64, align 8 1392 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1393 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1394 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1395 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 1396 // CHECK2-NEXT: [[TMP0:%.*]] = load double, double* undef, align 8 1397 // CHECK2-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]] 1398 // CHECK2-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8 1399 // CHECK2-NEXT: [[TMP1:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 1400 // CHECK2-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00 1401 // CHECK2-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00 1402 // CHECK2-NEXT: [[CONV3:%.*]] = fptoui double [[DIV]] to i64 1403 // CHECK2-NEXT: [[SUB4:%.*]] = sub i64 [[CONV3]], 1 1404 // CHECK2-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_2]], align 8 1405 // CHECK2-NEXT: store i64 1, i64* [[I]], align 8 1406 // CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 1407 // CHECK2-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]] 1408 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1409 // CHECK2: omp.precond.then: 1410 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1411 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1412 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 1413 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1414 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1415 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 1416 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64 1417 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1418 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 1419 // CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]) 1420 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1421 // CHECK2: omp.dispatch.cond: 1422 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1423 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1424 // CHECK2-NEXT: [[CMP7:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]] 1425 // CHECK2-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1426 // CHECK2: cond.true: 1427 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1428 // CHECK2-NEXT: br label [[COND_END:%.*]] 1429 // CHECK2: cond.false: 1430 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1431 // CHECK2-NEXT: br label [[COND_END]] 1432 // CHECK2: cond.end: 1433 // CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 1434 // CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1435 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1436 // CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 1437 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1438 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1439 // CHECK2-NEXT: [[ADD8:%.*]] = add i64 [[TMP13]], 1 1440 // CHECK2-NEXT: [[CMP9:%.*]] = icmp ult i64 [[TMP12]], [[ADD8]] 1441 // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1442 // CHECK2: omp.dispatch.body: 1443 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1444 // CHECK2: omp.inner.for.cond: 1445 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1446 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1447 // CHECK2-NEXT: [[ADD10:%.*]] = add i64 [[TMP15]], 1 1448 // CHECK2-NEXT: [[CMP11:%.*]] = icmp ult i64 [[TMP14]], [[ADD10]] 1449 // CHECK2-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1450 // CHECK2: omp.inner.for.body: 1451 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1452 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1 1453 // CHECK2-NEXT: [[ADD12:%.*]] = add i64 1, [[MUL]] 1454 // CHECK2-NEXT: store i64 [[ADD12]], i64* [[I5]], align 8 1455 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1456 // CHECK2: omp.body.continue: 1457 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1458 // CHECK2: omp.inner.for.inc: 1459 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1460 // CHECK2-NEXT: [[ADD13:%.*]] = add i64 [[TMP17]], 1 1461 // CHECK2-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_IV]], align 8 1462 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1463 // CHECK2: omp.inner.for.end: 1464 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1465 // CHECK2: omp.dispatch.inc: 1466 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1467 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 1468 // CHECK2-NEXT: [[ADD14:%.*]] = add i64 [[TMP18]], [[TMP19]] 1469 // CHECK2-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_LB]], align 8 1470 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1471 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 1472 // CHECK2-NEXT: [[ADD15:%.*]] = add i64 [[TMP20]], [[TMP21]] 1473 // CHECK2-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_UB]], align 8 1474 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1475 // CHECK2: omp.dispatch.end: 1476 // CHECK2-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1477 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 1478 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 1479 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 1480 // CHECK2: omp.precond.end: 1481 // CHECK2-NEXT: ret void 1482 // 1483 // 1484 // CHECK2-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 1485 // CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1486 // CHECK2-NEXT: entry: 1487 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1488 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1489 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1490 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1491 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1492 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1493 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1494 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1495 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1496 // CHECK2-NEXT: ret void 1497 // 1498 // 1499 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 1500 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1501 // CHECK2-NEXT: entry: 1502 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1503 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1504 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1505 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1506 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1507 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1508 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1509 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1510 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1511 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1512 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1513 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1514 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1515 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1516 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1517 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1518 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1519 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1520 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1521 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1522 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1523 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1524 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1525 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1526 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1527 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1528 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1529 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1530 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1531 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1532 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1533 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1534 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1535 // CHECK2: cond.true: 1536 // CHECK2-NEXT: br label [[COND_END:%.*]] 1537 // CHECK2: cond.false: 1538 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1539 // CHECK2-NEXT: br label [[COND_END]] 1540 // CHECK2: cond.end: 1541 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1542 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1543 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1544 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1545 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1546 // CHECK2: omp.inner.for.cond: 1547 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1548 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1549 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1550 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1551 // CHECK2: omp.inner.for.body: 1552 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1553 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1554 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 1555 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1556 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 1557 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1558 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 1559 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 1560 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1561 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 1562 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1563 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 1564 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 1565 // CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 1566 // CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 1567 // CHECK2-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 1568 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1569 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 1570 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 1571 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 1572 // CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 1573 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 1574 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1575 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 1576 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 1577 // CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 1578 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1579 // CHECK2: omp.body.continue: 1580 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1581 // CHECK2: omp.inner.for.inc: 1582 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1583 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 1584 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 1585 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1586 // CHECK2: omp.inner.for.end: 1587 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1588 // CHECK2: omp.loop.exit: 1589 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1590 // CHECK2-NEXT: ret void 1591 // 1592 // 1593 // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1594 // CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1595 // CHECK2-NEXT: entry: 1596 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1597 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1598 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1599 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1600 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1601 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1602 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1603 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1604 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1605 // CHECK2-NEXT: ret void 1606 // 1607 // 1608 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 1609 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1610 // CHECK2-NEXT: entry: 1611 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1612 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1613 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1614 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1615 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1616 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1617 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1618 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1619 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1620 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1621 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1622 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1623 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1624 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1625 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1626 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1627 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1628 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1629 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1630 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1631 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1632 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1633 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1634 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1635 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1636 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1637 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1638 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1639 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1640 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1641 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1642 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1643 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1644 // CHECK2: cond.true: 1645 // CHECK2-NEXT: br label [[COND_END:%.*]] 1646 // CHECK2: cond.false: 1647 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1648 // CHECK2-NEXT: br label [[COND_END]] 1649 // CHECK2: cond.end: 1650 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1651 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1652 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1653 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1654 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1655 // CHECK2: omp.inner.for.cond: 1656 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1657 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1658 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1659 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1660 // CHECK2: omp.inner.for.body: 1661 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1662 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1663 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1664 // CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1665 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 1666 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1667 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 1668 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 1669 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1670 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 1671 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1672 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 1673 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 1674 // CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 1675 // CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 1676 // CHECK2-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 1677 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1678 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 1679 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 1680 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 1681 // CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 1682 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 1683 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1684 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 1685 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 1686 // CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 1687 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1688 // CHECK2: omp.body.continue: 1689 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1690 // CHECK2: omp.inner.for.inc: 1691 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1692 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 1693 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1694 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1695 // CHECK2: omp.inner.for.end: 1696 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1697 // CHECK2: omp.loop.exit: 1698 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1699 // CHECK2-NEXT: ret void 1700 // 1701 // 1702 // CHECK2-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 1703 // CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1704 // CHECK2-NEXT: entry: 1705 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1706 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1707 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1708 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1709 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1710 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1711 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1712 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1713 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1714 // CHECK2-NEXT: ret void 1715 // 1716 // 1717 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 1718 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1719 // CHECK2-NEXT: entry: 1720 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1721 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1722 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1723 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1724 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1725 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1726 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1727 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1728 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1729 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1730 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1731 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1732 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1733 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1734 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1735 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1736 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1737 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1738 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1739 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1740 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1741 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1742 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1743 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1744 // CHECK2-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 1745 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1746 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1747 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1748 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1749 // CHECK2-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 1750 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1751 // CHECK2: omp.dispatch.cond: 1752 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1753 // CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 1754 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1755 // CHECK2: cond.true: 1756 // CHECK2-NEXT: br label [[COND_END:%.*]] 1757 // CHECK2: cond.false: 1758 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1759 // CHECK2-NEXT: br label [[COND_END]] 1760 // CHECK2: cond.end: 1761 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1762 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1763 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1764 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1765 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1766 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1767 // CHECK2-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 1768 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1769 // CHECK2: omp.dispatch.body: 1770 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1771 // CHECK2: omp.inner.for.cond: 1772 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1773 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1774 // CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 1775 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1776 // CHECK2: omp.inner.for.body: 1777 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1778 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 1779 // CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 1780 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1781 // CHECK2-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8 1782 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 1783 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 1784 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 1785 // CHECK2-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4 1786 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8 1787 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 1788 // CHECK2-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 1789 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 1790 // CHECK2-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1791 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 1792 // CHECK2-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8 1793 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 1794 // CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 1795 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 1796 // CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4 1797 // CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 1798 // CHECK2-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8 1799 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 1800 // CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 1801 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 1802 // CHECK2-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 1803 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1804 // CHECK2: omp.body.continue: 1805 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1806 // CHECK2: omp.inner.for.inc: 1807 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1808 // CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 1809 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 1810 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1811 // CHECK2: omp.inner.for.end: 1812 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1813 // CHECK2: omp.dispatch.inc: 1814 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1815 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1816 // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 1817 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 1818 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1819 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1820 // CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 1821 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 1822 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1823 // CHECK2: omp.dispatch.end: 1824 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1825 // CHECK2-NEXT: ret void 1826 // 1827 // 1828 // CHECK2-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 1829 // CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1830 // CHECK2-NEXT: entry: 1831 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1832 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1833 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1834 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1835 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1836 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1837 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1838 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1839 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1840 // CHECK2-NEXT: ret void 1841 // 1842 // 1843 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 1844 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1845 // CHECK2-NEXT: entry: 1846 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1847 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1848 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1849 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1850 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1851 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1852 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1853 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 1854 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1855 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1856 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1857 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1858 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 1859 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1860 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1861 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1862 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1863 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1864 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1865 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1866 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1867 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1868 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1869 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1870 // CHECK2-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 1871 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1872 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1873 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1874 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1875 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 35, i64 0, i64 16908287, i64 1, i64 1) 1876 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1877 // CHECK2: omp.dispatch.cond: 1878 // CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1879 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 1880 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1881 // CHECK2: omp.dispatch.body: 1882 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1883 // CHECK2-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 1884 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1885 // CHECK2: omp.inner.for.cond: 1886 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1887 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 1888 // CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 1889 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 1890 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1891 // CHECK2: omp.inner.for.body: 1892 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1893 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 1894 // CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 1895 // CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5 1896 // CHECK2-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !5 1897 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 1898 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 1899 // CHECK2-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !5 1900 // CHECK2-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !5 1901 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 1902 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 1903 // CHECK2-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !5 1904 // CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 1905 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !5 1906 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 1907 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 1908 // CHECK2-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !5 1909 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 1910 // CHECK2-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !5 1911 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 1912 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 1913 // CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5 1914 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1915 // CHECK2: omp.body.continue: 1916 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1917 // CHECK2: omp.inner.for.inc: 1918 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1919 // CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 1920 // CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1921 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 1922 // CHECK2: omp.inner.for.end: 1923 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1924 // CHECK2: omp.dispatch.inc: 1925 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1926 // CHECK2: omp.dispatch.end: 1927 // CHECK2-NEXT: ret void 1928 // 1929 // 1930 // CHECK2-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 1931 // CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 1932 // CHECK2-NEXT: entry: 1933 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1934 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1935 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1936 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1937 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1938 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1939 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1940 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1941 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..5 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1942 // CHECK2-NEXT: ret void 1943 // 1944 // 1945 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 1946 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1947 // CHECK2-NEXT: entry: 1948 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1949 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1950 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1951 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1952 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1953 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1954 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1955 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 1956 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1957 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1958 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1959 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1960 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 1961 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1962 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1963 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1964 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1965 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1966 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1967 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1968 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1969 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1970 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1971 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1972 // CHECK2-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 1973 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1974 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1975 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1976 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1977 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 36, i64 0, i64 16908287, i64 1, i64 7) 1978 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1979 // CHECK2: omp.dispatch.cond: 1980 // CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1981 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 1982 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1983 // CHECK2: omp.dispatch.body: 1984 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1985 // CHECK2-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 1986 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1987 // CHECK2: omp.inner.for.cond: 1988 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 1989 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !8 1990 // CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 1991 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 1992 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1993 // CHECK2: omp.inner.for.body: 1994 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 1995 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 1996 // CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 1997 // CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8 1998 // CHECK2-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !8 1999 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 2000 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 2001 // CHECK2-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8 2002 // CHECK2-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8 2003 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 2004 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 2005 // CHECK2-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !8 2006 // CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 2007 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !8 2008 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 2009 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 2010 // CHECK2-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !8 2011 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 2012 // CHECK2-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !8 2013 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 2014 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 2015 // CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8 2016 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2017 // CHECK2: omp.body.continue: 2018 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2019 // CHECK2: omp.inner.for.inc: 2020 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 2021 // CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 2022 // CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 2023 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 2024 // CHECK2: omp.inner.for.end: 2025 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2026 // CHECK2: omp.dispatch.inc: 2027 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2028 // CHECK2: omp.dispatch.end: 2029 // CHECK2-NEXT: ret void 2030 // 2031 // 2032 // CHECK2-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 2033 // CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2034 // CHECK2-NEXT: entry: 2035 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2036 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2037 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2038 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2039 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 2040 // CHECK2-NEXT: [[Y:%.*]] = alloca i32, align 4 2041 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2042 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2043 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2044 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2045 // CHECK2-NEXT: store i32 0, i32* [[X]], align 4 2046 // CHECK2-NEXT: store i32 0, i32* [[Y]], align 4 2047 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[Y]], float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2048 // CHECK2-NEXT: ret void 2049 // 2050 // 2051 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 2052 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2053 // CHECK2-NEXT: entry: 2054 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2055 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2056 // CHECK2-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 2057 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2058 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2059 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2060 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2061 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2062 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 2063 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2064 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2065 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 2066 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 2067 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 2068 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2069 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2070 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2071 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2072 // CHECK2-NEXT: [[I7:%.*]] = alloca i8, align 1 2073 // CHECK2-NEXT: [[X8:%.*]] = alloca i32, align 4 2074 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2075 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2076 // CHECK2-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8 2077 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2078 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2079 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2080 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2081 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[Y_ADDR]], align 8 2082 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[A_ADDR]], align 8 2083 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[B_ADDR]], align 8 2084 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[C_ADDR]], align 8 2085 // CHECK2-NEXT: [[TMP4:%.*]] = load float**, float*** [[D_ADDR]], align 8 2086 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 2087 // CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8 2088 // CHECK2-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 2089 // CHECK2-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2090 // CHECK2-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32 2091 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 2092 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 2093 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2094 // CHECK2-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 2095 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 2096 // CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 2097 // CHECK2-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 2098 // CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2099 // CHECK2-NEXT: store i8 [[TMP7]], i8* [[I]], align 1 2100 // CHECK2-NEXT: store i32 11, i32* [[X]], align 4 2101 // CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2102 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32 2103 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57 2104 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2105 // CHECK2: omp.precond.then: 2106 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2107 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2108 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 2109 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2110 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2111 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2112 // CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2113 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 2114 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 38, i64 0, i64 [[TMP10]], i64 1, i64 1) 2115 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2116 // CHECK2: omp.dispatch.cond: 2117 // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2118 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 2119 // CHECK2-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2120 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 2121 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2122 // CHECK2: omp.dispatch.body: 2123 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2124 // CHECK2-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 2125 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2126 // CHECK2: omp.inner.for.cond: 2127 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 2128 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !11 2129 // CHECK2-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 2130 // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2131 // CHECK2: omp.inner.for.body: 2132 // CHECK2-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11 2133 // CHECK2-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64 2134 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 2135 // CHECK2-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11 2136 // CHECK2-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1 2137 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]] 2138 // CHECK2-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8 2139 // CHECK2-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11 2140 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 2141 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 2142 // CHECK2-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11 2143 // CHECK2-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11 2144 // CHECK2-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]] 2145 // CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1 2146 // CHECK2-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]] 2147 // CHECK2-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32 2148 // CHECK2-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11 2149 // CHECK2-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !11 2150 // CHECK2-NEXT: [[TMP24:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 2151 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64 2152 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM]] 2153 // CHECK2-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 2154 // CHECK2-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !11 2155 // CHECK2-NEXT: [[TMP27:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 2156 // CHECK2-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64 2157 // CHECK2-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM21]] 2158 // CHECK2-NEXT: [[TMP28:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !llvm.access.group !11 2159 // CHECK2-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]] 2160 // CHECK2-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !11 2161 // CHECK2-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 2162 // CHECK2-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64 2163 // CHECK2-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM24]] 2164 // CHECK2-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !llvm.access.group !11 2165 // CHECK2-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]] 2166 // CHECK2-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !11 2167 // CHECK2-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 2168 // CHECK2-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64 2169 // CHECK2-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM27]] 2170 // CHECK2-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11 2171 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2172 // CHECK2: omp.body.continue: 2173 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2174 // CHECK2: omp.inner.for.inc: 2175 // CHECK2-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 2176 // CHECK2-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1 2177 // CHECK2-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 2178 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 2179 // CHECK2: omp.inner.for.end: 2180 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2181 // CHECK2: omp.dispatch.inc: 2182 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2183 // CHECK2: omp.dispatch.end: 2184 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 2185 // CHECK2: omp.precond.end: 2186 // CHECK2-NEXT: ret void 2187 // 2188 // 2189 // CHECK2-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 2190 // CHECK2-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 2191 // CHECK2-NEXT: entry: 2192 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2193 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2194 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2195 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2196 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 2197 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2198 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2199 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2200 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2201 // CHECK2-NEXT: store i32 0, i32* [[X]], align 4 2202 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2203 // CHECK2-NEXT: ret void 2204 // 2205 // 2206 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 2207 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2208 // CHECK2-NEXT: entry: 2209 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2210 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2211 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2212 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2213 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2214 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2215 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2216 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 2217 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2218 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2219 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2220 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2221 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2222 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 2223 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 2224 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2225 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2226 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2227 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2228 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2229 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2230 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2231 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 2232 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 2233 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 2234 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2235 // CHECK2-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 2236 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2237 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2238 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2239 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2240 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 37, i32 0, i32 199, i32 1, i32 1) 2241 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2242 // CHECK2: omp.dispatch.cond: 2243 // CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2244 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 2245 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2246 // CHECK2: omp.dispatch.body: 2247 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2248 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 2249 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2250 // CHECK2: omp.inner.for.cond: 2251 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2252 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 2253 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 2254 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2255 // CHECK2: omp.inner.for.body: 2256 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2257 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20 2258 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2259 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 2260 // CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 2261 // CHECK2-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14 2262 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2263 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2264 // CHECK2-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20 2265 // CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20 2266 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]] 2267 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 2268 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]] 2269 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14 2270 // CHECK2-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !14 2271 // CHECK2-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 2272 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64 2273 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] 2274 // CHECK2-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !14 2275 // CHECK2-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !14 2276 // CHECK2-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 2277 // CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64 2278 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM6]] 2279 // CHECK2-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !14 2280 // CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]] 2281 // CHECK2-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !14 2282 // CHECK2-NEXT: [[TMP20:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 2283 // CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64 2284 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM9]] 2285 // CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 2286 // CHECK2-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]] 2287 // CHECK2-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !14 2288 // CHECK2-NEXT: [[TMP23:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 2289 // CHECK2-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64 2290 // CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM12]] 2291 // CHECK2-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14 2292 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2293 // CHECK2: omp.body.continue: 2294 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2295 // CHECK2: omp.inner.for.inc: 2296 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2297 // CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1 2298 // CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2299 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 2300 // CHECK2: omp.inner.for.end: 2301 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2302 // CHECK2: omp.dispatch.inc: 2303 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2304 // CHECK2: omp.dispatch.end: 2305 // CHECK2-NEXT: ret void 2306 // 2307 // 2308 // CHECK2-LABEL: define {{[^@]+}}@_Z3foov 2309 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 2310 // CHECK2-NEXT: entry: 2311 // CHECK2-NEXT: call void @_Z8mayThrowv() 2312 // CHECK2-NEXT: ret i32 0 2313 // 2314 // 2315 // CHECK2-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 2316 // CHECK2-SAME: (float* noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] { 2317 // CHECK2-NEXT: entry: 2318 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2319 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2320 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2321 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2322 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 2323 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2324 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2325 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2326 // CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 2327 // CHECK2-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2328 // CHECK2-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 2329 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 2330 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 2331 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2332 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 2333 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 2334 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 2335 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), float** [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]) 2336 // CHECK2-NEXT: [[TMP5:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2337 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP5]]) 2338 // CHECK2-NEXT: ret void 2339 // 2340 // 2341 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 2342 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { 2343 // CHECK2-NEXT: entry: 2344 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2345 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2346 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2347 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2348 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 2349 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2350 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 2351 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2352 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2353 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2354 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2355 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2356 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2357 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 2358 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2359 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2360 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2361 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2362 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 2363 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2364 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2365 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 2366 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2367 // CHECK2-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 2368 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2369 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2370 // CHECK2-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2371 // CHECK2-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 2372 // CHECK2-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16 2373 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 2374 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2375 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 2376 // CHECK2-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 2377 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2378 // CHECK2: omp.dispatch.cond: 2379 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2380 // CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288 2381 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2382 // CHECK2: cond.true: 2383 // CHECK2-NEXT: br label [[COND_END:%.*]] 2384 // CHECK2: cond.false: 2385 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2386 // CHECK2-NEXT: br label [[COND_END]] 2387 // CHECK2: cond.end: 2388 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 2389 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2390 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2391 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 2392 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2393 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2394 // CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]] 2395 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]] 2396 // CHECK2: omp.dispatch.cleanup: 2397 // CHECK2-NEXT: br label [[OMP_DISPATCH_END:%.*]] 2398 // CHECK2: omp.dispatch.body: 2399 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2400 // CHECK2: omp.inner.for.cond: 2401 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2402 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2403 // CHECK2-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]] 2404 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2405 // CHECK2: omp.inner.for.cond.cleanup: 2406 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2407 // CHECK2: omp.inner.for.body: 2408 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2409 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127 2410 // CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 2411 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2412 // CHECK2-NEXT: [[CALL:%.*]] = invoke noundef i32 @_Z3foov() 2413 // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 2414 // CHECK2: invoke.cont: 2415 // CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float 2416 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2417 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 2418 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] 2419 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2420 // CHECK2-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]] 2421 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4 2422 // CHECK2-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float 2423 // CHECK2-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] 2424 // CHECK2-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8 2425 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 2426 // CHECK2-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64 2427 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]] 2428 // CHECK2-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4 2429 // CHECK2-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]] 2430 // CHECK2-NEXT: store float [[ADD10]], float* [[ARRAYIDX9]], align 4 2431 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2432 // CHECK2: omp.body.continue: 2433 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2434 // CHECK2: omp.inner.for.inc: 2435 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2436 // CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP19]], 1 2437 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 2438 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2439 // CHECK2: omp.inner.for.end: 2440 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2441 // CHECK2: omp.dispatch.inc: 2442 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2443 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2444 // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP20]], [[TMP21]] 2445 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 2446 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2447 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2448 // CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP22]], [[TMP23]] 2449 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 2450 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2451 // CHECK2: omp.dispatch.end: 2452 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) 2453 // CHECK2-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2454 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) 2455 // CHECK2-NEXT: ret void 2456 // CHECK2: terminate.lpad: 2457 // CHECK2-NEXT: [[TMP25:%.*]] = landingpad { i8*, i32 } 2458 // CHECK2-NEXT: catch i8* null 2459 // CHECK2-NEXT: [[TMP26:%.*]] = extractvalue { i8*, i32 } [[TMP25]], 0 2460 // CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP26]]) #[[ATTR7:[0-9]+]] 2461 // CHECK2-NEXT: unreachable 2462 // 2463 // 2464 // CHECK2-LABEL: define {{[^@]+}}@__clang_call_terminate 2465 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 2466 // CHECK2-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 2467 // CHECK2-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 2468 // CHECK2-NEXT: unreachable 2469 // 2470 // 2471 // CHECK5-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 2472 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { 2473 // CHECK5-NEXT: entry: 2474 // CHECK5-NEXT: [[A:%.*]] = alloca double, align 8 2475 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2476 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 2477 // CHECK5-NEXT: store double 5.000000e+00, double* [[A]], align 8, !dbg [[DBG10:![0-9]+]] 2478 // CHECK5-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8, !dbg [[DBG11:![0-9]+]] 2479 // CHECK5-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8, !dbg [[DBG11]] 2480 // CHECK5-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11]] 2481 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11]] 2482 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*, !dbg [[DBG11]] 2483 // CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1, !dbg [[DBG11]] 2484 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !dbg [[DBG11]] 2485 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]]), !dbg [[DBG11]] 2486 // CHECK5-NEXT: ret void, !dbg [[DBG12:![0-9]+]] 2487 // 2488 // 2489 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. 2490 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG13:![0-9]+]] { 2491 // CHECK5-NEXT: entry: 2492 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2493 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2494 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2495 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2496 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 2497 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 2498 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 2499 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 2500 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2501 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2502 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2503 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2504 // CHECK5-NEXT: [[A:%.*]] = alloca double, align 8 2505 // CHECK5-NEXT: [[I5:%.*]] = alloca i64, align 8 2506 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2507 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2508 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2509 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*, !dbg [[DBG14:![0-9]+]] 2510 // CHECK5-NEXT: [[TMP0:%.*]] = load double, double* undef, align 8, !dbg [[DBG15:![0-9]+]] 2511 // CHECK5-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]], !dbg [[DBG15]] 2512 // CHECK5-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG15]] 2513 // CHECK5-NEXT: [[TMP1:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG15]] 2514 // CHECK5-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00, !dbg [[DBG15]] 2515 // CHECK5-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00, !dbg [[DBG15]] 2516 // CHECK5-NEXT: [[CONV3:%.*]] = fptoui double [[DIV]] to i64, !dbg [[DBG15]] 2517 // CHECK5-NEXT: [[SUB4:%.*]] = sub i64 [[CONV3]], 1, !dbg [[DBG15]] 2518 // CHECK5-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]] 2519 // CHECK5-NEXT: store i64 1, i64* [[I]], align 8, !dbg [[DBG15]] 2520 // CHECK5-NEXT: [[TMP2:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG15]] 2521 // CHECK5-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]], !dbg [[DBG15]] 2522 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG14]] 2523 // CHECK5: omp.precond.then: 2524 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG15]] 2525 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]] 2526 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 2527 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG15]] 2528 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG15]] 2529 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1, !dbg [[DBG14]] 2530 // CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64, !dbg [[DBG14]] 2531 // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG14]] 2532 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG14]] 2533 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]), !dbg [[DBG14]] 2534 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG14]] 2535 // CHECK5: omp.dispatch.cond: 2536 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 2537 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]] 2538 // CHECK5-NEXT: [[CMP7:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]], !dbg [[DBG15]] 2539 // CHECK5-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG15]] 2540 // CHECK5: cond.true: 2541 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]] 2542 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG15]] 2543 // CHECK5: cond.false: 2544 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 2545 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG15]] 2546 // CHECK5: cond.end: 2547 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ], !dbg [[DBG15]] 2548 // CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 2549 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG15]] 2550 // CHECK5-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]] 2551 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]] 2552 // CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 2553 // CHECK5-NEXT: [[ADD8:%.*]] = add i64 [[TMP13]], 1, !dbg [[DBG15]] 2554 // CHECK5-NEXT: [[CMP9:%.*]] = icmp ult i64 [[TMP12]], [[ADD8]], !dbg [[DBG15]] 2555 // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG14]] 2556 // CHECK5: omp.dispatch.body: 2557 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG14]] 2558 // CHECK5: omp.inner.for.cond: 2559 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]] 2560 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 2561 // CHECK5-NEXT: [[ADD10:%.*]] = add i64 [[TMP15]], 1, !dbg [[DBG15]] 2562 // CHECK5-NEXT: [[CMP11:%.*]] = icmp ult i64 [[TMP14]], [[ADD10]], !dbg [[DBG15]] 2563 // CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG14]] 2564 // CHECK5: omp.inner.for.body: 2565 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]] 2566 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1, !dbg [[DBG15]] 2567 // CHECK5-NEXT: [[ADD12:%.*]] = add i64 1, [[MUL]], !dbg [[DBG15]] 2568 // CHECK5-NEXT: store i64 [[ADD12]], i64* [[I5]], align 8, !dbg [[DBG15]] 2569 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG16:![0-9]+]] 2570 // CHECK5: omp.body.continue: 2571 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG14]] 2572 // CHECK5: omp.inner.for.inc: 2573 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]] 2574 // CHECK5-NEXT: [[ADD13:%.*]] = add i64 [[TMP17]], 1, !dbg [[DBG15]] 2575 // CHECK5-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]] 2576 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG14]], !llvm.loop [[LOOP17:![0-9]+]] 2577 // CHECK5: omp.inner.for.end: 2578 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG14]] 2579 // CHECK5: omp.dispatch.inc: 2580 // CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG15]] 2581 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG15]] 2582 // CHECK5-NEXT: [[ADD14:%.*]] = add i64 [[TMP18]], [[TMP19]], !dbg [[DBG15]] 2583 // CHECK5-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_LB]], align 8, !dbg [[DBG15]] 2584 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 2585 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG15]] 2586 // CHECK5-NEXT: [[ADD15:%.*]] = add i64 [[TMP20]], [[TMP21]], !dbg [[DBG15]] 2587 // CHECK5-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 2588 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG14]], !llvm.loop [[LOOP18:![0-9]+]] 2589 // CHECK5: omp.dispatch.end: 2590 // CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG14]] 2591 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4, !dbg [[DBG14]] 2592 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP23]]), !dbg [[DBG14]] 2593 // CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG14]] 2594 // CHECK5: omp.precond.end: 2595 // CHECK5-NEXT: ret void, !dbg [[DBG16]] 2596 // 2597 // 2598 // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 2599 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG21:![0-9]+]] { 2600 // CHECK5-NEXT: entry: 2601 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2602 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2603 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2604 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2605 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2606 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2607 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2608 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2609 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB9:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG22:![0-9]+]] 2610 // CHECK5-NEXT: ret void, !dbg [[DBG23:![0-9]+]] 2611 // 2612 // 2613 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 2614 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG24:![0-9]+]] { 2615 // CHECK5-NEXT: entry: 2616 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2617 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2618 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2619 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2620 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2621 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2622 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2623 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2624 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2625 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2626 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2627 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2628 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2629 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2630 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2631 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2632 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2633 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2634 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2635 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG25:![0-9]+]] 2636 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG25]] 2637 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG25]] 2638 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG25]] 2639 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG26:![0-9]+]] 2640 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG26]] 2641 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG26]] 2642 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG26]] 2643 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG25]] 2644 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG25]] 2645 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB6:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG25]] 2646 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG26]] 2647 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG26]] 2648 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG26]] 2649 // CHECK5: cond.true: 2650 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG26]] 2651 // CHECK5: cond.false: 2652 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG26]] 2653 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG26]] 2654 // CHECK5: cond.end: 2655 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG26]] 2656 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG26]] 2657 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG26]] 2658 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG26]] 2659 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG25]] 2660 // CHECK5: omp.inner.for.cond: 2661 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG26]] 2662 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG26]] 2663 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG26]] 2664 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG25]] 2665 // CHECK5: omp.inner.for.body: 2666 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG26]] 2667 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG26]] 2668 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]], !dbg [[DBG26]] 2669 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG26]] 2670 // CHECK5-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG27:![0-9]+]] 2671 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG27]] 2672 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG27]] 2673 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG27]] 2674 // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG27]] 2675 // CHECK5-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG27]] 2676 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG27]] 2677 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG27]] 2678 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG27]] 2679 // CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !dbg [[DBG27]] 2680 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG27]] 2681 // CHECK5-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG27]] 2682 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG27]] 2683 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG27]] 2684 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG27]] 2685 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !dbg [[DBG27]] 2686 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG27]] 2687 // CHECK5-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG27]] 2688 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG27]] 2689 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG27]] 2690 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG27]] 2691 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG27]] 2692 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG28:![0-9]+]] 2693 // CHECK5: omp.body.continue: 2694 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG25]] 2695 // CHECK5: omp.inner.for.inc: 2696 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG26]] 2697 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG26]] 2698 // CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG26]] 2699 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG25]], !llvm.loop [[LOOP29:![0-9]+]] 2700 // CHECK5: omp.inner.for.end: 2701 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG25]] 2702 // CHECK5: omp.loop.exit: 2703 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB8:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG25]] 2704 // CHECK5-NEXT: ret void, !dbg [[DBG28]] 2705 // 2706 // 2707 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 2708 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG30:![0-9]+]] { 2709 // CHECK5-NEXT: entry: 2710 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2711 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2712 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2713 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2714 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2715 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2716 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2717 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2718 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB14:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG31:![0-9]+]] 2719 // CHECK5-NEXT: ret void, !dbg [[DBG32:![0-9]+]] 2720 // 2721 // 2722 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 2723 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG33:![0-9]+]] { 2724 // CHECK5-NEXT: entry: 2725 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2726 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2727 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2728 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2729 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2730 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2731 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2732 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2733 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2734 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2735 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2736 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2737 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2738 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2739 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2740 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2741 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2742 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2743 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2744 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG34:![0-9]+]] 2745 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG34]] 2746 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG34]] 2747 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG34]] 2748 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG35:![0-9]+]] 2749 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG35]] 2750 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG35]] 2751 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG35]] 2752 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG34]] 2753 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG34]] 2754 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB11:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG34]] 2755 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG35]] 2756 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG35]] 2757 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG35]] 2758 // CHECK5: cond.true: 2759 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG35]] 2760 // CHECK5: cond.false: 2761 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG35]] 2762 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG35]] 2763 // CHECK5: cond.end: 2764 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG35]] 2765 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG35]] 2766 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG35]] 2767 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG35]] 2768 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG34]] 2769 // CHECK5: omp.inner.for.cond: 2770 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG35]] 2771 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG35]] 2772 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG35]] 2773 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG34]] 2774 // CHECK5: omp.inner.for.body: 2775 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG35]] 2776 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG35]] 2777 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]], !dbg [[DBG35]] 2778 // CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !dbg [[DBG35]] 2779 // CHECK5-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG36:![0-9]+]] 2780 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36]] 2781 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG36]] 2782 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG36]] 2783 // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG36]] 2784 // CHECK5-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG36]] 2785 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36]] 2786 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG36]] 2787 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG36]] 2788 // CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !dbg [[DBG36]] 2789 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG36]] 2790 // CHECK5-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG36]] 2791 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36]] 2792 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG36]] 2793 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG36]] 2794 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !dbg [[DBG36]] 2795 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG36]] 2796 // CHECK5-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG36]] 2797 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36]] 2798 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG36]] 2799 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG36]] 2800 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG36]] 2801 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG37:![0-9]+]] 2802 // CHECK5: omp.body.continue: 2803 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG34]] 2804 // CHECK5: omp.inner.for.inc: 2805 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG35]] 2806 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG35]] 2807 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG35]] 2808 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG34]], !llvm.loop [[LOOP38:![0-9]+]] 2809 // CHECK5: omp.inner.for.end: 2810 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG34]] 2811 // CHECK5: omp.loop.exit: 2812 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB13:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG34]] 2813 // CHECK5-NEXT: ret void, !dbg [[DBG37]] 2814 // 2815 // 2816 // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 2817 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG39:![0-9]+]] { 2818 // CHECK5-NEXT: entry: 2819 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2820 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2821 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2822 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2823 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2824 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2825 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2826 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2827 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB19:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG40:![0-9]+]] 2828 // CHECK5-NEXT: ret void, !dbg [[DBG41:![0-9]+]] 2829 // 2830 // 2831 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 2832 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG42:![0-9]+]] { 2833 // CHECK5-NEXT: entry: 2834 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2835 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2836 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2837 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2838 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2839 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2840 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2841 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 2842 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2843 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2844 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2845 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2846 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 2847 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2848 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2849 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2850 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2851 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2852 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2853 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG43:![0-9]+]] 2854 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG43]] 2855 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG43]] 2856 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG43]] 2857 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG44:![0-9]+]] 2858 // CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 2859 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]] 2860 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG44]] 2861 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG43]] 2862 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG43]] 2863 // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB16:[0-9]+]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG43]] 2864 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG43]] 2865 // CHECK5: omp.dispatch.cond: 2866 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 2867 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288, !dbg [[DBG44]] 2868 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG44]] 2869 // CHECK5: cond.true: 2870 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG44]] 2871 // CHECK5: cond.false: 2872 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 2873 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG44]] 2874 // CHECK5: cond.end: 2875 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG44]] 2876 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 2877 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG44]] 2878 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]] 2879 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]] 2880 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 2881 // CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]], !dbg [[DBG44]] 2882 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG43]] 2883 // CHECK5: omp.dispatch.body: 2884 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG43]] 2885 // CHECK5: omp.inner.for.cond: 2886 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]] 2887 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 2888 // CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]], !dbg [[DBG44]] 2889 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG43]] 2890 // CHECK5: omp.inner.for.body: 2891 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]] 2892 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127, !dbg [[DBG44]] 2893 // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG44]] 2894 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG44]] 2895 // CHECK5-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG45:![0-9]+]] 2896 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG45]] 2897 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64, !dbg [[DBG45]] 2898 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]], !dbg [[DBG45]] 2899 // CHECK5-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG45]] 2900 // CHECK5-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG45]] 2901 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG45]] 2902 // CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64, !dbg [[DBG45]] 2903 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]], !dbg [[DBG45]] 2904 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG45]] 2905 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]], !dbg [[DBG45]] 2906 // CHECK5-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG45]] 2907 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG45]] 2908 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64, !dbg [[DBG45]] 2909 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]], !dbg [[DBG45]] 2910 // CHECK5-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !dbg [[DBG45]] 2911 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]], !dbg [[DBG45]] 2912 // CHECK5-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG45]] 2913 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG45]] 2914 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64, !dbg [[DBG45]] 2915 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]], !dbg [[DBG45]] 2916 // CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !dbg [[DBG45]] 2917 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG46:![0-9]+]] 2918 // CHECK5: omp.body.continue: 2919 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG43]] 2920 // CHECK5: omp.inner.for.inc: 2921 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]] 2922 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1, !dbg [[DBG44]] 2923 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]] 2924 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG43]], !llvm.loop [[LOOP47:![0-9]+]] 2925 // CHECK5: omp.inner.for.end: 2926 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG43]] 2927 // CHECK5: omp.dispatch.inc: 2928 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG44]] 2929 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]] 2930 // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]], !dbg [[DBG44]] 2931 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG44]] 2932 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 2933 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]] 2934 // CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]], !dbg [[DBG44]] 2935 // CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 2936 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG43]], !llvm.loop [[LOOP48:![0-9]+]] 2937 // CHECK5: omp.dispatch.end: 2938 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB18:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG43]] 2939 // CHECK5-NEXT: ret void, !dbg [[DBG46]] 2940 // 2941 // 2942 // CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 2943 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG49:![0-9]+]] { 2944 // CHECK5-NEXT: entry: 2945 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2946 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2947 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2948 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2949 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2950 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2951 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2952 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2953 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB21:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG50:![0-9]+]] 2954 // CHECK5-NEXT: ret void, !dbg [[DBG51:![0-9]+]] 2955 // 2956 // 2957 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 2958 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG52:![0-9]+]] { 2959 // CHECK5-NEXT: entry: 2960 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2961 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2962 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2963 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2964 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2965 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2966 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2967 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 2968 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2969 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2970 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2971 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2972 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 2973 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2974 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2975 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2976 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2977 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2978 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2979 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG53:![0-9]+]] 2980 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG53]] 2981 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG53]] 2982 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG53]] 2983 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG54:![0-9]+]] 2984 // CHECK5-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG54]] 2985 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG54]] 2986 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG54]] 2987 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG53]] 2988 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG53]] 2989 // CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB21]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1), !dbg [[DBG53]] 2990 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG53]] 2991 // CHECK5: omp.dispatch.cond: 2992 // CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB21]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG53]] 2993 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG53]] 2994 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG53]] 2995 // CHECK5: omp.dispatch.body: 2996 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG54]] 2997 // CHECK5-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG54]] 2998 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG53]] 2999 // CHECK5: omp.inner.for.cond: 3000 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group !55 3001 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG54]], !llvm.access.group !55 3002 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG54]] 3003 // CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG54]] 3004 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG53]] 3005 // CHECK5: omp.inner.for.body: 3006 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group !55 3007 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG54]] 3008 // CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG54]] 3009 // CHECK5-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !dbg [[DBG54]], !llvm.access.group !55 3010 // CHECK5-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG56:![0-9]+]], !llvm.access.group !55 3011 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG56]], !llvm.access.group !55 3012 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]], !dbg [[DBG56]] 3013 // CHECK5-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG56]], !llvm.access.group !55 3014 // CHECK5-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG56]], !llvm.access.group !55 3015 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG56]], !llvm.access.group !55 3016 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]], !dbg [[DBG56]] 3017 // CHECK5-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG56]], !llvm.access.group !55 3018 // CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG56]] 3019 // CHECK5-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG56]], !llvm.access.group !55 3020 // CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG56]], !llvm.access.group !55 3021 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]], !dbg [[DBG56]] 3022 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG56]], !llvm.access.group !55 3023 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG56]] 3024 // CHECK5-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG56]], !llvm.access.group !55 3025 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG56]], !llvm.access.group !55 3026 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]], !dbg [[DBG56]] 3027 // CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG56]], !llvm.access.group !55 3028 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG57:![0-9]+]] 3029 // CHECK5: omp.body.continue: 3030 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG53]] 3031 // CHECK5: omp.inner.for.inc: 3032 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group !55 3033 // CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG54]] 3034 // CHECK5-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group !55 3035 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG53]], !llvm.loop [[LOOP58:![0-9]+]] 3036 // CHECK5: omp.inner.for.end: 3037 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG53]] 3038 // CHECK5: omp.dispatch.inc: 3039 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG53]], !llvm.loop [[LOOP60:![0-9]+]] 3040 // CHECK5: omp.dispatch.end: 3041 // CHECK5-NEXT: ret void, !dbg [[DBG57]] 3042 // 3043 // 3044 // CHECK5-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 3045 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG61:![0-9]+]] { 3046 // CHECK5-NEXT: entry: 3047 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3048 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3049 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3050 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3051 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3052 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3053 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3054 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3055 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB23:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..5 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG62:![0-9]+]] 3056 // CHECK5-NEXT: ret void, !dbg [[DBG63:![0-9]+]] 3057 // 3058 // 3059 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 3060 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG64:![0-9]+]] { 3061 // CHECK5-NEXT: entry: 3062 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3063 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3064 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3065 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3066 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3067 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3068 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3069 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 3070 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3071 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3072 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3073 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3074 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 3075 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3076 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3077 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3078 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3079 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3080 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3081 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG65:![0-9]+]] 3082 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG65]] 3083 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG65]] 3084 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG65]] 3085 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG66:![0-9]+]] 3086 // CHECK5-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG66]] 3087 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG66]] 3088 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG66]] 3089 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG65]] 3090 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG65]] 3091 // CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB23]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7), !dbg [[DBG65]] 3092 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG65]] 3093 // CHECK5: omp.dispatch.cond: 3094 // CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB23]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG65]] 3095 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG65]] 3096 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG65]] 3097 // CHECK5: omp.dispatch.body: 3098 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG66]] 3099 // CHECK5-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG66]] 3100 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG65]] 3101 // CHECK5: omp.inner.for.cond: 3102 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group !67 3103 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG66]], !llvm.access.group !67 3104 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG66]] 3105 // CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG66]] 3106 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG65]] 3107 // CHECK5: omp.inner.for.body: 3108 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group !67 3109 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG66]] 3110 // CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG66]] 3111 // CHECK5-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !dbg [[DBG66]], !llvm.access.group !67 3112 // CHECK5-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG68:![0-9]+]], !llvm.access.group !67 3113 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG68]], !llvm.access.group !67 3114 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]], !dbg [[DBG68]] 3115 // CHECK5-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG68]], !llvm.access.group !67 3116 // CHECK5-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG68]], !llvm.access.group !67 3117 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG68]], !llvm.access.group !67 3118 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]], !dbg [[DBG68]] 3119 // CHECK5-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG68]], !llvm.access.group !67 3120 // CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG68]] 3121 // CHECK5-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG68]], !llvm.access.group !67 3122 // CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG68]], !llvm.access.group !67 3123 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]], !dbg [[DBG68]] 3124 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG68]], !llvm.access.group !67 3125 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG68]] 3126 // CHECK5-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG68]], !llvm.access.group !67 3127 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG68]], !llvm.access.group !67 3128 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]], !dbg [[DBG68]] 3129 // CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG68]], !llvm.access.group !67 3130 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG69:![0-9]+]] 3131 // CHECK5: omp.body.continue: 3132 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG65]] 3133 // CHECK5: omp.inner.for.inc: 3134 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group !67 3135 // CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG66]] 3136 // CHECK5-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group !67 3137 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG65]], !llvm.loop [[LOOP70:![0-9]+]] 3138 // CHECK5: omp.inner.for.end: 3139 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG65]] 3140 // CHECK5: omp.dispatch.inc: 3141 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG65]], !llvm.loop [[LOOP72:![0-9]+]] 3142 // CHECK5: omp.dispatch.end: 3143 // CHECK5-NEXT: ret void, !dbg [[DBG69]] 3144 // 3145 // 3146 // CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 3147 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG73:![0-9]+]] { 3148 // CHECK5-NEXT: entry: 3149 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3150 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3151 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3152 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3153 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 3154 // CHECK5-NEXT: [[Y:%.*]] = alloca i32, align 4 3155 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3156 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3157 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3158 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3159 // CHECK5-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG74:![0-9]+]] 3160 // CHECK5-NEXT: store i32 0, i32* [[Y]], align 4, !dbg [[DBG75:![0-9]+]] 3161 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB25:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[Y]], float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG76:![0-9]+]] 3162 // CHECK5-NEXT: ret void, !dbg [[DBG77:![0-9]+]] 3163 // 3164 // 3165 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 3166 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG78:![0-9]+]] { 3167 // CHECK5-NEXT: entry: 3168 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3169 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3170 // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 3171 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3172 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3173 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3174 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3175 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3176 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 3177 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3178 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3179 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 3180 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 3181 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 3182 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3183 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3184 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3185 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3186 // CHECK5-NEXT: [[I7:%.*]] = alloca i8, align 1 3187 // CHECK5-NEXT: [[X8:%.*]] = alloca i32, align 4 3188 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3189 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3190 // CHECK5-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8 3191 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3192 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3193 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3194 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3195 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[Y_ADDR]], align 8, !dbg [[DBG79:![0-9]+]] 3196 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG79]] 3197 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG79]] 3198 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG79]] 3199 // CHECK5-NEXT: [[TMP4:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG79]] 3200 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4, !dbg [[DBG80:![0-9]+]] 3201 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8, !dbg [[DBG80]] 3202 // CHECK5-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]] 3203 // CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]] 3204 // CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32, !dbg [[DBG80]] 3205 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]], !dbg [[DBG80]] 3206 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1, !dbg [[DBG80]] 3207 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1, !dbg [[DBG80]] 3208 // CHECK5-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64, !dbg [[DBG80]] 3209 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11, !dbg [[DBG81:![0-9]+]] 3210 // CHECK5-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1, !dbg [[DBG81]] 3211 // CHECK5-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG80]] 3212 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]] 3213 // CHECK5-NEXT: store i8 [[TMP7]], i8* [[I]], align 1, !dbg [[DBG80]] 3214 // CHECK5-NEXT: store i32 11, i32* [[X]], align 4, !dbg [[DBG81]] 3215 // CHECK5-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]] 3216 // CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32, !dbg [[DBG80]] 3217 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57, !dbg [[DBG80]] 3218 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG79]] 3219 // CHECK5: omp.precond.then: 3220 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG80]] 3221 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG81]] 3222 // CHECK5-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG80]] 3223 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG80]] 3224 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG80]] 3225 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG81]] 3226 // CHECK5-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]] 3227 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4, !dbg [[DBG79]] 3228 // CHECK5-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB25]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1), !dbg [[DBG79]] 3229 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG79]] 3230 // CHECK5: omp.dispatch.cond: 3231 // CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]] 3232 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4, !dbg [[DBG79]] 3233 // CHECK5-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB25]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG79]] 3234 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0, !dbg [[DBG79]] 3235 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG79]] 3236 // CHECK5: omp.dispatch.body: 3237 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG80]] 3238 // CHECK5-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]] 3239 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG79]] 3240 // CHECK5: omp.inner.for.cond: 3241 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82 3242 // CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG80]], !llvm.access.group !82 3243 // CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]], !dbg [[DBG80]] 3244 // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG79]] 3245 // CHECK5: omp.inner.for.body: 3246 // CHECK5-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]], !llvm.access.group !82 3247 // CHECK5-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64, !dbg [[DBG80]] 3248 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82 3249 // CHECK5-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11, !dbg [[DBG80]] 3250 // CHECK5-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1, !dbg [[DBG80]] 3251 // CHECK5-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]], !dbg [[DBG80]] 3252 // CHECK5-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8, !dbg [[DBG80]] 3253 // CHECK5-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !dbg [[DBG80]], !llvm.access.group !82 3254 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82 3255 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82 3256 // CHECK5-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11, !dbg [[DBG80]] 3257 // CHECK5-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11, !dbg [[DBG80]] 3258 // CHECK5-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]], !dbg [[DBG80]] 3259 // CHECK5-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1, !dbg [[DBG81]] 3260 // CHECK5-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]], !dbg [[DBG81]] 3261 // CHECK5-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32, !dbg [[DBG81]] 3262 // CHECK5-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !dbg [[DBG81]], !llvm.access.group !82 3263 // CHECK5-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG83:![0-9]+]], !llvm.access.group !82 3264 // CHECK5-NEXT: [[TMP24:%.*]] = load i8, i8* [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group !82 3265 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64, !dbg [[DBG83]] 3266 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM]], !dbg [[DBG83]] 3267 // CHECK5-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG83]], !llvm.access.group !82 3268 // CHECK5-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG83]], !llvm.access.group !82 3269 // CHECK5-NEXT: [[TMP27:%.*]] = load i8, i8* [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group !82 3270 // CHECK5-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64, !dbg [[DBG83]] 3271 // CHECK5-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM21]], !dbg [[DBG83]] 3272 // CHECK5-NEXT: [[TMP28:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !dbg [[DBG83]], !llvm.access.group !82 3273 // CHECK5-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]], !dbg [[DBG83]] 3274 // CHECK5-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP4]], align 8, !dbg [[DBG83]], !llvm.access.group !82 3275 // CHECK5-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group !82 3276 // CHECK5-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64, !dbg [[DBG83]] 3277 // CHECK5-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM24]], !dbg [[DBG83]] 3278 // CHECK5-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !dbg [[DBG83]], !llvm.access.group !82 3279 // CHECK5-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]], !dbg [[DBG83]] 3280 // CHECK5-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG83]], !llvm.access.group !82 3281 // CHECK5-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group !82 3282 // CHECK5-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64, !dbg [[DBG83]] 3283 // CHECK5-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM27]], !dbg [[DBG83]] 3284 // CHECK5-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !dbg [[DBG83]], !llvm.access.group !82 3285 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG84:![0-9]+]] 3286 // CHECK5: omp.body.continue: 3287 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG79]] 3288 // CHECK5: omp.inner.for.inc: 3289 // CHECK5-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82 3290 // CHECK5-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1, !dbg [[DBG80]] 3291 // CHECK5-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82 3292 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG79]], !llvm.loop [[LOOP85:![0-9]+]] 3293 // CHECK5: omp.inner.for.end: 3294 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG79]] 3295 // CHECK5: omp.dispatch.inc: 3296 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG79]], !llvm.loop [[LOOP87:![0-9]+]] 3297 // CHECK5: omp.dispatch.end: 3298 // CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG79]] 3299 // CHECK5: omp.precond.end: 3300 // CHECK5-NEXT: ret void, !dbg [[DBG84]] 3301 // 3302 // 3303 // CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 3304 // CHECK5-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG88:![0-9]+]] { 3305 // CHECK5-NEXT: entry: 3306 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3307 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3308 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3309 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3310 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 3311 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3312 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3313 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3314 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3315 // CHECK5-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG89:![0-9]+]] 3316 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB27:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG90:![0-9]+]] 3317 // CHECK5-NEXT: ret void, !dbg [[DBG91:![0-9]+]] 3318 // 3319 // 3320 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 3321 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG92:![0-9]+]] { 3322 // CHECK5-NEXT: entry: 3323 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3324 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3325 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3326 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3327 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3328 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3329 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3330 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 3331 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3332 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3333 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3334 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3335 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3336 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 3337 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 3338 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3339 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3340 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3341 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3342 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3343 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3344 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG93:![0-9]+]] 3345 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG93]] 3346 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG93]] 3347 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG93]] 3348 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG94:![0-9]+]] 3349 // CHECK5-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG94]] 3350 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG94]] 3351 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG94]] 3352 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG93]] 3353 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG93]] 3354 // CHECK5-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB27]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1), !dbg [[DBG93]] 3355 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG93]] 3356 // CHECK5: omp.dispatch.cond: 3357 // CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB27]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]), !dbg [[DBG93]] 3358 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG93]] 3359 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG93]] 3360 // CHECK5: omp.dispatch.body: 3361 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG94]] 3362 // CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]] 3363 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG93]] 3364 // CHECK5: omp.inner.for.cond: 3365 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95 3366 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG94]], !llvm.access.group !95 3367 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]], !dbg [[DBG94]] 3368 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG93]] 3369 // CHECK5: omp.inner.for.body: 3370 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95 3371 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20, !dbg [[DBG94]] 3372 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1, !dbg [[DBG94]] 3373 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]], !dbg [[DBG94]] 3374 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8, !dbg [[DBG94]] 3375 // CHECK5-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !dbg [[DBG94]], !llvm.access.group !95 3376 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95 3377 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95 3378 // CHECK5-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20, !dbg [[DBG94]] 3379 // CHECK5-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20, !dbg [[DBG94]] 3380 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]], !dbg [[DBG94]] 3381 // CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1, !dbg [[DBG96:![0-9]+]] 3382 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]], !dbg [[DBG96]] 3383 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !dbg [[DBG96]], !llvm.access.group !95 3384 // CHECK5-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG97:![0-9]+]], !llvm.access.group !95 3385 // CHECK5-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG97]], !llvm.access.group !95 3386 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64, !dbg [[DBG97]] 3387 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]], !dbg [[DBG97]] 3388 // CHECK5-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG97]], !llvm.access.group !95 3389 // CHECK5-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG97]], !llvm.access.group !95 3390 // CHECK5-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG97]], !llvm.access.group !95 3391 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64, !dbg [[DBG97]] 3392 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM6]], !dbg [[DBG97]] 3393 // CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !dbg [[DBG97]], !llvm.access.group !95 3394 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]], !dbg [[DBG97]] 3395 // CHECK5-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG97]], !llvm.access.group !95 3396 // CHECK5-NEXT: [[TMP20:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG97]], !llvm.access.group !95 3397 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64, !dbg [[DBG97]] 3398 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM9]], !dbg [[DBG97]] 3399 // CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !dbg [[DBG97]], !llvm.access.group !95 3400 // CHECK5-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]], !dbg [[DBG97]] 3401 // CHECK5-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG97]], !llvm.access.group !95 3402 // CHECK5-NEXT: [[TMP23:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG97]], !llvm.access.group !95 3403 // CHECK5-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64, !dbg [[DBG97]] 3404 // CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM12]], !dbg [[DBG97]] 3405 // CHECK5-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !dbg [[DBG97]], !llvm.access.group !95 3406 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG98:![0-9]+]] 3407 // CHECK5: omp.body.continue: 3408 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG93]] 3409 // CHECK5: omp.inner.for.inc: 3410 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95 3411 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1, !dbg [[DBG94]] 3412 // CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95 3413 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG93]], !llvm.loop [[LOOP99:![0-9]+]] 3414 // CHECK5: omp.inner.for.end: 3415 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG93]] 3416 // CHECK5: omp.dispatch.inc: 3417 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG93]], !llvm.loop [[LOOP101:![0-9]+]] 3418 // CHECK5: omp.dispatch.end: 3419 // CHECK5-NEXT: ret void, !dbg [[DBG98]] 3420 // 3421 // 3422 // CHECK5-LABEL: define {{[^@]+}}@_Z3foov 3423 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] !dbg [[DBG102:![0-9]+]] { 3424 // CHECK5-NEXT: entry: 3425 // CHECK5-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG103:![0-9]+]] 3426 // CHECK5-NEXT: ret i32 0, !dbg [[DBG103]] 3427 // 3428 // 3429 // CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 3430 // CHECK5-SAME: (float* noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] !dbg [[DBG104:![0-9]+]] { 3431 // CHECK5-NEXT: entry: 3432 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3433 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3434 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3435 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3436 // CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 3437 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3438 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3439 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4, !dbg [[DBG105:![0-9]+]] 3440 // CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG105]] 3441 // CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG105]] 3442 // CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG105]] 3443 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG105]] 3444 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG105]] 3445 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4, !dbg [[DBG106:![0-9]+]] 3446 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32*, !dbg [[DBG106]] 3447 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4, !dbg [[DBG106]] 3448 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8, !dbg [[DBG106]] 3449 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB32:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), float** [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]), !dbg [[DBG106]] 3450 // CHECK5-NEXT: [[TMP5:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG107:![0-9]+]] 3451 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP5]]), !dbg [[DBG107]] 3452 // CHECK5-NEXT: ret void, !dbg [[DBG107]] 3453 // 3454 // 3455 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 3456 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG108:![0-9]+]] { 3457 // CHECK5-NEXT: entry: 3458 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3459 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3460 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3461 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3462 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 3463 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3464 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3465 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3466 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3467 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3468 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3469 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3470 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3471 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3472 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3473 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3474 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3475 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3476 // CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 3477 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG109:![0-9]+]] 3478 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8, !dbg [[DBG109]] 3479 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*, !dbg [[DBG109]] 3480 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG110:![0-9]+]] 3481 // CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG110]] 3482 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]] 3483 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG110]] 3484 // CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG109]] 3485 // CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG109]] 3486 // CHECK5-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG109]] 3487 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG109]] 3488 // CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG109]] 3489 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4, !dbg [[DBG109]] 3490 // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB29:[0-9]+]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG109]] 3491 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG109]] 3492 // CHECK5: omp.dispatch.cond: 3493 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG110]] 3494 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288, !dbg [[DBG110]] 3495 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG110]] 3496 // CHECK5: cond.true: 3497 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG110]] 3498 // CHECK5: cond.false: 3499 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG110]] 3500 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG110]] 3501 // CHECK5: cond.end: 3502 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ], !dbg [[DBG110]] 3503 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG110]] 3504 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG110]] 3505 // CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG110]] 3506 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG110]] 3507 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG110]] 3508 // CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]], !dbg [[DBG110]] 3509 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]], !dbg [[DBG109]] 3510 // CHECK5: omp.dispatch.cleanup: 3511 // CHECK5-NEXT: br label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG109]] 3512 // CHECK5: omp.dispatch.body: 3513 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG109]] 3514 // CHECK5: omp.inner.for.cond: 3515 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG110]] 3516 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG110]] 3517 // CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]], !dbg [[DBG110]] 3518 // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]], !dbg [[DBG109]] 3519 // CHECK5: omp.inner.for.cond.cleanup: 3520 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG109]] 3521 // CHECK5: omp.inner.for.body: 3522 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG110]] 3523 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127, !dbg [[DBG110]] 3524 // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG110]] 3525 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG110]] 3526 // CHECK5-NEXT: [[CALL:%.*]] = invoke noundef i32 @_Z3foov() 3527 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG111:![0-9]+]] 3528 // CHECK5: invoke.cont: 3529 // CHECK5-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG111]] 3530 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG111]] 3531 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64, !dbg [[DBG111]] 3532 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]], !dbg [[DBG111]] 3533 // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG111]] 3534 // CHECK5-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]], !dbg [[DBG111]] 3535 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4, !dbg [[DBG111]] 3536 // CHECK5-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float, !dbg [[DBG111]] 3537 // CHECK5-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]], !dbg [[DBG111]] 3538 // CHECK5-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG111]] 3539 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG111]] 3540 // CHECK5-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64, !dbg [[DBG111]] 3541 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]], !dbg [[DBG111]] 3542 // CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !dbg [[DBG111]] 3543 // CHECK5-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]], !dbg [[DBG111]] 3544 // CHECK5-NEXT: store float [[ADD10]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG111]] 3545 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG111]] 3546 // CHECK5: omp.body.continue: 3547 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG109]] 3548 // CHECK5: omp.inner.for.inc: 3549 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG110]] 3550 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP19]], 1, !dbg [[DBG110]] 3551 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG110]] 3552 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG109]], !llvm.loop [[LOOP112:![0-9]+]] 3553 // CHECK5: omp.inner.for.end: 3554 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG109]] 3555 // CHECK5: omp.dispatch.inc: 3556 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG110]] 3557 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]] 3558 // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP20]], [[TMP21]], !dbg [[DBG110]] 3559 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG110]] 3560 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG110]] 3561 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]] 3562 // CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP22]], [[TMP23]], !dbg [[DBG110]] 3563 // CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG110]] 3564 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG109]], !llvm.loop [[LOOP113:![0-9]+]] 3565 // CHECK5: omp.dispatch.end: 3566 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB31:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG109]] 3567 // CHECK5-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG109]] 3568 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]), !dbg [[DBG109]] 3569 // CHECK5-NEXT: ret void, !dbg [[DBG111]] 3570 // CHECK5: terminate.lpad: 3571 // CHECK5-NEXT: [[TMP25:%.*]] = landingpad { i8*, i32 } 3572 // CHECK5-NEXT: catch i8* null, !dbg [[DBG111]] 3573 // CHECK5-NEXT: [[TMP26:%.*]] = extractvalue { i8*, i32 } [[TMP25]], 0, !dbg [[DBG111]] 3574 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP26]]) #[[ATTR7:[0-9]+]], !dbg [[DBG111]] 3575 // CHECK5-NEXT: unreachable, !dbg [[DBG111]] 3576 // 3577 // 3578 // CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate 3579 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] { 3580 // CHECK5-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 3581 // CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 3582 // CHECK5-NEXT: unreachable 3583 // 3584 // 3585 // CHECK6-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 3586 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 3587 // CHECK6-NEXT: entry: 3588 // CHECK6-NEXT: [[A:%.*]] = alloca double, align 8 3589 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3590 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3591 // CHECK6-NEXT: store double 5.000000e+00, double* [[A]], align 8 3592 // CHECK6-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 3593 // CHECK6-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 3594 // CHECK6-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 3595 // CHECK6-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3596 // CHECK6-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 3597 // CHECK6-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 3598 // CHECK6-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3599 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]]) 3600 // CHECK6-NEXT: ret void 3601 // 3602 // 3603 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. 3604 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 3605 // CHECK6-NEXT: entry: 3606 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3607 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3608 // CHECK6-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3609 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3610 // CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 3611 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 3612 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 3613 // CHECK6-NEXT: [[I:%.*]] = alloca i64, align 8 3614 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3615 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3616 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3617 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3618 // CHECK6-NEXT: [[A:%.*]] = alloca double, align 8 3619 // CHECK6-NEXT: [[I5:%.*]] = alloca i64, align 8 3620 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3621 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3622 // CHECK6-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3623 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 3624 // CHECK6-NEXT: [[TMP0:%.*]] = load double, double* undef, align 8 3625 // CHECK6-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]] 3626 // CHECK6-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8 3627 // CHECK6-NEXT: [[TMP1:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 3628 // CHECK6-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00 3629 // CHECK6-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00 3630 // CHECK6-NEXT: [[CONV3:%.*]] = fptoui double [[DIV]] to i64 3631 // CHECK6-NEXT: [[SUB4:%.*]] = sub i64 [[CONV3]], 1 3632 // CHECK6-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_2]], align 8 3633 // CHECK6-NEXT: store i64 1, i64* [[I]], align 8 3634 // CHECK6-NEXT: [[TMP2:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 3635 // CHECK6-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]] 3636 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3637 // CHECK6: omp.precond.then: 3638 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3639 // CHECK6-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3640 // CHECK6-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 3641 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3642 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3643 // CHECK6-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 3644 // CHECK6-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64 3645 // CHECK6-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3646 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 3647 // CHECK6-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]) 3648 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3649 // CHECK6: omp.dispatch.cond: 3650 // CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3651 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3652 // CHECK6-NEXT: [[CMP7:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]] 3653 // CHECK6-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3654 // CHECK6: cond.true: 3655 // CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3656 // CHECK6-NEXT: br label [[COND_END:%.*]] 3657 // CHECK6: cond.false: 3658 // CHECK6-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3659 // CHECK6-NEXT: br label [[COND_END]] 3660 // CHECK6: cond.end: 3661 // CHECK6-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 3662 // CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3663 // CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3664 // CHECK6-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 3665 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3666 // CHECK6-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3667 // CHECK6-NEXT: [[ADD8:%.*]] = add i64 [[TMP13]], 1 3668 // CHECK6-NEXT: [[CMP9:%.*]] = icmp ult i64 [[TMP12]], [[ADD8]] 3669 // CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3670 // CHECK6: omp.dispatch.body: 3671 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3672 // CHECK6: omp.inner.for.cond: 3673 // CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3674 // CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3675 // CHECK6-NEXT: [[ADD10:%.*]] = add i64 [[TMP15]], 1 3676 // CHECK6-NEXT: [[CMP11:%.*]] = icmp ult i64 [[TMP14]], [[ADD10]] 3677 // CHECK6-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3678 // CHECK6: omp.inner.for.body: 3679 // CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3680 // CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1 3681 // CHECK6-NEXT: [[ADD12:%.*]] = add i64 1, [[MUL]] 3682 // CHECK6-NEXT: store i64 [[ADD12]], i64* [[I5]], align 8 3683 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3684 // CHECK6: omp.body.continue: 3685 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3686 // CHECK6: omp.inner.for.inc: 3687 // CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3688 // CHECK6-NEXT: [[ADD13:%.*]] = add i64 [[TMP17]], 1 3689 // CHECK6-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_IV]], align 8 3690 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 3691 // CHECK6: omp.inner.for.end: 3692 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3693 // CHECK6: omp.dispatch.inc: 3694 // CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3695 // CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 3696 // CHECK6-NEXT: [[ADD14:%.*]] = add i64 [[TMP18]], [[TMP19]] 3697 // CHECK6-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_LB]], align 8 3698 // CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3699 // CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 3700 // CHECK6-NEXT: [[ADD15:%.*]] = add i64 [[TMP20]], [[TMP21]] 3701 // CHECK6-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_UB]], align 8 3702 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 3703 // CHECK6: omp.dispatch.end: 3704 // CHECK6-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3705 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 3706 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 3707 // CHECK6-NEXT: br label [[OMP_PRECOND_END]] 3708 // CHECK6: omp.precond.end: 3709 // CHECK6-NEXT: ret void 3710 // 3711 // 3712 // CHECK6-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 3713 // CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 3714 // CHECK6-NEXT: entry: 3715 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3716 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3717 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3718 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3719 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3720 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3721 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3722 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3723 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3724 // CHECK6-NEXT: ret void 3725 // 3726 // 3727 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 3728 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 3729 // CHECK6-NEXT: entry: 3730 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3731 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3732 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3733 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3734 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3735 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3736 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3737 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 3738 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3739 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3740 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3741 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3742 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3743 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3744 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3745 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3746 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3747 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3748 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3749 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 3750 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 3751 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 3752 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 3753 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3754 // CHECK6-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 3755 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3756 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3757 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3758 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3759 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3760 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3761 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 3762 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3763 // CHECK6: cond.true: 3764 // CHECK6-NEXT: br label [[COND_END:%.*]] 3765 // CHECK6: cond.false: 3766 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3767 // CHECK6-NEXT: br label [[COND_END]] 3768 // CHECK6: cond.end: 3769 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3770 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3771 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3772 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3773 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3774 // CHECK6: omp.inner.for.cond: 3775 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3776 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3777 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3778 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3779 // CHECK6: omp.inner.for.body: 3780 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3781 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 3782 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 3783 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3784 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 3785 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 3786 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 3787 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 3788 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 3789 // CHECK6-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 3790 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 3791 // CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 3792 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 3793 // CHECK6-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 3794 // CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 3795 // CHECK6-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 3796 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 3797 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 3798 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 3799 // CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 3800 // CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 3801 // CHECK6-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 3802 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 3803 // CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 3804 // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 3805 // CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 3806 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3807 // CHECK6: omp.body.continue: 3808 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3809 // CHECK6: omp.inner.for.inc: 3810 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3811 // CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 3812 // CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 3813 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 3814 // CHECK6: omp.inner.for.end: 3815 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3816 // CHECK6: omp.loop.exit: 3817 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3818 // CHECK6-NEXT: ret void 3819 // 3820 // 3821 // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 3822 // CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 3823 // CHECK6-NEXT: entry: 3824 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3825 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3826 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3827 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3828 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3829 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3830 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3831 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3832 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3833 // CHECK6-NEXT: ret void 3834 // 3835 // 3836 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 3837 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 3838 // CHECK6-NEXT: entry: 3839 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3840 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3841 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3842 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3843 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3844 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3845 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3846 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 3847 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3848 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3849 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3850 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3851 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3852 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3853 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3854 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3855 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3856 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3857 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3858 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 3859 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 3860 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 3861 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 3862 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3863 // CHECK6-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 3864 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3865 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3866 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3867 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3868 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3869 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3870 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 3871 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3872 // CHECK6: cond.true: 3873 // CHECK6-NEXT: br label [[COND_END:%.*]] 3874 // CHECK6: cond.false: 3875 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3876 // CHECK6-NEXT: br label [[COND_END]] 3877 // CHECK6: cond.end: 3878 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3879 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3880 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3881 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3882 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3883 // CHECK6: omp.inner.for.cond: 3884 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3885 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3886 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3887 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3888 // CHECK6: omp.inner.for.body: 3889 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3890 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 3891 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 3892 // CHECK6-NEXT: store i32 [[SUB]], i32* [[I]], align 4 3893 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 3894 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 3895 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 3896 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 3897 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 3898 // CHECK6-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 3899 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 3900 // CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 3901 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 3902 // CHECK6-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 3903 // CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 3904 // CHECK6-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 3905 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 3906 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 3907 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 3908 // CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 3909 // CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 3910 // CHECK6-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 3911 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 3912 // CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 3913 // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 3914 // CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 3915 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3916 // CHECK6: omp.body.continue: 3917 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3918 // CHECK6: omp.inner.for.inc: 3919 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3920 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 3921 // CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 3922 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 3923 // CHECK6: omp.inner.for.end: 3924 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3925 // CHECK6: omp.loop.exit: 3926 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3927 // CHECK6-NEXT: ret void 3928 // 3929 // 3930 // CHECK6-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 3931 // CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 3932 // CHECK6-NEXT: entry: 3933 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3934 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3935 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3936 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3937 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3938 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3939 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3940 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3941 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3942 // CHECK6-NEXT: ret void 3943 // 3944 // 3945 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 3946 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 3947 // CHECK6-NEXT: entry: 3948 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3949 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3950 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3951 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3952 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3953 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3954 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3955 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 3956 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3957 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3958 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3959 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3960 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 3961 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3962 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3963 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3964 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3965 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3966 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3967 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 3968 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 3969 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 3970 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 3971 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3972 // CHECK6-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 3973 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3974 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3975 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3976 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3977 // CHECK6-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 3978 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3979 // CHECK6: omp.dispatch.cond: 3980 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3981 // CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 3982 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3983 // CHECK6: cond.true: 3984 // CHECK6-NEXT: br label [[COND_END:%.*]] 3985 // CHECK6: cond.false: 3986 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3987 // CHECK6-NEXT: br label [[COND_END]] 3988 // CHECK6: cond.end: 3989 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3990 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3991 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3992 // CHECK6-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3993 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3994 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3995 // CHECK6-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 3996 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3997 // CHECK6: omp.dispatch.body: 3998 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3999 // CHECK6: omp.inner.for.cond: 4000 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4001 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4002 // CHECK6-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 4003 // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4004 // CHECK6: omp.inner.for.body: 4005 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4006 // CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 4007 // CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4008 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4009 // CHECK6-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8 4010 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 4011 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 4012 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 4013 // CHECK6-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4 4014 // CHECK6-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8 4015 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 4016 // CHECK6-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 4017 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 4018 // CHECK6-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4 4019 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 4020 // CHECK6-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8 4021 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 4022 // CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 4023 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 4024 // CHECK6-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4 4025 // CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 4026 // CHECK6-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8 4027 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 4028 // CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 4029 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 4030 // CHECK6-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 4031 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4032 // CHECK6: omp.body.continue: 4033 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4034 // CHECK6: omp.inner.for.inc: 4035 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4036 // CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 4037 // CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 4038 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 4039 // CHECK6: omp.inner.for.end: 4040 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4041 // CHECK6: omp.dispatch.inc: 4042 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4043 // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4044 // CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 4045 // CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 4046 // CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4047 // CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4048 // CHECK6-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 4049 // CHECK6-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 4050 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 4051 // CHECK6: omp.dispatch.end: 4052 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 4053 // CHECK6-NEXT: ret void 4054 // 4055 // 4056 // CHECK6-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 4057 // CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4058 // CHECK6-NEXT: entry: 4059 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4060 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4061 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4062 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4063 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4064 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4065 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4066 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4067 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 4068 // CHECK6-NEXT: ret void 4069 // 4070 // 4071 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 4072 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 4073 // CHECK6-NEXT: entry: 4074 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4075 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4076 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4077 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4078 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4079 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4080 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4081 // CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 4082 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4083 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4084 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4085 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4086 // CHECK6-NEXT: [[I:%.*]] = alloca i64, align 8 4087 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4088 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4089 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4090 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4091 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4092 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4093 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 4094 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 4095 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 4096 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 4097 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4098 // CHECK6-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 4099 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4100 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4101 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4102 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4103 // CHECK6-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1) 4104 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4105 // CHECK6: omp.dispatch.cond: 4106 // CHECK6-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 4107 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 4108 // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4109 // CHECK6: omp.dispatch.body: 4110 // CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4111 // CHECK6-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 4112 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4113 // CHECK6: omp.inner.for.cond: 4114 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 4115 // CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 4116 // CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 4117 // CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 4118 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4119 // CHECK6: omp.inner.for.body: 4120 // CHECK6-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 4121 // CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 4122 // CHECK6-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 4123 // CHECK6-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5 4124 // CHECK6-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !5 4125 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 4126 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 4127 // CHECK6-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !5 4128 // CHECK6-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !5 4129 // CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 4130 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 4131 // CHECK6-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !5 4132 // CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 4133 // CHECK6-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !5 4134 // CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 4135 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 4136 // CHECK6-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !5 4137 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 4138 // CHECK6-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !5 4139 // CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 4140 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 4141 // CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5 4142 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4143 // CHECK6: omp.body.continue: 4144 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4145 // CHECK6: omp.inner.for.inc: 4146 // CHECK6-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 4147 // CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 4148 // CHECK6-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 4149 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 4150 // CHECK6: omp.inner.for.end: 4151 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4152 // CHECK6: omp.dispatch.inc: 4153 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 4154 // CHECK6: omp.dispatch.end: 4155 // CHECK6-NEXT: ret void 4156 // 4157 // 4158 // CHECK6-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 4159 // CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4160 // CHECK6-NEXT: entry: 4161 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4162 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4163 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4164 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4165 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4166 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4167 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4168 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4169 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..5 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 4170 // CHECK6-NEXT: ret void 4171 // 4172 // 4173 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 4174 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 4175 // CHECK6-NEXT: entry: 4176 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4177 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4178 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4179 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4180 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4181 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4182 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4183 // CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 4184 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4185 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4186 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4187 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4188 // CHECK6-NEXT: [[I:%.*]] = alloca i64, align 8 4189 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4190 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4191 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4192 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4193 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4194 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4195 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 4196 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 4197 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 4198 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 4199 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4200 // CHECK6-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 4201 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4202 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4203 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4204 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4205 // CHECK6-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7) 4206 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4207 // CHECK6: omp.dispatch.cond: 4208 // CHECK6-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 4209 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 4210 // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4211 // CHECK6: omp.dispatch.body: 4212 // CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4213 // CHECK6-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 4214 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4215 // CHECK6: omp.inner.for.cond: 4216 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 4217 // CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !8 4218 // CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 4219 // CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 4220 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4221 // CHECK6: omp.inner.for.body: 4222 // CHECK6-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 4223 // CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 4224 // CHECK6-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 4225 // CHECK6-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8 4226 // CHECK6-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !8 4227 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 4228 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 4229 // CHECK6-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8 4230 // CHECK6-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8 4231 // CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 4232 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 4233 // CHECK6-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !8 4234 // CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 4235 // CHECK6-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !8 4236 // CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 4237 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 4238 // CHECK6-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !8 4239 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 4240 // CHECK6-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !8 4241 // CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 4242 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 4243 // CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8 4244 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4245 // CHECK6: omp.body.continue: 4246 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4247 // CHECK6: omp.inner.for.inc: 4248 // CHECK6-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 4249 // CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 4250 // CHECK6-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 4251 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 4252 // CHECK6: omp.inner.for.end: 4253 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4254 // CHECK6: omp.dispatch.inc: 4255 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 4256 // CHECK6: omp.dispatch.end: 4257 // CHECK6-NEXT: ret void 4258 // 4259 // 4260 // CHECK6-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 4261 // CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4262 // CHECK6-NEXT: entry: 4263 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4264 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4265 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4266 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4267 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 4268 // CHECK6-NEXT: [[Y:%.*]] = alloca i32, align 4 4269 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4270 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4271 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4272 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4273 // CHECK6-NEXT: store i32 0, i32* [[X]], align 4 4274 // CHECK6-NEXT: store i32 0, i32* [[Y]], align 4 4275 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[Y]], float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 4276 // CHECK6-NEXT: ret void 4277 // 4278 // 4279 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 4280 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 4281 // CHECK6-NEXT: entry: 4282 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4283 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4284 // CHECK6-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 4285 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4286 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4287 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4288 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4289 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4290 // CHECK6-NEXT: [[TMP:%.*]] = alloca i8, align 1 4291 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4292 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4293 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 4294 // CHECK6-NEXT: [[I:%.*]] = alloca i8, align 1 4295 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 4296 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4297 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4298 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4299 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4300 // CHECK6-NEXT: [[I7:%.*]] = alloca i8, align 1 4301 // CHECK6-NEXT: [[X8:%.*]] = alloca i32, align 4 4302 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4303 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4304 // CHECK6-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8 4305 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4306 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4307 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4308 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4309 // CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[Y_ADDR]], align 8 4310 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[A_ADDR]], align 8 4311 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[B_ADDR]], align 8 4312 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[C_ADDR]], align 8 4313 // CHECK6-NEXT: [[TMP4:%.*]] = load float**, float*** [[D_ADDR]], align 8 4314 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 4315 // CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8 4316 // CHECK6-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 4317 // CHECK6-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4318 // CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32 4319 // CHECK6-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 4320 // CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 4321 // CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4322 // CHECK6-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 4323 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 4324 // CHECK6-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 4325 // CHECK6-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 4326 // CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4327 // CHECK6-NEXT: store i8 [[TMP7]], i8* [[I]], align 1 4328 // CHECK6-NEXT: store i32 11, i32* [[X]], align 4 4329 // CHECK6-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4330 // CHECK6-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32 4331 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57 4332 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 4333 // CHECK6: omp.precond.then: 4334 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4335 // CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 4336 // CHECK6-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 4337 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4338 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4339 // CHECK6-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 4340 // CHECK6-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4341 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 4342 // CHECK6-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1) 4343 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4344 // CHECK6: omp.dispatch.cond: 4345 // CHECK6-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4346 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 4347 // CHECK6-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 4348 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 4349 // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4350 // CHECK6: omp.dispatch.body: 4351 // CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4352 // CHECK6-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 4353 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4354 // CHECK6: omp.inner.for.cond: 4355 // CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 4356 // CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !11 4357 // CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 4358 // CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4359 // CHECK6: omp.inner.for.body: 4360 // CHECK6-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11 4361 // CHECK6-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64 4362 // CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 4363 // CHECK6-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11 4364 // CHECK6-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1 4365 // CHECK6-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]] 4366 // CHECK6-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8 4367 // CHECK6-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11 4368 // CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 4369 // CHECK6-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 4370 // CHECK6-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11 4371 // CHECK6-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11 4372 // CHECK6-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]] 4373 // CHECK6-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1 4374 // CHECK6-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]] 4375 // CHECK6-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32 4376 // CHECK6-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11 4377 // CHECK6-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !11 4378 // CHECK6-NEXT: [[TMP24:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 4379 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64 4380 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM]] 4381 // CHECK6-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 4382 // CHECK6-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !11 4383 // CHECK6-NEXT: [[TMP27:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 4384 // CHECK6-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64 4385 // CHECK6-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM21]] 4386 // CHECK6-NEXT: [[TMP28:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !llvm.access.group !11 4387 // CHECK6-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]] 4388 // CHECK6-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !11 4389 // CHECK6-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 4390 // CHECK6-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64 4391 // CHECK6-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM24]] 4392 // CHECK6-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !llvm.access.group !11 4393 // CHECK6-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]] 4394 // CHECK6-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !11 4395 // CHECK6-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 4396 // CHECK6-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64 4397 // CHECK6-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM27]] 4398 // CHECK6-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11 4399 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4400 // CHECK6: omp.body.continue: 4401 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4402 // CHECK6: omp.inner.for.inc: 4403 // CHECK6-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 4404 // CHECK6-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1 4405 // CHECK6-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 4406 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 4407 // CHECK6: omp.inner.for.end: 4408 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4409 // CHECK6: omp.dispatch.inc: 4410 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 4411 // CHECK6: omp.dispatch.end: 4412 // CHECK6-NEXT: br label [[OMP_PRECOND_END]] 4413 // CHECK6: omp.precond.end: 4414 // CHECK6-NEXT: ret void 4415 // 4416 // 4417 // CHECK6-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 4418 // CHECK6-SAME: (float* noundef [[A:%.*]], float* noundef [[B:%.*]], float* noundef [[C:%.*]], float* noundef [[D:%.*]]) #[[ATTR0]] { 4419 // CHECK6-NEXT: entry: 4420 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4421 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4422 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4423 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4424 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 4425 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4426 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4427 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4428 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4429 // CHECK6-NEXT: store i32 0, i32* [[X]], align 4 4430 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 4431 // CHECK6-NEXT: ret void 4432 // 4433 // 4434 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 4435 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[B:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[C:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 4436 // CHECK6-NEXT: entry: 4437 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4438 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4439 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4440 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4441 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4442 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4443 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4444 // CHECK6-NEXT: [[TMP:%.*]] = alloca i8, align 1 4445 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4446 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4447 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4448 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4449 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4450 // CHECK6-NEXT: [[I:%.*]] = alloca i8, align 1 4451 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 4452 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4453 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4454 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4455 // CHECK6-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4456 // CHECK6-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4457 // CHECK6-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4458 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 4459 // CHECK6-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 4460 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 4461 // CHECK6-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 4462 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4463 // CHECK6-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 4464 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4465 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4466 // CHECK6-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4467 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4468 // CHECK6-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1) 4469 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4470 // CHECK6: omp.dispatch.cond: 4471 // CHECK6-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 4472 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 4473 // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4474 // CHECK6: omp.dispatch.body: 4475 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4476 // CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 4477 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4478 // CHECK6: omp.inner.for.cond: 4479 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4480 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 4481 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 4482 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4483 // CHECK6: omp.inner.for.body: 4484 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4485 // CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20 4486 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 4487 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 4488 // CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 4489 // CHECK6-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14 4490 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4491 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4492 // CHECK6-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20 4493 // CHECK6-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20 4494 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]] 4495 // CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 4496 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]] 4497 // CHECK6-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14 4498 // CHECK6-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !14 4499 // CHECK6-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 4500 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64 4501 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] 4502 // CHECK6-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !14 4503 // CHECK6-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !14 4504 // CHECK6-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 4505 // CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64 4506 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM6]] 4507 // CHECK6-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !14 4508 // CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]] 4509 // CHECK6-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !14 4510 // CHECK6-NEXT: [[TMP20:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 4511 // CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64 4512 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM9]] 4513 // CHECK6-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 4514 // CHECK6-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]] 4515 // CHECK6-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !14 4516 // CHECK6-NEXT: [[TMP23:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 4517 // CHECK6-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64 4518 // CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM12]] 4519 // CHECK6-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14 4520 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4521 // CHECK6: omp.body.continue: 4522 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4523 // CHECK6: omp.inner.for.inc: 4524 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4525 // CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1 4526 // CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4527 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 4528 // CHECK6: omp.inner.for.end: 4529 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4530 // CHECK6: omp.dispatch.inc: 4531 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 4532 // CHECK6: omp.dispatch.end: 4533 // CHECK6-NEXT: ret void 4534 // 4535 // 4536 // CHECK6-LABEL: define {{[^@]+}}@_Z3foov 4537 // CHECK6-SAME: () #[[ATTR0]] { 4538 // CHECK6-NEXT: entry: 4539 // CHECK6-NEXT: call void @_Z8mayThrowv() 4540 // CHECK6-NEXT: ret i32 0 4541 // 4542 // 4543 // CHECK6-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 4544 // CHECK6-SAME: (float* noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] { 4545 // CHECK6-NEXT: entry: 4546 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4547 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4548 // CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4549 // CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4550 // CHECK6-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 4551 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4552 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4553 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4554 // CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 4555 // CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 4556 // CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 4557 // CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 4558 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 4559 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 4560 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 4561 // CHECK6-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 4562 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 4563 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), float** [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]) 4564 // CHECK6-NEXT: [[TMP5:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4565 // CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP5]]) 4566 // CHECK6-NEXT: ret void 4567 // 4568 // 4569 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 4570 // CHECK6-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], float** noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] { 4571 // CHECK6-NEXT: entry: 4572 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4573 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4574 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4575 // CHECK6-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4576 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 4577 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4578 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 4579 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4580 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4581 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4582 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4583 // CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4584 // CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4585 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 4586 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4587 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4588 // CHECK6-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4589 // CHECK6-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4590 // CHECK6-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 4591 // CHECK6-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 4592 // CHECK6-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4593 // CHECK6-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 4594 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4595 // CHECK6-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 4596 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4597 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4598 // CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 4599 // CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 4600 // CHECK6-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16 4601 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 4602 // CHECK6-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4603 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 4604 // CHECK6-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 4605 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4606 // CHECK6: omp.dispatch.cond: 4607 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4608 // CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288 4609 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4610 // CHECK6: cond.true: 4611 // CHECK6-NEXT: br label [[COND_END:%.*]] 4612 // CHECK6: cond.false: 4613 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4614 // CHECK6-NEXT: br label [[COND_END]] 4615 // CHECK6: cond.end: 4616 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 4617 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4618 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4619 // CHECK6-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 4620 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4621 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4622 // CHECK6-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]] 4623 // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]] 4624 // CHECK6: omp.dispatch.cleanup: 4625 // CHECK6-NEXT: br label [[OMP_DISPATCH_END:%.*]] 4626 // CHECK6: omp.dispatch.body: 4627 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4628 // CHECK6: omp.inner.for.cond: 4629 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4630 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4631 // CHECK6-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]] 4632 // CHECK6-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 4633 // CHECK6: omp.inner.for.cond.cleanup: 4634 // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 4635 // CHECK6: omp.inner.for.body: 4636 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4637 // CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127 4638 // CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4639 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4640 // CHECK6-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3foov() 4641 // CHECK6-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float 4642 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 4643 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 4644 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] 4645 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 4646 // CHECK6-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]] 4647 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 4 4648 // CHECK6-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float 4649 // CHECK6-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] 4650 // CHECK6-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8 4651 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 4652 // CHECK6-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64 4653 // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]] 4654 // CHECK6-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4 4655 // CHECK6-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]] 4656 // CHECK6-NEXT: store float [[ADD10]], float* [[ARRAYIDX9]], align 4 4657 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4658 // CHECK6: omp.body.continue: 4659 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4660 // CHECK6: omp.inner.for.inc: 4661 // CHECK6-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4662 // CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP19]], 1 4663 // CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 4664 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 4665 // CHECK6: omp.inner.for.end: 4666 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4667 // CHECK6: omp.dispatch.inc: 4668 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4669 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4670 // CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP20]], [[TMP21]] 4671 // CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 4672 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4673 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4674 // CHECK6-NEXT: [[ADD13:%.*]] = add i32 [[TMP22]], [[TMP23]] 4675 // CHECK6-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 4676 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 4677 // CHECK6: omp.dispatch.end: 4678 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) 4679 // CHECK6-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4680 // CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) 4681 // CHECK6-NEXT: ret void 4682 // 4683 // 4684 // CHECK11-LABEL: define {{[^@]+}}@_Z9incrementv 4685 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 4686 // CHECK11-NEXT: entry: 4687 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4688 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4689 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4690 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4691 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4692 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4693 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 4694 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 4695 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4696 // CHECK11-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 4697 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4698 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4699 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4700 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4701 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 4702 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4703 // CHECK11: cond.true: 4704 // CHECK11-NEXT: br label [[COND_END:%.*]] 4705 // CHECK11: cond.false: 4706 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4707 // CHECK11-NEXT: br label [[COND_END]] 4708 // CHECK11: cond.end: 4709 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 4710 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4711 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4712 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 4713 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4714 // CHECK11: omp.inner.for.cond: 4715 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4716 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4717 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 4718 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4719 // CHECK11: omp.inner.for.body: 4720 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4721 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 4722 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 4723 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4724 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4725 // CHECK11: omp.body.continue: 4726 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4727 // CHECK11: omp.inner.for.inc: 4728 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4729 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], 1 4730 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 4731 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4732 // CHECK11: omp.inner.for.end: 4733 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4734 // CHECK11: omp.loop.exit: 4735 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 4736 // CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]) 4737 // CHECK11-NEXT: ret i32 0 4738 // 4739 // 4740 // CHECK11-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv 4741 // CHECK11-SAME: () #[[ATTR0]] { 4742 // CHECK11-NEXT: entry: 4743 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4744 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 4745 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4746 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4747 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4748 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4749 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 4750 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 4751 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4752 // CHECK11-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 4753 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4754 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4755 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4756 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4757 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 4758 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4759 // CHECK11: cond.true: 4760 // CHECK11-NEXT: br label [[COND_END:%.*]] 4761 // CHECK11: cond.false: 4762 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4763 // CHECK11-NEXT: br label [[COND_END]] 4764 // CHECK11: cond.end: 4765 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 4766 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4767 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4768 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 4769 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4770 // CHECK11: omp.inner.for.cond: 4771 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4772 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4773 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 4774 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4775 // CHECK11: omp.inner.for.body: 4776 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4777 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 4778 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 5, [[MUL]] 4779 // CHECK11-NEXT: store i32 [[SUB]], i32* [[J]], align 4 4780 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4781 // CHECK11: omp.body.continue: 4782 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4783 // CHECK11: omp.inner.for.inc: 4784 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4785 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 4786 // CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 4787 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4788 // CHECK11: omp.inner.for.end: 4789 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4790 // CHECK11: omp.loop.exit: 4791 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 4792 // CHECK11-NEXT: ret i32 0 4793 // 4794 // 4795 // CHECK11-LABEL: define {{[^@]+}}@_Z16range_for_singlev 4796 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 4797 // CHECK11-NEXT: entry: 4798 // CHECK11-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 4799 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 4800 // CHECK11-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 4801 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) 4802 // CHECK11-NEXT: ret void 4803 // 4804 // 4805 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 4806 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5:[0-9]+]] { 4807 // CHECK11-NEXT: entry: 4808 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4809 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4810 // CHECK11-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 4811 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4812 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4813 // CHECK11-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 4814 // CHECK11-NEXT: [[__END1:%.*]] = alloca i32*, align 8 4815 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 4816 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32*, align 8 4817 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 4818 // CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 4819 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4820 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4821 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4822 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4823 // CHECK11-NEXT: [[__BEGIN15:%.*]] = alloca i32*, align 8 4824 // CHECK11-NEXT: [[A:%.*]] = alloca i32*, align 8 4825 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4826 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4827 // CHECK11-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 4828 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 4829 // CHECK11-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 4830 // CHECK11-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 4831 // CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 4832 // CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 4833 // CHECK11-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 4834 // CHECK11-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 4835 // CHECK11-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 4836 // CHECK11-NEXT: store i32* [[ARRAYDECAY1]], i32** [[DOTCAPTURE_EXPR_]], align 8 4837 // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__END1]], align 8 4838 // CHECK11-NEXT: store i32* [[TMP3]], i32** [[DOTCAPTURE_EXPR_2]], align 8 4839 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 4840 // CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 4841 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP4]] to i64 4842 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP5]] to i64 4843 // CHECK11-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 4844 // CHECK11-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 4845 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 4846 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 4847 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 4848 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i64 [[DIV]], 1 4849 // CHECK11-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_3]], align 8 4850 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 4851 // CHECK11-NEXT: store i32* [[TMP6]], i32** [[__BEGIN1]], align 8 4852 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 4853 // CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 4854 // CHECK11-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP7]], [[TMP8]] 4855 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 4856 // CHECK11: omp.precond.then: 4857 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4858 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 4859 // CHECK11-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 4860 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4861 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4862 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4863 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 4864 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4865 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4866 // CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 4867 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 4868 // CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4869 // CHECK11: cond.true: 4870 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 4871 // CHECK11-NEXT: br label [[COND_END:%.*]] 4872 // CHECK11: cond.false: 4873 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4874 // CHECK11-NEXT: br label [[COND_END]] 4875 // CHECK11: cond.end: 4876 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 4877 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 4878 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4879 // CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 4880 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4881 // CHECK11: omp.inner.for.cond: 4882 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4883 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4884 // CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 4885 // CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4886 // CHECK11: omp.inner.for.body: 4887 // CHECK11-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 4888 // CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4889 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP20]], 1 4890 // CHECK11-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 [[MUL]] 4891 // CHECK11-NEXT: store i32* [[ADD_PTR8]], i32** [[__BEGIN15]], align 8 4892 // CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[__BEGIN15]], align 8 4893 // CHECK11-NEXT: store i32* [[TMP21]], i32** [[A]], align 8 4894 // CHECK11-NEXT: [[TMP22:%.*]] = load i32*, i32** [[A]], align 8 4895 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4896 // CHECK11: omp.body.continue: 4897 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4898 // CHECK11: omp.inner.for.inc: 4899 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4900 // CHECK11-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP23]], 1 4901 // CHECK11-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 4902 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 4903 // CHECK11: omp.inner.for.end: 4904 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4905 // CHECK11: omp.loop.exit: 4906 // CHECK11-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4907 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 4908 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) 4909 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 4910 // CHECK11: omp.precond.end: 4911 // CHECK11-NEXT: ret void 4912 // 4913 // 4914 // CHECK11-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv 4915 // CHECK11-SAME: () #[[ATTR3]] { 4916 // CHECK11-NEXT: entry: 4917 // CHECK11-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 4918 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 4919 // CHECK11-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 4920 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) 4921 // CHECK11-NEXT: ret void 4922 // 4923 // 4924 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 4925 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5]] { 4926 // CHECK11-NEXT: entry: 4927 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4928 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4929 // CHECK11-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 4930 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4931 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4932 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 4933 // CHECK11-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 4934 // CHECK11-NEXT: [[__END1:%.*]] = alloca i32*, align 8 4935 // CHECK11-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 4936 // CHECK11-NEXT: [[__END2:%.*]] = alloca i32*, align 8 4937 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 4938 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32*, align 8 4939 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32*, align 8 4940 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32*, align 8 4941 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8 4942 // CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 4943 // CHECK11-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 4944 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4945 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4946 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4947 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4948 // CHECK11-NEXT: [[__BEGIN119:%.*]] = alloca i32*, align 8 4949 // CHECK11-NEXT: [[__BEGIN220:%.*]] = alloca i32*, align 8 4950 // CHECK11-NEXT: [[A:%.*]] = alloca i32*, align 8 4951 // CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 4952 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4953 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4954 // CHECK11-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 4955 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 4956 // CHECK11-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 4957 // CHECK11-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 4958 // CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 4959 // CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 4960 // CHECK11-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 4961 // CHECK11-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE2]], align 8 4962 // CHECK11-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 4963 // CHECK11-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 4964 // CHECK11-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY2]], i64 10 4965 // CHECK11-NEXT: store i32* [[ADD_PTR3]], i32** [[__END2]], align 8 4966 // CHECK11-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 4967 // CHECK11-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP3]], i64 0, i64 0 4968 // CHECK11-NEXT: store i32* [[ARRAYDECAY4]], i32** [[DOTCAPTURE_EXPR_]], align 8 4969 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 4970 // CHECK11-NEXT: store i32* [[TMP4]], i32** [[DOTCAPTURE_EXPR_5]], align 8 4971 // CHECK11-NEXT: [[TMP5:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 4972 // CHECK11-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP5]], i64 0, i64 0 4973 // CHECK11-NEXT: store i32* [[ARRAYDECAY7]], i32** [[DOTCAPTURE_EXPR_6]], align 8 4974 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[__END2]], align 8 4975 // CHECK11-NEXT: store i32* [[TMP6]], i32** [[DOTCAPTURE_EXPR_8]], align 8 4976 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 4977 // CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 4978 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP7]] to i64 4979 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP8]] to i64 4980 // CHECK11-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 4981 // CHECK11-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 4982 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 4983 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 4984 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 4985 // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 4986 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 4987 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST10:%.*]] = ptrtoint i32* [[TMP9]] to i64 4988 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST11:%.*]] = ptrtoint i32* [[TMP10]] to i64 4989 // CHECK11-NEXT: [[SUB_PTR_SUB12:%.*]] = sub i64 [[SUB_PTR_LHS_CAST10]], [[SUB_PTR_RHS_CAST11]] 4990 // CHECK11-NEXT: [[SUB_PTR_DIV13:%.*]] = sdiv exact i64 [[SUB_PTR_SUB12]], 4 4991 // CHECK11-NEXT: [[SUB14:%.*]] = sub nsw i64 [[SUB_PTR_DIV13]], 1 4992 // CHECK11-NEXT: [[ADD15:%.*]] = add nsw i64 [[SUB14]], 1 4993 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i64 [[ADD15]], 1 4994 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV16]] 4995 // CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i64 [[MUL]], 1 4996 // CHECK11-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_9]], align 8 4997 // CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 4998 // CHECK11-NEXT: store i32* [[TMP11]], i32** [[__BEGIN1]], align 8 4999 // CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 5000 // CHECK11-NEXT: store i32* [[TMP12]], i32** [[__BEGIN2]], align 8 5001 // CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 5002 // CHECK11-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 5003 // CHECK11-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP13]], [[TMP14]] 5004 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 5005 // CHECK11: land.lhs.true: 5006 // CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 5007 // CHECK11-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 5008 // CHECK11-NEXT: [[CMP18:%.*]] = icmp ult i32* [[TMP15]], [[TMP16]] 5009 // CHECK11-NEXT: br i1 [[CMP18]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 5010 // CHECK11: omp.precond.then: 5011 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 5012 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 5013 // CHECK11-NEXT: store i64 [[TMP17]], i64* [[DOTOMP_UB]], align 8 5014 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 5015 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5016 // CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5017 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 5018 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 5019 // CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5020 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 5021 // CHECK11-NEXT: [[CMP21:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]] 5022 // CHECK11-NEXT: br i1 [[CMP21]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5023 // CHECK11: cond.true: 5024 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 5025 // CHECK11-NEXT: br label [[COND_END:%.*]] 5026 // CHECK11: cond.false: 5027 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5028 // CHECK11-NEXT: br label [[COND_END]] 5029 // CHECK11: cond.end: 5030 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ] 5031 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 5032 // CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 5033 // CHECK11-NEXT: store i64 [[TMP24]], i64* [[DOTOMP_IV]], align 8 5034 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5035 // CHECK11: omp.inner.for.cond: 5036 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5037 // CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5038 // CHECK11-NEXT: [[CMP22:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] 5039 // CHECK11-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5040 // CHECK11: omp.inner.for.body: 5041 // CHECK11-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 5042 // CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5043 // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 5044 // CHECK11-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 5045 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST23:%.*]] = ptrtoint i32* [[TMP29]] to i64 5046 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST24:%.*]] = ptrtoint i32* [[TMP30]] to i64 5047 // CHECK11-NEXT: [[SUB_PTR_SUB25:%.*]] = sub i64 [[SUB_PTR_LHS_CAST23]], [[SUB_PTR_RHS_CAST24]] 5048 // CHECK11-NEXT: [[SUB_PTR_DIV26:%.*]] = sdiv exact i64 [[SUB_PTR_SUB25]], 4 5049 // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i64 [[SUB_PTR_DIV26]], 1 5050 // CHECK11-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB27]], 1 5051 // CHECK11-NEXT: [[DIV29:%.*]] = sdiv i64 [[ADD28]], 1 5052 // CHECK11-NEXT: [[MUL30:%.*]] = mul nsw i64 1, [[DIV29]] 5053 // CHECK11-NEXT: [[DIV31:%.*]] = sdiv i64 [[TMP28]], [[MUL30]] 5054 // CHECK11-NEXT: [[MUL32:%.*]] = mul nsw i64 [[DIV31]], 1 5055 // CHECK11-NEXT: [[ADD_PTR33:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[MUL32]] 5056 // CHECK11-NEXT: store i32* [[ADD_PTR33]], i32** [[__BEGIN119]], align 8 5057 // CHECK11-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 5058 // CHECK11-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5059 // CHECK11-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5060 // CHECK11-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 5061 // CHECK11-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 5062 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST34:%.*]] = ptrtoint i32* [[TMP34]] to i64 5063 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST35:%.*]] = ptrtoint i32* [[TMP35]] to i64 5064 // CHECK11-NEXT: [[SUB_PTR_SUB36:%.*]] = sub i64 [[SUB_PTR_LHS_CAST34]], [[SUB_PTR_RHS_CAST35]] 5065 // CHECK11-NEXT: [[SUB_PTR_DIV37:%.*]] = sdiv exact i64 [[SUB_PTR_SUB36]], 4 5066 // CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i64 [[SUB_PTR_DIV37]], 1 5067 // CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[SUB38]], 1 5068 // CHECK11-NEXT: [[DIV40:%.*]] = sdiv i64 [[ADD39]], 1 5069 // CHECK11-NEXT: [[MUL41:%.*]] = mul nsw i64 1, [[DIV40]] 5070 // CHECK11-NEXT: [[DIV42:%.*]] = sdiv i64 [[TMP33]], [[MUL41]] 5071 // CHECK11-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 5072 // CHECK11-NEXT: [[TMP37:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 5073 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST43:%.*]] = ptrtoint i32* [[TMP36]] to i64 5074 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST44:%.*]] = ptrtoint i32* [[TMP37]] to i64 5075 // CHECK11-NEXT: [[SUB_PTR_SUB45:%.*]] = sub i64 [[SUB_PTR_LHS_CAST43]], [[SUB_PTR_RHS_CAST44]] 5076 // CHECK11-NEXT: [[SUB_PTR_DIV46:%.*]] = sdiv exact i64 [[SUB_PTR_SUB45]], 4 5077 // CHECK11-NEXT: [[SUB47:%.*]] = sub nsw i64 [[SUB_PTR_DIV46]], 1 5078 // CHECK11-NEXT: [[ADD48:%.*]] = add nsw i64 [[SUB47]], 1 5079 // CHECK11-NEXT: [[DIV49:%.*]] = sdiv i64 [[ADD48]], 1 5080 // CHECK11-NEXT: [[MUL50:%.*]] = mul nsw i64 1, [[DIV49]] 5081 // CHECK11-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV42]], [[MUL50]] 5082 // CHECK11-NEXT: [[SUB52:%.*]] = sub nsw i64 [[TMP32]], [[MUL51]] 5083 // CHECK11-NEXT: [[MUL53:%.*]] = mul nsw i64 [[SUB52]], 1 5084 // CHECK11-NEXT: [[ADD_PTR54:%.*]] = getelementptr inbounds i32, i32* [[TMP31]], i64 [[MUL53]] 5085 // CHECK11-NEXT: store i32* [[ADD_PTR54]], i32** [[__BEGIN220]], align 8 5086 // CHECK11-NEXT: [[TMP38:%.*]] = load i32*, i32** [[__BEGIN119]], align 8 5087 // CHECK11-NEXT: store i32* [[TMP38]], i32** [[A]], align 8 5088 // CHECK11-NEXT: [[TMP39:%.*]] = load i32*, i32** [[__BEGIN220]], align 8 5089 // CHECK11-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP39]], align 4 5090 // CHECK11-NEXT: store i32 [[TMP40]], i32* [[B]], align 4 5091 // CHECK11-NEXT: [[TMP41:%.*]] = load i32, i32* [[B]], align 4 5092 // CHECK11-NEXT: [[TMP42:%.*]] = load i32*, i32** [[A]], align 8 5093 // CHECK11-NEXT: store i32 [[TMP41]], i32* [[TMP42]], align 4 5094 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5095 // CHECK11: omp.body.continue: 5096 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5097 // CHECK11: omp.inner.for.inc: 5098 // CHECK11-NEXT: [[TMP43:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5099 // CHECK11-NEXT: [[ADD55:%.*]] = add nsw i64 [[TMP43]], 1 5100 // CHECK11-NEXT: store i64 [[ADD55]], i64* [[DOTOMP_IV]], align 8 5101 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 5102 // CHECK11: omp.inner.for.end: 5103 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5104 // CHECK11: omp.loop.exit: 5105 // CHECK11-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5106 // CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 5107 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP45]]) 5108 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 5109 // CHECK11: omp.precond.end: 5110 // CHECK11-NEXT: ret void 5111 // 5112