1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 7 8 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-pc-linux-gnu -emit-pch -o %t %s 10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 14 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 15 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s 16 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 17 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11 18 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK12 19 20 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 21 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-pc-linux-gnu -emit-pch -o %t %s 22 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 23 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 24 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 25 26 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 27 28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // expected-no-diagnostics 30 #ifndef ARRAY 31 #ifndef HEADER 32 #define HEADER 33 34 enum omp_allocator_handle_t { 35 omp_null_allocator = 0, 36 omp_default_mem_alloc = 1, 37 omp_large_cap_mem_alloc = 2, 38 omp_const_mem_alloc = 3, 39 omp_high_bw_mem_alloc = 4, 40 omp_low_lat_mem_alloc = 5, 41 omp_cgroup_mem_alloc = 6, 42 omp_pteam_mem_alloc = 7, 43 omp_thread_mem_alloc = 8, 44 KMP_ALLOCATOR_MAX_HANDLE = __UINTPTR_MAX__ 45 }; 46 47 struct St { 48 int a, b; 49 St() : a(0), b(0) {} 50 St(const St &st) : a(st.a + st.b), b(0) {} 51 ~St() {} 52 }; 53 54 volatile int g __attribute__((aligned(128))) = 1212; 55 56 struct SS { 57 int a; 58 int b : 4; 59 int &c; 60 int e[4]; 61 SS(int &d) : a(0), b(0), c(d) { 62 #pragma omp parallel firstprivate(a, b, c, e) 63 #ifdef LAMBDA 64 [&]() { 65 ++this->a, --b, (this)->c /= 1; 66 #pragma omp parallel firstprivate(a, b, c) 67 ++(this)->a, --b, this->c /= 1; 68 }(); 69 #elif defined(BLOCKS) 70 ^{ 71 ++a; 72 --this->b; 73 (this)->c /= 1; 74 #pragma omp parallel firstprivate(a, b, c) 75 ++(this)->a, --b, this->c /= 1; 76 }(); 77 #else 78 ++this->a, --b, c /= 1, e[2] = 1111; 79 #endif 80 } 81 }; 82 83 template<typename T> 84 struct SST { 85 T a; 86 SST() : a(T()) { 87 #pragma omp parallel firstprivate(a) 88 #ifdef LAMBDA 89 [&]() { 90 [&]() { 91 ++this->a; 92 #pragma omp parallel firstprivate(a) 93 ++(this)->a; 94 }(); 95 }(); 96 #elif defined(BLOCKS) 97 ^{ 98 ^{ 99 ++a; 100 #pragma omp parallel firstprivate(a) 101 ++(this)->a; 102 }(); 103 }(); 104 #else 105 ++(this)->a; 106 #endif 107 } 108 }; 109 110 template <class T> 111 struct S { 112 T f; 113 S(T a) : f(a + g) {} 114 S() : f(g) {} 115 S(const S &s, St t = St()) : f(s.f + t.a) {} 116 operator T() { return T(); } 117 ~S() {} 118 }; 119 120 121 template <typename T> 122 T tmain() { 123 S<T> test; 124 SST<T> sst; 125 T t_var __attribute__((aligned(128))) = T(); 126 T vec[] __attribute__((aligned(128))) = {1, 2}; 127 S<T> s_arr[] __attribute__((aligned(128))) = {1, 2}; 128 S<T> var __attribute__((aligned(128))) (3); 129 #pragma omp parallel firstprivate(t_var, vec, s_arr, var) 130 { 131 vec[0] = t_var; 132 s_arr[0] = var; 133 } 134 #pragma omp parallel firstprivate(t_var) 135 {} 136 return T(); 137 } 138 139 int main() { 140 static int sivar; 141 SS ss(sivar); 142 #ifdef LAMBDA 143 [&]() { 144 #pragma omp parallel firstprivate(g, sivar) 145 { 146 147 148 149 g = 1; 150 sivar = 2; 151 [&]() { 152 g = 2; 153 sivar = 4; 154 }(); 155 } 156 }(); 157 return 0; 158 #elif defined(BLOCKS) 159 ^{ 160 #pragma omp parallel firstprivate(g, sivar) 161 { 162 g = 1; 163 sivar = 2; 164 ^{ 165 g = 2; 166 sivar = 4; 167 }(); 168 } 169 }(); 170 return 0; 171 172 173 #else 174 S<float> test; 175 int t_var = 0; 176 int vec[] = {1, 2}; 177 S<float> s_arr[] = {1, 2}; 178 S<float> var(3); 179 #pragma omp parallel firstprivate(t_var, vec, s_arr, var, sivar) 180 { 181 vec[0] = t_var; 182 s_arr[0] = var; 183 sivar = 2; 184 } 185 const int a = 0; 186 #pragma omp parallel allocate(omp_default_mem_alloc: t_var) firstprivate(t_var, a) 187 { t_var = a; } 188 return tmain<int>(); 189 #endif 190 } 191 192 193 194 195 196 197 198 199 200 201 202 203 204 #endif 205 #else 206 207 enum omp_allocator_handle_t { 208 omp_null_allocator = 0, 209 omp_default_mem_alloc = 1, 210 omp_large_cap_mem_alloc = 2, 211 omp_const_mem_alloc = 3, 212 omp_high_bw_mem_alloc = 4, 213 omp_low_lat_mem_alloc = 5, 214 omp_cgroup_mem_alloc = 6, 215 omp_pteam_mem_alloc = 7, 216 omp_thread_mem_alloc = 8, 217 KMP_ALLOCATOR_MAX_HANDLE = __UINTPTR_MAX__ 218 }; 219 220 struct St { 221 int a, b; 222 St() : a(0), b(0) {} 223 St(const St &) { } 224 ~St() {} 225 void St_func(St s[2], int n, long double vla1[n]) { 226 double vla2[n][n] __attribute__((aligned(128))); 227 a = b; 228 #pragma omp parallel allocate(omp_thread_mem_alloc:vla2) firstprivate(s, vla1, vla2) 229 vla1[b] = vla2[1][n - 1] = a = b; 230 } 231 }; 232 233 void array_func(float a[3], St s[2], int n, long double vla1[n]) { 234 double vla2[n][n] __attribute__((aligned(128))); 235 #pragma omp parallel firstprivate(a, s, vla1, vla2) 236 s[0].St_func(s, n, vla1); 237 ; 238 } 239 240 #endif 241 242 243 // CHECK1-LABEL: define {{[^@]+}}@main 244 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 245 // CHECK1-NEXT: entry: 246 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 247 // CHECK1-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 248 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 249 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 250 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 251 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 252 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 253 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 254 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 255 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 256 // CHECK1-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 257 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 258 // CHECK1-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 259 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 260 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 4 261 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 262 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) 263 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 264 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 265 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 266 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 267 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 268 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 269 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 270 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 271 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 272 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[SIVAR_CASTED]], align 4 273 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 274 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32 [[TMP4]]) 275 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 276 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 277 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[T_VAR_CASTED1]], align 4 278 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR_CASTED1]], align 4 279 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP6]]) 280 // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 281 // CHECK1-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 282 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] 283 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 284 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 285 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 286 // CHECK1: arraydestroy.body: 287 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 288 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 289 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 290 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 291 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 292 // CHECK1: arraydestroy.done2: 293 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 294 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 295 // CHECK1-NEXT: ret i32 [[TMP8]] 296 // 297 // 298 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 299 // CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 300 // CHECK1-NEXT: entry: 301 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 302 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 303 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 304 // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 305 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 306 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 307 // CHECK1-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 308 // CHECK1-NEXT: ret void 309 // 310 // 311 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 312 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 313 // CHECK1-NEXT: entry: 314 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 315 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 316 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 317 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 318 // CHECK1-NEXT: ret void 319 // 320 // 321 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 322 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 323 // CHECK1-NEXT: entry: 324 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 325 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 326 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 327 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 328 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 329 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 330 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 331 // CHECK1-NEXT: ret void 332 // 333 // 334 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 335 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 336 // CHECK1-NEXT: entry: 337 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 338 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 339 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 340 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 341 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 342 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 343 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 344 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 345 // CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 346 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 347 // CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 348 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 349 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 350 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 351 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 352 // CHECK1-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 353 // CHECK1-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 354 // CHECK1-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 355 // CHECK1-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 356 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 357 // CHECK1-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 358 // CHECK1-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 359 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 360 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 361 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 362 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 363 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 364 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 365 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 366 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 367 // CHECK1: omp.arraycpy.body: 368 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 369 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 370 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 371 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 372 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 373 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 374 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 375 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 376 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 377 // CHECK1: omp.arraycpy.done3: 378 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 379 // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 380 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] 381 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 382 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 0 383 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 384 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 385 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* 386 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 387 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 4, i1 false) 388 // CHECK1-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 389 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] 390 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 391 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 392 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 393 // CHECK1: arraydestroy.body: 394 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 395 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 396 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 397 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 398 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 399 // CHECK1: arraydestroy.done8: 400 // CHECK1-NEXT: ret void 401 // 402 // 403 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev 404 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 405 // CHECK1-NEXT: entry: 406 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 407 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 408 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 409 // CHECK1-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 410 // CHECK1-NEXT: ret void 411 // 412 // 413 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 414 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 415 // CHECK1-NEXT: entry: 416 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 417 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 418 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 419 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 420 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 421 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 422 // CHECK1-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 423 // CHECK1-NEXT: ret void 424 // 425 // 426 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev 427 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 428 // CHECK1-NEXT: entry: 429 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 430 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 431 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 432 // CHECK1-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 433 // CHECK1-NEXT: ret void 434 // 435 // 436 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 437 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 438 // CHECK1-NEXT: entry: 439 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 440 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 441 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 442 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 443 // CHECK1-NEXT: ret void 444 // 445 // 446 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 447 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { 448 // CHECK1-NEXT: entry: 449 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 450 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 451 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 452 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 453 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 454 // CHECK1-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 455 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 456 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 457 // CHECK1-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i32 4, i8* inttoptr (i32 1 to i8*)) 458 // CHECK1-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32* 459 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 460 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4 461 // CHECK1-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4 462 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8* 463 // CHECK1-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i32 1 to i8*)) 464 // CHECK1-NEXT: ret void 465 // 466 // 467 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 468 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] comdat { 469 // CHECK1-NEXT: entry: 470 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 471 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 472 // CHECK1-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 473 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 474 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 475 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 476 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 477 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 478 // CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) 479 // CHECK1-NEXT: store i32 0, i32* [[T_VAR]], align 128 480 // CHECK1-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 481 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 482 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 483 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 484 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 485 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 486 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 487 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) 488 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[T_VAR]]) 489 // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 490 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 491 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 492 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 493 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 494 // CHECK1: arraydestroy.body: 495 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 496 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 497 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 498 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 499 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 500 // CHECK1: arraydestroy.done1: 501 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 502 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 503 // CHECK1-NEXT: ret i32 [[TMP2]] 504 // 505 // 506 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 507 // CHECK1-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 508 // CHECK1-NEXT: entry: 509 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 510 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 511 // CHECK1-NEXT: [[A2:%.*]] = alloca i32*, align 4 512 // CHECK1-NEXT: [[B4:%.*]] = alloca i32, align 4 513 // CHECK1-NEXT: [[C7:%.*]] = alloca i32*, align 4 514 // CHECK1-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4 515 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 516 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 517 // CHECK1-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 518 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 519 // CHECK1-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 520 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 521 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 522 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 523 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 524 // CHECK1-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 525 // CHECK1-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 526 // CHECK1-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 527 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 528 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 529 // CHECK1-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 530 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 531 // CHECK1-NEXT: store i32* [[A3]], i32** [[A2]], align 4 532 // CHECK1-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 533 // CHECK1-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 534 // CHECK1-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 535 // CHECK1-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 536 // CHECK1-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 537 // CHECK1-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 538 // CHECK1-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 539 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4 540 // CHECK1-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4 541 // CHECK1-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 542 // CHECK1-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4 543 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4 544 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 545 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 546 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 547 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 548 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 549 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 550 // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 4 551 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 552 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[C_CASTED]], align 4 553 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4 554 // CHECK1-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4 555 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32, i32, i32, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], [4 x i32]* [[TMP10]]) 556 // CHECK1-NEXT: ret void 557 // 558 // 559 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 560 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] { 561 // CHECK1-NEXT: entry: 562 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 563 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 564 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 565 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 566 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 567 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 568 // CHECK1-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 4 569 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 4 570 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 571 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca [4 x i32]*, align 4 572 // CHECK1-NEXT: [[E3:%.*]] = alloca [4 x i32], align 4 573 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 4 574 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 575 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 576 // CHECK1-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 577 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 578 // CHECK1-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 579 // CHECK1-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 580 // CHECK1-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 4 581 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 582 // CHECK1-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 4 583 // CHECK1-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4 584 // CHECK1-NEXT: store i32* [[C_ADDR]], i32** [[_TMP1]], align 4 585 // CHECK1-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP2]], align 4 586 // CHECK1-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP2]], align 4 587 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E3]] to i8* 588 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* 589 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 16, i1 false) 590 // CHECK1-NEXT: store [4 x i32]* [[E3]], [4 x i32]** [[_TMP4]], align 4 591 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 4 592 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 593 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 594 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 595 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[B_ADDR]], align 4 596 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 597 // CHECK1-NEXT: store i32 [[DEC]], i32* [[B_ADDR]], align 4 598 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP1]], align 4 599 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 600 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 601 // CHECK1-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 602 // CHECK1-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 4 603 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i32 0, i32 2 604 // CHECK1-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 605 // CHECK1-NEXT: ret void 606 // 607 // 608 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 609 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 610 // CHECK1-NEXT: entry: 611 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 612 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 613 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 614 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 615 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 616 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 617 // CHECK1-NEXT: store float [[CONV]], float* [[F]], align 4 618 // CHECK1-NEXT: ret void 619 // 620 // 621 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 622 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 623 // CHECK1-NEXT: entry: 624 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 625 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 626 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 627 // CHECK1-NEXT: store float [[A]], float* [[A_ADDR]], align 4 628 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 629 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 630 // CHECK1-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 631 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 632 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 633 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 634 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 635 // CHECK1-NEXT: ret void 636 // 637 // 638 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev 639 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 640 // CHECK1-NEXT: entry: 641 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 642 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 643 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 644 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 645 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 646 // CHECK1-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 647 // CHECK1-NEXT: store i32 0, i32* [[B]], align 4 648 // CHECK1-NEXT: ret void 649 // 650 // 651 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 652 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 653 // CHECK1-NEXT: entry: 654 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 655 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 656 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 657 // CHECK1-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 658 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 659 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 660 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 661 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 662 // CHECK1-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 663 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 664 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 665 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 666 // CHECK1-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 667 // CHECK1-NEXT: store float [[ADD]], float* [[F]], align 4 668 // CHECK1-NEXT: ret void 669 // 670 // 671 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev 672 // CHECK1-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 673 // CHECK1-NEXT: entry: 674 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 675 // CHECK1-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 676 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 677 // CHECK1-NEXT: ret void 678 // 679 // 680 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 681 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 682 // CHECK1-NEXT: entry: 683 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 684 // CHECK1-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 685 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 686 // CHECK1-NEXT: ret void 687 // 688 // 689 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 690 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 691 // CHECK1-NEXT: entry: 692 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 693 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 694 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 695 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 696 // CHECK1-NEXT: ret void 697 // 698 // 699 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 700 // CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 701 // CHECK1-NEXT: entry: 702 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 703 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 704 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 705 // CHECK1-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) 706 // CHECK1-NEXT: ret void 707 // 708 // 709 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 710 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 711 // CHECK1-NEXT: entry: 712 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 713 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 714 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 715 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 716 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 717 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 718 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 719 // CHECK1-NEXT: ret void 720 // 721 // 722 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 723 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 724 // CHECK1-NEXT: entry: 725 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 726 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 727 // CHECK1-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 728 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 729 // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 730 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 731 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 732 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 733 // CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 734 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 735 // CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 736 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 737 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 738 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 739 // CHECK1-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 740 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 741 // CHECK1-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 742 // CHECK1-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 743 // CHECK1-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 744 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 745 // CHECK1-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 746 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 747 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 748 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 749 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 750 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 751 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i32 8, i1 false) 752 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 753 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 754 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 755 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 756 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 757 // CHECK1: omp.arraycpy.body: 758 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 759 // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 760 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 761 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 762 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 763 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 764 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 765 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 766 // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 767 // CHECK1: omp.arraycpy.done4: 768 // CHECK1-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 769 // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 770 // CHECK1-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 771 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 772 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 773 // CHECK1-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 774 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 775 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 776 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 777 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 4, i1 false) 778 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 779 // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 780 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 781 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 782 // CHECK1: arraydestroy.body: 783 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 784 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 785 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 786 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 787 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 788 // CHECK1: arraydestroy.done9: 789 // CHECK1-NEXT: ret void 790 // 791 // 792 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 793 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 794 // CHECK1-NEXT: entry: 795 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 796 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 797 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 798 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 799 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 800 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 801 // CHECK1-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 802 // CHECK1-NEXT: ret void 803 // 804 // 805 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 806 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 807 // CHECK1-NEXT: entry: 808 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 809 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 810 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 811 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 812 // CHECK1-NEXT: ret void 813 // 814 // 815 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 816 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 817 // CHECK1-NEXT: entry: 818 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 819 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 820 // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 821 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 822 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 823 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 824 // CHECK1-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 825 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 826 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 827 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 828 // CHECK1-NEXT: ret void 829 // 830 // 831 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 832 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 833 // CHECK1-NEXT: entry: 834 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 835 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 836 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 837 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 838 // CHECK1-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 839 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 840 // CHECK1-NEXT: ret void 841 // 842 // 843 // CHECK1-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 844 // CHECK1-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 845 // CHECK1-NEXT: entry: 846 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 847 // CHECK1-NEXT: [[A2:%.*]] = alloca i32*, align 4 848 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 849 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 850 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 851 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 852 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 853 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 854 // CHECK1-NEXT: store i32* [[A3]], i32** [[A2]], align 4 855 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 4 856 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 857 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 858 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 859 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.SST* [[THIS1]], i32 [[TMP2]]) 860 // CHECK1-NEXT: ret void 861 // 862 // 863 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 864 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { 865 // CHECK1-NEXT: entry: 866 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 867 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 868 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 869 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 870 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32*, align 4 871 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 872 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 873 // CHECK1-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 874 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 875 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 876 // CHECK1-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4 877 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 878 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 879 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 880 // CHECK1-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 881 // CHECK1-NEXT: ret void 882 // 883 // 884 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 885 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 886 // CHECK1-NEXT: entry: 887 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 888 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 889 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 890 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 891 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 892 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 893 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 894 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 895 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 896 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 897 // CHECK1-NEXT: ret void 898 // 899 // 900 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 901 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 902 // CHECK1-NEXT: entry: 903 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 904 // CHECK1-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 905 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 906 // CHECK1-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 907 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 908 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 909 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 910 // CHECK1-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 911 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 912 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 913 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 914 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 915 // CHECK1-NEXT: store i32 [[ADD]], i32* [[F]], align 4 916 // CHECK1-NEXT: ret void 917 // 918 // 919 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 920 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 921 // CHECK1-NEXT: entry: 922 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 923 // CHECK1-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 924 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 925 // CHECK1-NEXT: ret void 926 // 927 // 928 // CHECK2-LABEL: define {{[^@]+}}@main 929 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 930 // CHECK2-NEXT: entry: 931 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 932 // CHECK2-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 933 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 934 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 935 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 936 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 937 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 938 // CHECK2-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 939 // CHECK2-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 940 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 941 // CHECK2-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 942 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 943 // CHECK2-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 944 // CHECK2-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 945 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 4 946 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 947 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) 948 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 949 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 950 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 951 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 952 // CHECK2-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 953 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 954 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[T_VAR_CASTED]], align 4 955 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 956 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 957 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[SIVAR_CASTED]], align 4 958 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 959 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32, [2 x %struct.S]*, %struct.S*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i32 [[TMP4]]) 960 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 961 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 962 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[T_VAR_CASTED1]], align 4 963 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[T_VAR_CASTED1]], align 4 964 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP6]]) 965 // CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 966 // CHECK2-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 967 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] 968 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 969 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 970 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 971 // CHECK2: arraydestroy.body: 972 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 973 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 974 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 975 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 976 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] 977 // CHECK2: arraydestroy.done2: 978 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 979 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 980 // CHECK2-NEXT: ret i32 [[TMP8]] 981 // 982 // 983 // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 984 // CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 985 // CHECK2-NEXT: entry: 986 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 987 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 988 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 989 // CHECK2-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 990 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 991 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 992 // CHECK2-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 993 // CHECK2-NEXT: ret void 994 // 995 // 996 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 997 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 998 // CHECK2-NEXT: entry: 999 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1000 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1001 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1002 // CHECK2-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 1003 // CHECK2-NEXT: ret void 1004 // 1005 // 1006 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 1007 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1008 // CHECK2-NEXT: entry: 1009 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1010 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1011 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1012 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1013 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1014 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1015 // CHECK2-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 1016 // CHECK2-NEXT: ret void 1017 // 1018 // 1019 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1020 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 1021 // CHECK2-NEXT: entry: 1022 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1023 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1024 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1025 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1026 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 1027 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 1028 // CHECK2-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1029 // CHECK2-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 1030 // CHECK2-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 1031 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1032 // CHECK2-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 1033 // CHECK2-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 1034 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1035 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1036 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1037 // CHECK2-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1038 // CHECK2-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1039 // CHECK2-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 1040 // CHECK2-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1041 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1042 // CHECK2-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 1043 // CHECK2-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 1044 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC1]] to i8* 1045 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1046 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 8, i1 false) 1047 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 1048 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 1049 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 1050 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 1051 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1052 // CHECK2: omp.arraycpy.body: 1053 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1054 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1055 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1056 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1057 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 1058 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1059 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1060 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 1061 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] 1062 // CHECK2: omp.arraycpy.done3: 1063 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) 1064 // CHECK2-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP5]]) 1065 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] 1066 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 1067 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC1]], i32 0, i32 0 1068 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 1069 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 1070 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX6]] to i8* 1071 // CHECK2-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR4]] to i8* 1072 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i32 4, i1 false) 1073 // CHECK2-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 1074 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] 1075 // CHECK2-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR2]], i32 0, i32 0 1076 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN7]], i32 2 1077 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1078 // CHECK2: arraydestroy.body: 1079 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1080 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1081 // CHECK2-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1082 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 1083 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 1084 // CHECK2: arraydestroy.done8: 1085 // CHECK2-NEXT: ret void 1086 // 1087 // 1088 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC1Ev 1089 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1090 // CHECK2-NEXT: entry: 1091 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1092 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1093 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1094 // CHECK2-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 1095 // CHECK2-NEXT: ret void 1096 // 1097 // 1098 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 1099 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1100 // CHECK2-NEXT: entry: 1101 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1102 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 1103 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1104 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 1105 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1106 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 1107 // CHECK2-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1108 // CHECK2-NEXT: ret void 1109 // 1110 // 1111 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD1Ev 1112 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1113 // CHECK2-NEXT: entry: 1114 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1115 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1116 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1117 // CHECK2-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 1118 // CHECK2-NEXT: ret void 1119 // 1120 // 1121 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 1122 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1123 // CHECK2-NEXT: entry: 1124 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1125 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1126 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1127 // CHECK2-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1128 // CHECK2-NEXT: ret void 1129 // 1130 // 1131 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 1132 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[T_VAR:%.*]]) #[[ATTR3]] { 1133 // CHECK2-NEXT: entry: 1134 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1135 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1136 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 1137 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1138 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1139 // CHECK2-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 1140 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1141 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1142 // CHECK2-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i32 4, i8* inttoptr (i32 1 to i8*)) 1143 // CHECK2-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32* 1144 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR_ADDR]], align 4 1145 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4 1146 // CHECK2-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4 1147 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8* 1148 // CHECK2-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i32 1 to i8*)) 1149 // CHECK2-NEXT: ret void 1150 // 1151 // 1152 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 1153 // CHECK2-SAME: () #[[ATTR5:[0-9]+]] comdat { 1154 // CHECK2-NEXT: entry: 1155 // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1156 // CHECK2-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 1157 // CHECK2-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 1158 // CHECK2-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 1159 // CHECK2-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 1160 // CHECK2-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 1161 // CHECK2-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 1162 // CHECK2-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 1163 // CHECK2-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) 1164 // CHECK2-NEXT: store i32 0, i32* [[T_VAR]], align 128 1165 // CHECK2-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 1166 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) 1167 // CHECK2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1168 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 1169 // CHECK2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 1170 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 1171 // CHECK2-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 1172 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) 1173 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[T_VAR]]) 1174 // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 1175 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 1176 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 1177 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1178 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1179 // CHECK2: arraydestroy.body: 1180 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1181 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1182 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1183 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 1184 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 1185 // CHECK2: arraydestroy.done1: 1186 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 1187 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 1188 // CHECK2-NEXT: ret i32 [[TMP2]] 1189 // 1190 // 1191 // CHECK2-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 1192 // CHECK2-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1193 // CHECK2-NEXT: entry: 1194 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 1195 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 1196 // CHECK2-NEXT: [[A2:%.*]] = alloca i32*, align 4 1197 // CHECK2-NEXT: [[B4:%.*]] = alloca i32, align 4 1198 // CHECK2-NEXT: [[C7:%.*]] = alloca i32*, align 4 1199 // CHECK2-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4 1200 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1201 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1202 // CHECK2-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 1203 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 1204 // CHECK2-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 1205 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 1206 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 1207 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1208 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 1209 // CHECK2-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 1210 // CHECK2-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 1211 // CHECK2-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 1212 // CHECK2-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 1213 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 1214 // CHECK2-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 1215 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 1216 // CHECK2-NEXT: store i32* [[A3]], i32** [[A2]], align 4 1217 // CHECK2-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 1218 // CHECK2-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 1219 // CHECK2-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 1220 // CHECK2-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 1221 // CHECK2-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 1222 // CHECK2-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 1223 // CHECK2-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 1224 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4 1225 // CHECK2-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4 1226 // CHECK2-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 1227 // CHECK2-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4 1228 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4 1229 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1230 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 1231 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 1232 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 1233 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 1234 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 1235 // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 4 1236 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 1237 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[C_CASTED]], align 4 1238 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4 1239 // CHECK2-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4 1240 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32, i32, i32, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], [4 x i32]* [[TMP10]]) 1241 // CHECK2-NEXT: ret void 1242 // 1243 // 1244 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 1245 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] { 1246 // CHECK2-NEXT: entry: 1247 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1248 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1249 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 1250 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1251 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1252 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 1253 // CHECK2-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 4 1254 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32*, align 4 1255 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 1256 // CHECK2-NEXT: [[_TMP2:%.*]] = alloca [4 x i32]*, align 4 1257 // CHECK2-NEXT: [[E3:%.*]] = alloca [4 x i32], align 4 1258 // CHECK2-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 4 1259 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1260 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1261 // CHECK2-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 1262 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1263 // CHECK2-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1264 // CHECK2-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 1265 // CHECK2-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 4 1266 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 1267 // CHECK2-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 4 1268 // CHECK2-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4 1269 // CHECK2-NEXT: store i32* [[C_ADDR]], i32** [[_TMP1]], align 4 1270 // CHECK2-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP2]], align 4 1271 // CHECK2-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP2]], align 4 1272 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E3]] to i8* 1273 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* 1274 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 16, i1 false) 1275 // CHECK2-NEXT: store [4 x i32]* [[E3]], [4 x i32]** [[_TMP4]], align 4 1276 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 4 1277 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 1278 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 1279 // CHECK2-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 1280 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[B_ADDR]], align 4 1281 // CHECK2-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 1282 // CHECK2-NEXT: store i32 [[DEC]], i32* [[B_ADDR]], align 4 1283 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP1]], align 4 1284 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 1285 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 1286 // CHECK2-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 1287 // CHECK2-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 4 1288 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i32 0, i32 2 1289 // CHECK2-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 1290 // CHECK2-NEXT: ret void 1291 // 1292 // 1293 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 1294 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1295 // CHECK2-NEXT: entry: 1296 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1297 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1298 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1299 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1300 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 1301 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 1302 // CHECK2-NEXT: store float [[CONV]], float* [[F]], align 4 1303 // CHECK2-NEXT: ret void 1304 // 1305 // 1306 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 1307 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1308 // CHECK2-NEXT: entry: 1309 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1310 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 1311 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1312 // CHECK2-NEXT: store float [[A]], float* [[A_ADDR]], align 4 1313 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1314 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1315 // CHECK2-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 1316 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 1317 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 1318 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 1319 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 1320 // CHECK2-NEXT: ret void 1321 // 1322 // 1323 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StC2Ev 1324 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1325 // CHECK2-NEXT: entry: 1326 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1327 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1328 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1329 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 1330 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1331 // CHECK2-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 1332 // CHECK2-NEXT: store i32 0, i32* [[B]], align 4 1333 // CHECK2-NEXT: ret void 1334 // 1335 // 1336 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 1337 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1338 // CHECK2-NEXT: entry: 1339 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1340 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 4 1341 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1342 // CHECK2-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 4 1343 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1344 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 1345 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 4 1346 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 1347 // CHECK2-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 1348 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1349 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1350 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 1351 // CHECK2-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 1352 // CHECK2-NEXT: store float [[ADD]], float* [[F]], align 4 1353 // CHECK2-NEXT: ret void 1354 // 1355 // 1356 // CHECK2-LABEL: define {{[^@]+}}@_ZN2StD2Ev 1357 // CHECK2-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1358 // CHECK2-NEXT: entry: 1359 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 4 1360 // CHECK2-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 4 1361 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 4 1362 // CHECK2-NEXT: ret void 1363 // 1364 // 1365 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 1366 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1367 // CHECK2-NEXT: entry: 1368 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 1369 // CHECK2-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 1370 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 1371 // CHECK2-NEXT: ret void 1372 // 1373 // 1374 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 1375 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1376 // CHECK2-NEXT: entry: 1377 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1378 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1379 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1380 // CHECK2-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 1381 // CHECK2-NEXT: ret void 1382 // 1383 // 1384 // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 1385 // CHECK2-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1386 // CHECK2-NEXT: entry: 1387 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 1388 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 1389 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 1390 // CHECK2-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) 1391 // CHECK2-NEXT: ret void 1392 // 1393 // 1394 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 1395 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1396 // CHECK2-NEXT: entry: 1397 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1398 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1399 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1400 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1401 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1402 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1403 // CHECK2-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 1404 // CHECK2-NEXT: ret void 1405 // 1406 // 1407 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 1408 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 1409 // CHECK2-NEXT: entry: 1410 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1411 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1412 // CHECK2-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 1413 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 1414 // CHECK2-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 1415 // CHECK2-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 1416 // CHECK2-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1417 // CHECK2-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 1418 // CHECK2-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 1419 // CHECK2-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 1420 // CHECK2-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 1421 // CHECK2-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 1422 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1423 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1424 // CHECK2-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 1425 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 1426 // CHECK2-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1427 // CHECK2-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 1428 // CHECK2-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 1429 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 1430 // CHECK2-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 1431 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 1432 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 1433 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 1434 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 1435 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 1436 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i32 8, i1 false) 1437 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1438 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 1439 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 1440 // CHECK2-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 1441 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 1442 // CHECK2: omp.arraycpy.body: 1443 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1444 // CHECK2-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 1445 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 1446 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 1447 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 1448 // CHECK2-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 1449 // CHECK2-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 1450 // CHECK2-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 1451 // CHECK2-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 1452 // CHECK2: omp.arraycpy.done4: 1453 // CHECK2-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 1454 // CHECK2-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 1455 // CHECK2-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 1456 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 1457 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i32 0, i32 0 1458 // CHECK2-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 1459 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1460 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 1461 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 1462 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i32 4, i1 false) 1463 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 1464 // CHECK2-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 1465 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i32 2 1466 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 1467 // CHECK2: arraydestroy.body: 1468 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 1469 // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 1470 // CHECK2-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 1471 // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 1472 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 1473 // CHECK2: arraydestroy.done9: 1474 // CHECK2-NEXT: ret void 1475 // 1476 // 1477 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 1478 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1479 // CHECK2-NEXT: entry: 1480 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1481 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 1482 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1483 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 1484 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1485 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 1486 // CHECK2-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 1487 // CHECK2-NEXT: ret void 1488 // 1489 // 1490 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 1491 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1492 // CHECK2-NEXT: entry: 1493 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1494 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1495 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1496 // CHECK2-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 1497 // CHECK2-NEXT: ret void 1498 // 1499 // 1500 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 1501 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 1502 // CHECK2-NEXT: entry: 1503 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1504 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1505 // CHECK2-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 1506 // CHECK2-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 1507 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1508 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1509 // CHECK2-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 1510 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 1511 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 1512 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 1513 // CHECK2-NEXT: ret void 1514 // 1515 // 1516 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 1517 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1518 // CHECK2-NEXT: entry: 1519 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1520 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1521 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1522 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1523 // CHECK2-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 1524 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 1525 // CHECK2-NEXT: ret void 1526 // 1527 // 1528 // CHECK2-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 1529 // CHECK2-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1530 // CHECK2-NEXT: entry: 1531 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 1532 // CHECK2-NEXT: [[A2:%.*]] = alloca i32*, align 4 1533 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1534 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 1535 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 1536 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 1537 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1538 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 1539 // CHECK2-NEXT: store i32* [[A3]], i32** [[A2]], align 4 1540 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 4 1541 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1542 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 1543 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 1544 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.SST* [[THIS1]], i32 [[TMP2]]) 1545 // CHECK2-NEXT: ret void 1546 // 1547 // 1548 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 1549 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { 1550 // CHECK2-NEXT: entry: 1551 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1552 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1553 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 4 1554 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1555 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32*, align 4 1556 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1557 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1558 // CHECK2-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 4 1559 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1560 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 4 1561 // CHECK2-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4 1562 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 1563 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1564 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 1565 // CHECK2-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 1566 // CHECK2-NEXT: ret void 1567 // 1568 // 1569 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 1570 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1571 // CHECK2-NEXT: entry: 1572 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1573 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1574 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1575 // CHECK2-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1576 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1577 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1578 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1579 // CHECK2-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 1580 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 1581 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1582 // CHECK2-NEXT: ret void 1583 // 1584 // 1585 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 1586 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1587 // CHECK2-NEXT: entry: 1588 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1589 // CHECK2-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 4 1590 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1591 // CHECK2-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 4 1592 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1593 // CHECK2-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 1594 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 4 1595 // CHECK2-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 1596 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 1597 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 1598 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 1599 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 1600 // CHECK2-NEXT: store i32 [[ADD]], i32* [[F]], align 4 1601 // CHECK2-NEXT: ret void 1602 // 1603 // 1604 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 1605 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1606 // CHECK2-NEXT: entry: 1607 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 1608 // CHECK2-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 1609 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 1610 // CHECK2-NEXT: ret void 1611 // 1612 // 1613 // CHECK3-LABEL: define {{[^@]+}}@main 1614 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1615 // CHECK3-NEXT: entry: 1616 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1617 // CHECK3-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 1618 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 1619 // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 1620 // CHECK3-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 1621 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 1622 // CHECK3-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 4 1623 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(4) [[REF_TMP]]) 1624 // CHECK3-NEXT: ret i32 0 1625 // 1626 // 1627 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 1628 // CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1629 // CHECK3-NEXT: entry: 1630 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 1631 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 1632 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 1633 // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 1634 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 1635 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 1636 // CHECK3-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 1637 // CHECK3-NEXT: ret void 1638 // 1639 // 1640 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 1641 // CHECK3-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1642 // CHECK3-NEXT: entry: 1643 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 1644 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 1645 // CHECK3-NEXT: [[A2:%.*]] = alloca i32*, align 4 1646 // CHECK3-NEXT: [[B4:%.*]] = alloca i32, align 4 1647 // CHECK3-NEXT: [[C7:%.*]] = alloca i32*, align 4 1648 // CHECK3-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4 1649 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1650 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1651 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 1652 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 1653 // CHECK3-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 1654 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 1655 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 1656 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1657 // CHECK3-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 1658 // CHECK3-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 1659 // CHECK3-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 1660 // CHECK3-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 1661 // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 1662 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 1663 // CHECK3-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 1664 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 1665 // CHECK3-NEXT: store i32* [[A3]], i32** [[A2]], align 4 1666 // CHECK3-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 1667 // CHECK3-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 1668 // CHECK3-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 1669 // CHECK3-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 1670 // CHECK3-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 1671 // CHECK3-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 1672 // CHECK3-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 1673 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4 1674 // CHECK3-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4 1675 // CHECK3-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 1676 // CHECK3-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4 1677 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4 1678 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 1679 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 1680 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 1681 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 1682 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 1683 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 1684 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 4 1685 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 1686 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[C_CASTED]], align 4 1687 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4 1688 // CHECK3-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4 1689 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32, i32, i32, [4 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], [4 x i32]* [[TMP10]]) 1690 // CHECK3-NEXT: ret void 1691 // 1692 // 1693 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1694 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3:[0-9]+]] { 1695 // CHECK3-NEXT: entry: 1696 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1697 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1698 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 1699 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1700 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1701 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 1702 // CHECK3-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 4 1703 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 4 1704 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 1705 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca [4 x i32]*, align 4 1706 // CHECK3-NEXT: [[E3:%.*]] = alloca [4 x i32], align 4 1707 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 4 1708 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 1709 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1710 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1711 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 1712 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1713 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1714 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 1715 // CHECK3-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 4 1716 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 1717 // CHECK3-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 4 1718 // CHECK3-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4 1719 // CHECK3-NEXT: store i32* [[C_ADDR]], i32** [[_TMP1]], align 4 1720 // CHECK3-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP2]], align 4 1721 // CHECK3-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP2]], align 4 1722 // CHECK3-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E3]] to i8* 1723 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* 1724 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 16, i1 false) 1725 // CHECK3-NEXT: store [4 x i32]* [[E3]], [4 x i32]** [[_TMP4]], align 4 1726 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 1727 // CHECK3-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[TMP5]], align 4 1728 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 1729 // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 4 1730 // CHECK3-NEXT: store i32* [[TMP7]], i32** [[TMP6]], align 4 1731 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 1732 // CHECK3-NEXT: store i32* [[B_ADDR]], i32** [[TMP8]], align 4 1733 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 1734 // CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP1]], align 4 1735 // CHECK3-NEXT: store i32* [[TMP10]], i32** [[TMP9]], align 4 1736 // CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) 1737 // CHECK3-NEXT: ret void 1738 // 1739 // 1740 // CHECK3-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv 1741 // CHECK3-SAME: (%class.anon.0* nonnull align 4 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { 1742 // CHECK3-NEXT: entry: 1743 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 4 1744 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1745 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1746 // CHECK3-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 1747 // CHECK3-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 4 1748 // CHECK3-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 4 1749 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 1750 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 4 1751 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 1752 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 4 1753 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 1754 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 1755 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 1756 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 1757 // CHECK3-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 4 1758 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 1759 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 1760 // CHECK3-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 1761 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 1762 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 4 1763 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1764 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 1765 // CHECK3-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 1766 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 1767 // CHECK3-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 4 1768 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 1769 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[A_CASTED]], align 4 1770 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[A_CASTED]], align 4 1771 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 1772 // CHECK3-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 4 1773 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 1774 // CHECK3-NEXT: store i32 [[TMP17]], i32* [[B_CASTED]], align 4 1775 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[B_CASTED]], align 4 1776 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 1777 // CHECK3-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP19]], align 4 1778 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 1779 // CHECK3-NEXT: store i32 [[TMP21]], i32* [[C_CASTED]], align 4 1780 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[C_CASTED]], align 4 1781 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP1]], i32 [[TMP14]], i32 [[TMP18]], i32 [[TMP22]]) 1782 // CHECK3-NEXT: ret void 1783 // 1784 // 1785 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 1786 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR3]] { 1787 // CHECK3-NEXT: entry: 1788 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1789 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1790 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 1791 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1792 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1793 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 1794 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32*, align 4 1795 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 1796 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1797 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1798 // CHECK3-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 1799 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1800 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1801 // CHECK3-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 1802 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 1803 // CHECK3-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4 1804 // CHECK3-NEXT: store i32* [[C_ADDR]], i32** [[_TMP1]], align 4 1805 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 1806 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1807 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 1808 // CHECK3-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 1809 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 1810 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 1811 // CHECK3-NEXT: store i32 [[DEC]], i32* [[B_ADDR]], align 4 1812 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 4 1813 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1814 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 1815 // CHECK3-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 1816 // CHECK3-NEXT: ret void 1817 // 1818 // 1819 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 1820 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR3]] { 1821 // CHECK3-NEXT: entry: 1822 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1823 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1824 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 1825 // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1826 // CHECK3-NEXT: [[G1:%.*]] = alloca i32, align 128 1827 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 4 1828 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1829 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1830 // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 1831 // CHECK3-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1832 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4 1833 // CHECK3-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128 1834 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 1835 // CHECK3-NEXT: store i32 1, i32* [[G1]], align 128 1836 // CHECK3-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 1837 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 1838 // CHECK3-NEXT: store i32* [[G1]], i32** [[TMP2]], align 4 1839 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 1840 // CHECK3-NEXT: store i32* [[SIVAR_ADDR]], i32** [[TMP3]], align 4 1841 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 4 dereferenceable(8) [[REF_TMP]]) 1842 // CHECK3-NEXT: ret void 1843 // 1844 // 1845 // CHECK4-LABEL: define {{[^@]+}}@main 1846 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 1847 // CHECK4-NEXT: entry: 1848 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 1849 // CHECK4-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 4 1850 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 4 1851 // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 1852 // CHECK4-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 1853 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 1854 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 4 1855 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 1856 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 4 1857 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 1858 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 1859 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 1860 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 4 1861 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 1862 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i32, i32, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 4 1863 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 1864 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1865 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 4 1866 // CHECK4-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* 1867 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* 1868 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 1869 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 1870 // CHECK4-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 4 1871 // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* 1872 // CHECK4-NEXT: call void [[TMP5]](i8* [[TMP3]]) 1873 // CHECK4-NEXT: ret i32 0 1874 // 1875 // 1876 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 1877 // CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 1878 // CHECK4-NEXT: entry: 1879 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 1880 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 1881 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 1882 // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 1883 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 1884 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 1885 // CHECK4-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 4 dereferenceable(28) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 1886 // CHECK4-NEXT: ret void 1887 // 1888 // 1889 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke 1890 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 1891 // CHECK4-NEXT: entry: 1892 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 4 1893 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 4 1894 // CHECK4-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 1895 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4 1896 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* 1897 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 4 1898 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 1899 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[SIVAR_CASTED]], align 4 1900 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIVAR_CASTED]], align 4 1901 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @g, i32 [[TMP1]]) 1902 // CHECK4-NEXT: ret void 1903 // 1904 // 1905 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 1906 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i32 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 1907 // CHECK4-NEXT: entry: 1908 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1909 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1910 // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 1911 // CHECK4-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 1912 // CHECK4-NEXT: [[G1:%.*]] = alloca i32, align 128 1913 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, align 128 1914 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1915 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1916 // CHECK4-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 1917 // CHECK4-NEXT: store i32 [[SIVAR]], i32* [[SIVAR_ADDR]], align 4 1918 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 4 1919 // CHECK4-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128 1920 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 1921 // CHECK4-NEXT: store i32 1, i32* [[G1]], align 128 1922 // CHECK4-NEXT: store i32 2, i32* [[SIVAR_ADDR]], align 4 1923 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 0 1924 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 1925 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 1 1926 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 4 1927 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 2 1928 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 8 1929 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 3 1930 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 4 1931 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 4 1932 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i32, i32, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 16 1933 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 1934 // CHECK4-NEXT: [[TMP2:%.*]] = load volatile i32, i32* [[G1]], align 128 1935 // CHECK4-NEXT: store volatile i32 [[TMP2]], i32* [[BLOCK_CAPTURED]], align 128 1936 // CHECK4-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 1937 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[SIVAR_ADDR]], align 4 1938 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[BLOCK_CAPTURED2]], align 4 1939 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]] to void ()* 1940 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP4]] to %struct.__block_literal_generic* 1941 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 1942 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 1943 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP5]], align 4 1944 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to void (i8*)* 1945 // CHECK4-NEXT: call void [[TMP8]](i8* [[TMP6]]) 1946 // CHECK4-NEXT: ret void 1947 // 1948 // 1949 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke 1950 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 1951 // CHECK4-NEXT: entry: 1952 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 4 1953 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>*, align 4 1954 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4 1955 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* 1956 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>** [[BLOCK_ADDR]], align 4 1957 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 1958 // CHECK4-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 1959 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [104 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 1960 // CHECK4-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 1961 // CHECK4-NEXT: ret void 1962 // 1963 // 1964 // CHECK4-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 1965 // CHECK4-SAME: (%struct.SS* nonnull align 4 dereferenceable(28) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 1966 // CHECK4-NEXT: entry: 1967 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 1968 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 4 1969 // CHECK4-NEXT: [[A2:%.*]] = alloca i32*, align 4 1970 // CHECK4-NEXT: [[B4:%.*]] = alloca i32, align 4 1971 // CHECK4-NEXT: [[C7:%.*]] = alloca i32*, align 4 1972 // CHECK4-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 4 1973 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1974 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1975 // CHECK4-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 1976 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 1977 // CHECK4-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 4 1978 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 1979 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 1980 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 1981 // CHECK4-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 1982 // CHECK4-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 1983 // CHECK4-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 1984 // CHECK4-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 1985 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 1986 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 4 1987 // CHECK4-NEXT: store i32* [[TMP0]], i32** [[C]], align 4 1988 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 1989 // CHECK4-NEXT: store i32* [[A3]], i32** [[A2]], align 4 1990 // CHECK4-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 1991 // CHECK4-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 1992 // CHECK4-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 1993 // CHECK4-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 1994 // CHECK4-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 1995 // CHECK4-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 1996 // CHECK4-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 1997 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 4 1998 // CHECK4-NEXT: store i32* [[TMP1]], i32** [[C7]], align 4 1999 // CHECK4-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 2000 // CHECK4-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 4 2001 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 4 2002 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2003 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 2004 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 2005 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 2006 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 2007 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 2008 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 4 2009 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 2010 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[C_CASTED]], align 4 2011 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[C_CASTED]], align 4 2012 // CHECK4-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 4 2013 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32, i32, i32, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP9]], [4 x i32]* [[TMP10]]) 2014 // CHECK4-NEXT: ret void 2015 // 2016 // 2017 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 2018 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR2]] { 2019 // CHECK4-NEXT: entry: 2020 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2021 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2022 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 2023 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2024 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2025 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 2026 // CHECK4-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 4 2027 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 4 2028 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 2029 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca [4 x i32]*, align 4 2030 // CHECK4-NEXT: [[E3:%.*]] = alloca [4 x i32], align 4 2031 // CHECK4-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 4 2032 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, align 4 2033 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2034 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2035 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 2036 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2037 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2038 // CHECK4-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 2039 // CHECK4-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 4 2040 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 2041 // CHECK4-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 4 2042 // CHECK4-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4 2043 // CHECK4-NEXT: store i32* [[C_ADDR]], i32** [[_TMP1]], align 4 2044 // CHECK4-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP2]], align 4 2045 // CHECK4-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP2]], align 4 2046 // CHECK4-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E3]] to i8* 2047 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* 2048 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i32 16, i1 false) 2049 // CHECK4-NEXT: store [4 x i32]* [[E3]], [4 x i32]** [[_TMP4]], align 4 2050 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 0 2051 // CHECK4-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 4 2052 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 1 2053 // CHECK4-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 4 2054 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 2 2055 // CHECK4-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 2056 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 3 2057 // CHECK4-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 4 2058 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 4 2059 // CHECK4-NEXT: store %struct.__block_descriptor* bitcast ({ i32, i32, i8*, i8* }* @__block_descriptor_tmp.4 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 4 2060 // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 5 2061 // CHECK4-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 4 2062 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 6 2063 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 4 2064 // CHECK4-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 4 2065 // CHECK4-NEXT: [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 7 2066 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_ADDR]], align 4 2067 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED5]], align 4 2068 // CHECK4-NEXT: [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 8 2069 // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP1]], align 4 2070 // CHECK4-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED6]], align 4 2071 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]] to void ()* 2072 // CHECK4-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic* 2073 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 2074 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 2075 // CHECK4-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 4 2076 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)* 2077 // CHECK4-NEXT: call void [[TMP12]](i8* [[TMP10]]) 2078 // CHECK4-NEXT: ret void 2079 // 2080 // 2081 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke_2 2082 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 2083 // CHECK4-NEXT: entry: 2084 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 4 2085 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>*, align 4 2086 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2087 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2088 // CHECK4-NEXT: [[C_CASTED:%.*]] = alloca i32, align 4 2089 // CHECK4-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 4 2090 // CHECK4-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* 2091 // CHECK4-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>** [[BLOCK_ADDR]], align 4 2092 // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 5 2093 // CHECK4-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 4 2094 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 6 2095 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 4 2096 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2097 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 2098 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 2099 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 7 2100 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 4 2101 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 2102 // CHECK4-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 4 2103 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 8 2104 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 4 2105 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 2106 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 2107 // CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 2108 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 6 2109 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 4 2110 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 2111 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[A_CASTED]], align 4 2112 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A_CASTED]], align 4 2113 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 7 2114 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 4 2115 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[B_CASTED]], align 4 2116 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[B_CASTED]], align 4 2117 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32, i32* }>* [[BLOCK]], i32 0, i32 8 2118 // CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR5]], align 4 2119 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 2120 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[C_CASTED]], align 4 2121 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[C_CASTED]], align 4 2122 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SS* [[THIS]], i32 [[TMP7]], i32 [[TMP9]], i32 [[TMP12]]) 2123 // CHECK4-NEXT: ret void 2124 // 2125 // 2126 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 2127 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR2]] { 2128 // CHECK4-NEXT: entry: 2129 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2130 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2131 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 4 2132 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2133 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2134 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4 2135 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32*, align 4 2136 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32*, align 4 2137 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2138 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2139 // CHECK4-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 4 2140 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2141 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2142 // CHECK4-NEXT: store i32 [[C]], i32* [[C_ADDR]], align 4 2143 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 4 2144 // CHECK4-NEXT: store i32* [[A_ADDR]], i32** [[TMP]], align 4 2145 // CHECK4-NEXT: store i32* [[C_ADDR]], i32** [[_TMP1]], align 4 2146 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 4 2147 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2148 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 2149 // CHECK4-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 2150 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 2151 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 2152 // CHECK4-NEXT: store i32 [[DEC]], i32* [[B_ADDR]], align 4 2153 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP1]], align 4 2154 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2155 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 2156 // CHECK4-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 2157 // CHECK4-NEXT: ret void 2158 // 2159 // 2160 // CHECK9-LABEL: define {{[^@]+}}@main 2161 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 2162 // CHECK9-NEXT: entry: 2163 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2164 // CHECK9-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 2165 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2166 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2167 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2168 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2169 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 2170 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 2171 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 2172 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 2173 // CHECK9-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 2174 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 2175 // CHECK9-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 2176 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 2177 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 2178 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2179 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 2180 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 2181 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 2182 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 2183 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 2184 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 2185 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 2186 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 2187 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 2188 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 2189 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 2190 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 2191 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 2192 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 2193 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) 2194 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 2195 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 2196 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* 2197 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 2198 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 2199 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP6]]) 2200 // CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 2201 // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2202 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] 2203 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2204 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 2205 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2206 // CHECK9: arraydestroy.body: 2207 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2208 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2209 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2210 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2211 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 2212 // CHECK9: arraydestroy.done4: 2213 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2214 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 2215 // CHECK9-NEXT: ret i32 [[TMP8]] 2216 // 2217 // 2218 // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 2219 // CHECK9-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2220 // CHECK9-NEXT: entry: 2221 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 2222 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 2223 // CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 2224 // CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 2225 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 2226 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 2227 // CHECK9-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 2228 // CHECK9-NEXT: ret void 2229 // 2230 // 2231 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2232 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2233 // CHECK9-NEXT: entry: 2234 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2235 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2236 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2237 // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2238 // CHECK9-NEXT: ret void 2239 // 2240 // 2241 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2242 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2243 // CHECK9-NEXT: entry: 2244 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2245 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2246 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2247 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2248 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2249 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2250 // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2251 // CHECK9-NEXT: ret void 2252 // 2253 // 2254 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 2255 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 2256 // CHECK9-NEXT: entry: 2257 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2258 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2259 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 2260 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 2261 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 2262 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 2263 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2264 // CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2265 // CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 2266 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2267 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2268 // CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 2269 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2270 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2271 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 2272 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 2273 // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 2274 // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 2275 // CHECK9-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 2276 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 2277 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 2278 // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 2279 // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 2280 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 2281 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 2282 // CHECK9-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2283 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 2284 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 2285 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 2286 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 2287 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 2288 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2289 // CHECK9: omp.arraycpy.body: 2290 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2291 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2292 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2293 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2294 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 2295 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2296 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2297 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2298 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2299 // CHECK9: omp.arraycpy.done4: 2300 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 2301 // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 2302 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 2303 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 2304 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 2305 // CHECK9-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 2306 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 2307 // CHECK9-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 2308 // CHECK9-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 2309 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) 2310 // CHECK9-NEXT: store i32 2, i32* [[CONV1]], align 8 2311 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 2312 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 2313 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 2314 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2315 // CHECK9: arraydestroy.body: 2316 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2317 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2318 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2319 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 2320 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 2321 // CHECK9: arraydestroy.done9: 2322 // CHECK9-NEXT: ret void 2323 // 2324 // 2325 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC1Ev 2326 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2327 // CHECK9-NEXT: entry: 2328 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 2329 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 2330 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 2331 // CHECK9-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 2332 // CHECK9-NEXT: ret void 2333 // 2334 // 2335 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 2336 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2337 // CHECK9-NEXT: entry: 2338 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2339 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 2340 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2341 // CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 2342 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2343 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 2344 // CHECK9-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2345 // CHECK9-NEXT: ret void 2346 // 2347 // 2348 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev 2349 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2350 // CHECK9-NEXT: entry: 2351 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 2352 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 2353 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 2354 // CHECK9-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 2355 // CHECK9-NEXT: ret void 2356 // 2357 // 2358 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 2359 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2360 // CHECK9-NEXT: entry: 2361 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2362 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2363 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2364 // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2365 // CHECK9-NEXT: ret void 2366 // 2367 // 2368 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 2369 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { 2370 // CHECK9-NEXT: entry: 2371 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2372 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2373 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 2374 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2375 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2376 // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 2377 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 2378 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2379 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2380 // CHECK9-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*)) 2381 // CHECK9-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32* 2382 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 2383 // CHECK9-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4 2384 // CHECK9-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4 2385 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8* 2386 // CHECK9-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i64 1 to i8*)) 2387 // CHECK9-NEXT: ret void 2388 // 2389 // 2390 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 2391 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { 2392 // CHECK9-NEXT: entry: 2393 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2394 // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 2395 // CHECK9-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 2396 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 2397 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 2398 // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 2399 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 2400 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 2401 // CHECK9-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) 2402 // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 128 2403 // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2404 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 2405 // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 2406 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 2407 // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 2408 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 2409 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 2410 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) 2411 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[T_VAR]]) 2412 // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 2413 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 2414 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 2415 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 2416 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2417 // CHECK9: arraydestroy.body: 2418 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2419 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2420 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2421 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2422 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 2423 // CHECK9: arraydestroy.done1: 2424 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2425 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 2426 // CHECK9-NEXT: ret i32 [[TMP2]] 2427 // 2428 // 2429 // CHECK9-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 2430 // CHECK9-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2431 // CHECK9-NEXT: entry: 2432 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 2433 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 2434 // CHECK9-NEXT: [[A2:%.*]] = alloca i32*, align 8 2435 // CHECK9-NEXT: [[B4:%.*]] = alloca i32, align 4 2436 // CHECK9-NEXT: [[C7:%.*]] = alloca i32*, align 8 2437 // CHECK9-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 2438 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2439 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2440 // CHECK9-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 2441 // CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 2442 // CHECK9-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 2443 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 2444 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 2445 // CHECK9-NEXT: store i32 0, i32* [[A]], align 8 2446 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 2447 // CHECK9-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 2448 // CHECK9-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 2449 // CHECK9-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 2450 // CHECK9-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 2451 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 2452 // CHECK9-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 2453 // CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 2454 // CHECK9-NEXT: store i32* [[A3]], i32** [[A2]], align 8 2455 // CHECK9-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 2456 // CHECK9-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 2457 // CHECK9-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 2458 // CHECK9-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 2459 // CHECK9-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 2460 // CHECK9-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 2461 // CHECK9-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 2462 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 2463 // CHECK9-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 2464 // CHECK9-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 2465 // CHECK9-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 2466 // CHECK9-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 2467 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2468 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2469 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 2470 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 2471 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 2472 // CHECK9-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2473 // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4 2474 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 2475 // CHECK9-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8 2476 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 2477 // CHECK9-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32* 2478 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4 2479 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 2480 // CHECK9-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 2481 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]]) 2482 // CHECK9-NEXT: ret void 2483 // 2484 // 2485 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 2486 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] { 2487 // CHECK9-NEXT: entry: 2488 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2489 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2490 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 2491 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2492 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2493 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 2494 // CHECK9-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8 2495 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 2496 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 2497 // CHECK9-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8 2498 // CHECK9-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16 2499 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8 2500 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2501 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2502 // CHECK9-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 2503 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2504 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2505 // CHECK9-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 2506 // CHECK9-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8 2507 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 2508 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2509 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2510 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* 2511 // CHECK9-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8 2512 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 2513 // CHECK9-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 2514 // CHECK9-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8 2515 // CHECK9-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8 2516 // CHECK9-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* 2517 // CHECK9-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* 2518 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) 2519 // CHECK9-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 2520 // CHECK9-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 2521 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 2522 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 2523 // CHECK9-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 2524 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8 2525 // CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 2526 // CHECK9-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 2527 // CHECK9-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8 2528 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 2529 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 2530 // CHECK9-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 2531 // CHECK9-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP6]], align 8 2532 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2 2533 // CHECK9-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 2534 // CHECK9-NEXT: ret void 2535 // 2536 // 2537 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 2538 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2539 // CHECK9-NEXT: entry: 2540 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2541 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2542 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2543 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2544 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 2545 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 2546 // CHECK9-NEXT: store float [[CONV]], float* [[F]], align 4 2547 // CHECK9-NEXT: ret void 2548 // 2549 // 2550 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 2551 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2552 // CHECK9-NEXT: entry: 2553 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2554 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2555 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2556 // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2557 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2558 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2559 // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2560 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 2561 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 2562 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 2563 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 2564 // CHECK9-NEXT: ret void 2565 // 2566 // 2567 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StC2Ev 2568 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2569 // CHECK9-NEXT: entry: 2570 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 2571 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 2572 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 2573 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 2574 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 2575 // CHECK9-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 2576 // CHECK9-NEXT: store i32 0, i32* [[B]], align 4 2577 // CHECK9-NEXT: ret void 2578 // 2579 // 2580 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 2581 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2582 // CHECK9-NEXT: entry: 2583 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2584 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 2585 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2586 // CHECK9-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 2587 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2588 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 2589 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 2590 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 2591 // CHECK9-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 2592 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2593 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2594 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 2595 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 2596 // CHECK9-NEXT: store float [[ADD]], float* [[F]], align 4 2597 // CHECK9-NEXT: ret void 2598 // 2599 // 2600 // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev 2601 // CHECK9-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2602 // CHECK9-NEXT: entry: 2603 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 2604 // CHECK9-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 2605 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 2606 // CHECK9-NEXT: ret void 2607 // 2608 // 2609 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 2610 // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2611 // CHECK9-NEXT: entry: 2612 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2613 // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2614 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2615 // CHECK9-NEXT: ret void 2616 // 2617 // 2618 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 2619 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2620 // CHECK9-NEXT: entry: 2621 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2622 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2623 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2624 // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 2625 // CHECK9-NEXT: ret void 2626 // 2627 // 2628 // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 2629 // CHECK9-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2630 // CHECK9-NEXT: entry: 2631 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 2632 // CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 2633 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 2634 // CHECK9-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) 2635 // CHECK9-NEXT: ret void 2636 // 2637 // 2638 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 2639 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2640 // CHECK9-NEXT: entry: 2641 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2642 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2643 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2644 // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2645 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2646 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2647 // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 2648 // CHECK9-NEXT: ret void 2649 // 2650 // 2651 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 2652 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 2653 // CHECK9-NEXT: entry: 2654 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2655 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2656 // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 2657 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 2658 // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 2659 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 2660 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 2661 // CHECK9-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 2662 // CHECK9-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 2663 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2664 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 2665 // CHECK9-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 2666 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2667 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2668 // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 2669 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 2670 // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 2671 // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 2672 // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 2673 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 2674 // CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 2675 // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 2676 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 2677 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 2678 // CHECK9-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 2679 // CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2680 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) 2681 // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2682 // CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 2683 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 2684 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 2685 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2686 // CHECK9: omp.arraycpy.body: 2687 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2688 // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2689 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2690 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2691 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 2692 // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2693 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2694 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 2695 // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2696 // CHECK9: omp.arraycpy.done4: 2697 // CHECK9-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 2698 // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 2699 // CHECK9-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 2700 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 2701 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 2702 // CHECK9-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 2703 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 2704 // CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 2705 // CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 2706 // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) 2707 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 2708 // CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 2709 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 2710 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2711 // CHECK9: arraydestroy.body: 2712 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2713 // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2714 // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2715 // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 2716 // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 2717 // CHECK9: arraydestroy.done9: 2718 // CHECK9-NEXT: ret void 2719 // 2720 // 2721 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 2722 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2723 // CHECK9-NEXT: entry: 2724 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2725 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 2726 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2727 // CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 2728 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2729 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 2730 // CHECK9-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 2731 // CHECK9-NEXT: ret void 2732 // 2733 // 2734 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 2735 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2736 // CHECK9-NEXT: entry: 2737 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2738 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2739 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2740 // CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 2741 // CHECK9-NEXT: ret void 2742 // 2743 // 2744 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 2745 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 2746 // CHECK9-NEXT: entry: 2747 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2748 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2749 // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 2750 // CHECK9-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 2751 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2752 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2753 // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 2754 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 2755 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 2756 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 2757 // CHECK9-NEXT: ret void 2758 // 2759 // 2760 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 2761 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2762 // CHECK9-NEXT: entry: 2763 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2764 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2765 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2766 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2767 // CHECK9-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 2768 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 2769 // CHECK9-NEXT: ret void 2770 // 2771 // 2772 // CHECK9-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 2773 // CHECK9-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2774 // CHECK9-NEXT: entry: 2775 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 2776 // CHECK9-NEXT: [[A2:%.*]] = alloca i32*, align 8 2777 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2778 // CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 2779 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 2780 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 2781 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 2782 // CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 2783 // CHECK9-NEXT: store i32* [[A3]], i32** [[A2]], align 8 2784 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 2785 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2786 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2787 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 2788 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 2789 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.SST* [[THIS1]], i64 [[TMP2]]) 2790 // CHECK9-NEXT: ret void 2791 // 2792 // 2793 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 2794 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { 2795 // CHECK9-NEXT: entry: 2796 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2797 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2798 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 2799 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2800 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32*, align 8 2801 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2802 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2803 // CHECK9-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 2804 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2805 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 2806 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2807 // CHECK9-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 2808 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 2809 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2810 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 2811 // CHECK9-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 2812 // CHECK9-NEXT: ret void 2813 // 2814 // 2815 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 2816 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2817 // CHECK9-NEXT: entry: 2818 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2819 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2820 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2821 // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2822 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2823 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2824 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2825 // CHECK9-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 2826 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 2827 // CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2828 // CHECK9-NEXT: ret void 2829 // 2830 // 2831 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 2832 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2833 // CHECK9-NEXT: entry: 2834 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2835 // CHECK9-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 2836 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2837 // CHECK9-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 2838 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2839 // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 2840 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 2841 // CHECK9-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 2842 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 2843 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 2844 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2845 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 2846 // CHECK9-NEXT: store i32 [[ADD]], i32* [[F]], align 4 2847 // CHECK9-NEXT: ret void 2848 // 2849 // 2850 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 2851 // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2852 // CHECK9-NEXT: entry: 2853 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 2854 // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 2855 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 2856 // CHECK9-NEXT: ret void 2857 // 2858 // 2859 // CHECK10-LABEL: define {{[^@]+}}@main 2860 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 2861 // CHECK10-NEXT: entry: 2862 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 2863 // CHECK10-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 2864 // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2865 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 2866 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 2867 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 2868 // CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 2869 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 2870 // CHECK10-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 2871 // CHECK10-NEXT: [[A:%.*]] = alloca i32, align 4 2872 // CHECK10-NEXT: [[T_VAR_CASTED2:%.*]] = alloca i64, align 8 2873 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 2874 // CHECK10-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 2875 // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) 2876 // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 2877 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 2878 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) 2879 // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 2880 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) 2881 // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 2882 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) 2883 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]], float 3.000000e+00) 2884 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[T_VAR]], align 4 2885 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* 2886 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 2887 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 2888 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 2889 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 2890 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV1]], align 4 2891 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 2892 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i64, [2 x %struct.S]*, %struct.S*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i64 [[TMP2]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[VAR]], i64 [[TMP4]]) 2893 // CHECK10-NEXT: store i32 0, i32* [[A]], align 4 2894 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4 2895 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[T_VAR_CASTED2]] to i32* 2896 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV3]], align 4 2897 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[T_VAR_CASTED2]], align 8 2898 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP6]]) 2899 // CHECK10-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() 2900 // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 2901 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] 2902 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 2903 // CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 2904 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 2905 // CHECK10: arraydestroy.body: 2906 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 2907 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 2908 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 2909 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 2910 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] 2911 // CHECK10: arraydestroy.done4: 2912 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 2913 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4 2914 // CHECK10-NEXT: ret i32 [[TMP8]] 2915 // 2916 // 2917 // CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 2918 // CHECK10-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 2919 // CHECK10-NEXT: entry: 2920 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 2921 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 2922 // CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 2923 // CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 2924 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 2925 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 2926 // CHECK10-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 2927 // CHECK10-NEXT: ret void 2928 // 2929 // 2930 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 2931 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2932 // CHECK10-NEXT: entry: 2933 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2934 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2935 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2936 // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) 2937 // CHECK10-NEXT: ret void 2938 // 2939 // 2940 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 2941 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 2942 // CHECK10-NEXT: entry: 2943 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 2944 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 2945 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 2946 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 2947 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 2948 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 2949 // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) 2950 // CHECK10-NEXT: ret void 2951 // 2952 // 2953 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 2954 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 [[T_VAR:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3:[0-9]+]] { 2955 // CHECK10-NEXT: entry: 2956 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2957 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2958 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 2959 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 2960 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 2961 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 2962 // CHECK10-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 2963 // CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 2964 // CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 2965 // CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 2966 // CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 2967 // CHECK10-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 2968 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2969 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2970 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 2971 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 2972 // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 2973 // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 2974 // CHECK10-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 2975 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 2976 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 2977 // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 2978 // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 2979 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 2980 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 2981 // CHECK10-NEXT: [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 2982 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 8, i1 false) 2983 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 2984 // CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x %struct.S]* [[TMP1]] to %struct.S* 2985 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 2986 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP6]] 2987 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 2988 // CHECK10: omp.arraycpy.body: 2989 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2990 // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 2991 // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 2992 // CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 2993 // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 2994 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 2995 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 2996 // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] 2997 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 2998 // CHECK10: omp.arraycpy.done4: 2999 // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3000 // CHECK10-NEXT: call void @_ZN1SIfEC1ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], %struct.St* [[AGG_TMP6]]) 3001 // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 3002 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV]], align 8 3003 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 3004 // CHECK10-NEXT: store i32 [[TMP7]], i32* [[ARRAYIDX]], align 4 3005 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i64 0, i64 0 3006 // CHECK10-NEXT: [[TMP8:%.*]] = bitcast %struct.S* [[ARRAYIDX7]] to i8* 3007 // CHECK10-NEXT: [[TMP9:%.*]] = bitcast %struct.S* [[VAR5]] to i8* 3008 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 4, i1 false) 3009 // CHECK10-NEXT: store i32 2, i32* [[CONV1]], align 8 3010 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 3011 // CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR3]], i32 0, i32 0 3012 // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN8]], i64 2 3013 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3014 // CHECK10: arraydestroy.body: 3015 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP10]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3016 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3017 // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 3018 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 3019 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 3020 // CHECK10: arraydestroy.done9: 3021 // CHECK10-NEXT: ret void 3022 // 3023 // 3024 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StC1Ev 3025 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3026 // CHECK10-NEXT: entry: 3027 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 3028 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 3029 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 3030 // CHECK10-NEXT: call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) 3031 // CHECK10-NEXT: ret void 3032 // 3033 // 3034 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St 3035 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3036 // CHECK10-NEXT: entry: 3037 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3038 // CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 3039 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3040 // CHECK10-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 3041 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3042 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 3043 // CHECK10-NEXT: call void @_ZN1SIfEC2ERKS0_2St(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 3044 // CHECK10-NEXT: ret void 3045 // 3046 // 3047 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StD1Ev 3048 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3049 // CHECK10-NEXT: entry: 3050 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 3051 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 3052 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 3053 // CHECK10-NEXT: call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] 3054 // CHECK10-NEXT: ret void 3055 // 3056 // 3057 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 3058 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3059 // CHECK10-NEXT: entry: 3060 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3061 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3062 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3063 // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 3064 // CHECK10-NEXT: ret void 3065 // 3066 // 3067 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 3068 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[T_VAR:%.*]]) #[[ATTR3]] { 3069 // CHECK10-NEXT: entry: 3070 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3071 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3072 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 3073 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3074 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3075 // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 3076 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* 3077 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3078 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3079 // CHECK10-NEXT: [[DOTT_VAR__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP1]], i64 4, i8* inttoptr (i64 1 to i8*)) 3080 // CHECK10-NEXT: [[DOTT_VAR__ADDR:%.*]] = bitcast i8* [[DOTT_VAR__VOID_ADDR]] to i32* 3081 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 3082 // CHECK10-NEXT: store i32 [[TMP2]], i32* [[DOTT_VAR__ADDR]], align 4 3083 // CHECK10-NEXT: store i32 0, i32* [[DOTT_VAR__ADDR]], align 4 3084 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTT_VAR__ADDR]] to i8* 3085 // CHECK10-NEXT: call void @__kmpc_free(i32 [[TMP1]], i8* [[TMP3]], i8* inttoptr (i64 1 to i8*)) 3086 // CHECK10-NEXT: ret void 3087 // 3088 // 3089 // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 3090 // CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { 3091 // CHECK10-NEXT: entry: 3092 // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3093 // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 3094 // CHECK10-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 3095 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 3096 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 3097 // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 3098 // CHECK10-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 3099 // CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) 3100 // CHECK10-NEXT: call void @_ZN3SSTIiEC1Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[SST]]) 3101 // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 128 3102 // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* 3103 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP0]], i8* align 128 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) 3104 // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 3105 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) 3106 // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 3107 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) 3108 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]], i32 3) 3109 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, i32*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), [2 x i32]* [[VEC]], i32* [[T_VAR]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[VAR]]) 3110 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* [[T_VAR]]) 3111 // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 3112 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 3113 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 3114 // CHECK10-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 3115 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3116 // CHECK10: arraydestroy.body: 3117 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3118 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3119 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 3120 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 3121 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 3122 // CHECK10: arraydestroy.done1: 3123 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 3124 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[RETVAL]], align 4 3125 // CHECK10-NEXT: ret i32 [[TMP2]] 3126 // 3127 // 3128 // CHECK10-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 3129 // CHECK10-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3130 // CHECK10-NEXT: entry: 3131 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3132 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 3133 // CHECK10-NEXT: [[A2:%.*]] = alloca i32*, align 8 3134 // CHECK10-NEXT: [[B4:%.*]] = alloca i32, align 4 3135 // CHECK10-NEXT: [[C7:%.*]] = alloca i32*, align 8 3136 // CHECK10-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 3137 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3138 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3139 // CHECK10-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 3140 // CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3141 // CHECK10-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 3142 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3143 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 3144 // CHECK10-NEXT: store i32 0, i32* [[A]], align 8 3145 // CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3146 // CHECK10-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 3147 // CHECK10-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 3148 // CHECK10-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 3149 // CHECK10-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 3150 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 3151 // CHECK10-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 3152 // CHECK10-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 3153 // CHECK10-NEXT: store i32* [[A3]], i32** [[A2]], align 8 3154 // CHECK10-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3155 // CHECK10-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 3156 // CHECK10-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 3157 // CHECK10-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 3158 // CHECK10-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 3159 // CHECK10-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 3160 // CHECK10-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 3161 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 3162 // CHECK10-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 3163 // CHECK10-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 3164 // CHECK10-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 3165 // CHECK10-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 3166 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 3167 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3168 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 3169 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 3170 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 3171 // CHECK10-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3172 // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4 3173 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 3174 // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8 3175 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 3176 // CHECK10-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32* 3177 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4 3178 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 3179 // CHECK10-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 3180 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]]) 3181 // CHECK10-NEXT: ret void 3182 // 3183 // 3184 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 3185 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3]] { 3186 // CHECK10-NEXT: entry: 3187 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3188 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3189 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3190 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3191 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3192 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 3193 // CHECK10-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8 3194 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 3195 // CHECK10-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 3196 // CHECK10-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8 3197 // CHECK10-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16 3198 // CHECK10-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8 3199 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3200 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3201 // CHECK10-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3202 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3203 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3204 // CHECK10-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 3205 // CHECK10-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8 3206 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3207 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3208 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3209 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* 3210 // CHECK10-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8 3211 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 3212 // CHECK10-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 3213 // CHECK10-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8 3214 // CHECK10-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8 3215 // CHECK10-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* 3216 // CHECK10-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* 3217 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) 3218 // CHECK10-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 3219 // CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 3220 // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 3221 // CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1 3222 // CHECK10-NEXT: store i32 [[INC]], i32* [[TMP5]], align 4 3223 // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[CONV1]], align 8 3224 // CHECK10-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 3225 // CHECK10-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 3226 // CHECK10-NEXT: [[TMP8:%.*]] = load i32*, i32** [[_TMP3]], align 8 3227 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 3228 // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 1 3229 // CHECK10-NEXT: store i32 [[DIV]], i32* [[TMP8]], align 4 3230 // CHECK10-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP6]], align 8 3231 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], [4 x i32]* [[TMP10]], i64 0, i64 2 3232 // CHECK10-NEXT: store i32 1111, i32* [[ARRAYIDX]], align 4 3233 // CHECK10-NEXT: ret void 3234 // 3235 // 3236 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 3237 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3238 // CHECK10-NEXT: entry: 3239 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3240 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3241 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3242 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3243 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 3244 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP0]] to float 3245 // CHECK10-NEXT: store float [[CONV]], float* [[F]], align 4 3246 // CHECK10-NEXT: ret void 3247 // 3248 // 3249 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 3250 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3251 // CHECK10-NEXT: entry: 3252 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3253 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 3254 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3255 // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 3256 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3257 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3258 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 3259 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 3260 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to float 3261 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]] 3262 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 3263 // CHECK10-NEXT: ret void 3264 // 3265 // 3266 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StC2Ev 3267 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3268 // CHECK10-NEXT: entry: 3269 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 3270 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 3271 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 3272 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0 3273 // CHECK10-NEXT: store i32 0, i32* [[A]], align 4 3274 // CHECK10-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1 3275 // CHECK10-NEXT: store i32 0, i32* [[B]], align 4 3276 // CHECK10-NEXT: ret void 3277 // 3278 // 3279 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St 3280 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3281 // CHECK10-NEXT: entry: 3282 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3283 // CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S*, align 8 3284 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3285 // CHECK10-NEXT: store %struct.S* [[S]], %struct.S** [[S_ADDR]], align 8 3286 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3287 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 3288 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S*, %struct.S** [[S_ADDR]], align 8 3289 // CHECK10-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[TMP0]], i32 0, i32 0 3290 // CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[F2]], align 4 3291 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 3292 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3293 // CHECK10-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to float 3294 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]] 3295 // CHECK10-NEXT: store float [[ADD]], float* [[F]], align 4 3296 // CHECK10-NEXT: ret void 3297 // 3298 // 3299 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StD2Ev 3300 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3301 // CHECK10-NEXT: entry: 3302 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 3303 // CHECK10-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 3304 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 3305 // CHECK10-NEXT: ret void 3306 // 3307 // 3308 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 3309 // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3310 // CHECK10-NEXT: entry: 3311 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 3312 // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 3313 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 3314 // CHECK10-NEXT: ret void 3315 // 3316 // 3317 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 3318 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3319 // CHECK10-NEXT: entry: 3320 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3321 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3322 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3323 // CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) 3324 // CHECK10-NEXT: ret void 3325 // 3326 // 3327 // CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC1Ev 3328 // CHECK10-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3329 // CHECK10-NEXT: entry: 3330 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 3331 // CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 3332 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 3333 // CHECK10-NEXT: call void @_ZN3SSTIiEC2Ev(%struct.SST* nonnull align 4 dereferenceable(4) [[THIS1]]) 3334 // CHECK10-NEXT: ret void 3335 // 3336 // 3337 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 3338 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3339 // CHECK10-NEXT: entry: 3340 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3341 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3342 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3343 // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3344 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3345 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3346 // CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) 3347 // CHECK10-NEXT: ret void 3348 // 3349 // 3350 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 3351 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { 3352 // CHECK10-NEXT: entry: 3353 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3354 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3355 // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 3356 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 3357 // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 3358 // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 3359 // CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 3360 // CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 128 3361 // CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 128 3362 // CHECK10-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 3363 // CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 3364 // CHECK10-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 3365 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3366 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3367 // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 3368 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 3369 // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 3370 // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 3371 // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 3372 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 3373 // CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 3374 // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 3375 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 128 3376 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[T_VAR1]], align 128 3377 // CHECK10-NEXT: [[TMP5:%.*]] = bitcast [2 x i32]* [[VEC2]] to i8* 3378 // CHECK10-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8* 3379 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP5]], i8* align 128 [[TMP6]], i64 8, i1 false) 3380 // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3381 // CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* 3382 // CHECK10-NEXT: [[TMP8:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 3383 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP8]] 3384 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] 3385 // CHECK10: omp.arraycpy.body: 3386 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP7]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3387 // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] 3388 // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) 3389 // CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], %struct.St* [[AGG_TMP]]) 3390 // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] 3391 // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 3392 // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 3393 // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] 3394 // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] 3395 // CHECK10: omp.arraycpy.done4: 3396 // CHECK10-NEXT: call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) 3397 // CHECK10-NEXT: call void @_ZN1SIiEC1ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]], %struct.St* [[AGG_TMP6]]) 3398 // CHECK10-NEXT: call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR4]] 3399 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[T_VAR1]], align 128 3400 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC2]], i64 0, i64 0 3401 // CHECK10-NEXT: store i32 [[TMP9]], i32* [[ARRAYIDX]], align 128 3402 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i64 0, i64 0 3403 // CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[ARRAYIDX7]] to i8* 3404 // CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[VAR5]] to i8* 3405 // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP10]], i8* align 128 [[TMP11]], i64 4, i1 false) 3406 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] 3407 // CHECK10-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR3]], i32 0, i32 0 3408 // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN8]], i64 2 3409 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 3410 // CHECK10: arraydestroy.body: 3411 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP12]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 3412 // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 3413 // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 3414 // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] 3415 // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] 3416 // CHECK10: arraydestroy.done9: 3417 // CHECK10-NEXT: ret void 3418 // 3419 // 3420 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St 3421 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3422 // CHECK10-NEXT: entry: 3423 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3424 // CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 3425 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3426 // CHECK10-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 3427 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3428 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 3429 // CHECK10-NEXT: call void @_ZN1SIiEC2ERKS0_2St(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0]], %struct.St* [[T]]) 3430 // CHECK10-NEXT: ret void 3431 // 3432 // 3433 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 3434 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3435 // CHECK10-NEXT: entry: 3436 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3437 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3438 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3439 // CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 3440 // CHECK10-NEXT: ret void 3441 // 3442 // 3443 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 3444 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR3]] { 3445 // CHECK10-NEXT: entry: 3446 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3447 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3448 // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 3449 // CHECK10-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 3450 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3451 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3452 // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 3453 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 3454 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 128 3455 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[T_VAR1]], align 128 3456 // CHECK10-NEXT: ret void 3457 // 3458 // 3459 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 3460 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3461 // CHECK10-NEXT: entry: 3462 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3463 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3464 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3465 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3466 // CHECK10-NEXT: [[TMP0:%.*]] = load volatile i32, i32* @g, align 128 3467 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 3468 // CHECK10-NEXT: ret void 3469 // 3470 // 3471 // CHECK10-LABEL: define {{[^@]+}}@_ZN3SSTIiEC2Ev 3472 // CHECK10-SAME: (%struct.SST* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3473 // CHECK10-NEXT: entry: 3474 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 3475 // CHECK10-NEXT: [[A2:%.*]] = alloca i32*, align 8 3476 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3477 // CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 3478 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 3479 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SST:%.*]], %struct.SST* [[THIS1]], i32 0, i32 0 3480 // CHECK10-NEXT: store i32 0, i32* [[A]], align 4 3481 // CHECK10-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SST]], %struct.SST* [[THIS1]], i32 0, i32 0 3482 // CHECK10-NEXT: store i32* [[A3]], i32** [[A2]], align 8 3483 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[A2]], align 8 3484 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3485 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3486 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 3487 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 3488 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SST*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.SST* [[THIS1]], i64 [[TMP2]]) 3489 // CHECK10-NEXT: ret void 3490 // 3491 // 3492 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 3493 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SST* [[THIS:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { 3494 // CHECK10-NEXT: entry: 3495 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3496 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3497 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SST*, align 8 3498 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3499 // CHECK10-NEXT: [[TMP:%.*]] = alloca i32*, align 8 3500 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3501 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3502 // CHECK10-NEXT: store %struct.SST* [[THIS]], %struct.SST** [[THIS_ADDR]], align 8 3503 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3504 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.SST*, %struct.SST** [[THIS_ADDR]], align 8 3505 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3506 // CHECK10-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 3507 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 3508 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3509 // CHECK10-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 3510 // CHECK10-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 3511 // CHECK10-NEXT: ret void 3512 // 3513 // 3514 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 3515 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3516 // CHECK10-NEXT: entry: 3517 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3518 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3519 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3520 // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3521 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3522 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3523 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3524 // CHECK10-NEXT: [[TMP1:%.*]] = load volatile i32, i32* @g, align 128 3525 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]] 3526 // CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3527 // CHECK10-NEXT: ret void 3528 // 3529 // 3530 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St 3531 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[S:%.*]], %struct.St* [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3532 // CHECK10-NEXT: entry: 3533 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3534 // CHECK10-NEXT: [[S_ADDR:%.*]] = alloca %struct.S.0*, align 8 3535 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3536 // CHECK10-NEXT: store %struct.S.0* [[S]], %struct.S.0** [[S_ADDR]], align 8 3537 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3538 // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 3539 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S.0*, %struct.S.0** [[S_ADDR]], align 8 3540 // CHECK10-NEXT: [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[TMP0]], i32 0, i32 0 3541 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[F2]], align 4 3542 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[T]], i32 0, i32 0 3543 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3544 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]] 3545 // CHECK10-NEXT: store i32 [[ADD]], i32* [[F]], align 4 3546 // CHECK10-NEXT: ret void 3547 // 3548 // 3549 // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 3550 // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3551 // CHECK10-NEXT: entry: 3552 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 3553 // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 3554 // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 3555 // CHECK10-NEXT: ret void 3556 // 3557 // 3558 // CHECK11-LABEL: define {{[^@]+}}@main 3559 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 3560 // CHECK11-NEXT: entry: 3561 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3562 // CHECK11-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 3563 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 3564 // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 3565 // CHECK11-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 3566 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 3567 // CHECK11-NEXT: store i32* @_ZZ4mainE5sivar, i32** [[TMP0]], align 8 3568 // CHECK11-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(8) [[REF_TMP]]) 3569 // CHECK11-NEXT: ret i32 0 3570 // 3571 // 3572 // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 3573 // CHECK11-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3574 // CHECK11-NEXT: entry: 3575 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3576 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 3577 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3578 // CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 3579 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3580 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 3581 // CHECK11-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 3582 // CHECK11-NEXT: ret void 3583 // 3584 // 3585 // CHECK11-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 3586 // CHECK11-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3587 // CHECK11-NEXT: entry: 3588 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3589 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 3590 // CHECK11-NEXT: [[A2:%.*]] = alloca i32*, align 8 3591 // CHECK11-NEXT: [[B4:%.*]] = alloca i32, align 4 3592 // CHECK11-NEXT: [[C7:%.*]] = alloca i32*, align 8 3593 // CHECK11-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 3594 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3595 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3596 // CHECK11-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 3597 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3598 // CHECK11-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 3599 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3600 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 3601 // CHECK11-NEXT: store i32 0, i32* [[A]], align 8 3602 // CHECK11-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3603 // CHECK11-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 3604 // CHECK11-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 3605 // CHECK11-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 3606 // CHECK11-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 3607 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 3608 // CHECK11-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 3609 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 3610 // CHECK11-NEXT: store i32* [[A3]], i32** [[A2]], align 8 3611 // CHECK11-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3612 // CHECK11-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 3613 // CHECK11-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 3614 // CHECK11-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 3615 // CHECK11-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 3616 // CHECK11-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 3617 // CHECK11-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 3618 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 3619 // CHECK11-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 3620 // CHECK11-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 3621 // CHECK11-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 3622 // CHECK11-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 3623 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 3624 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3625 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 3626 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 3627 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 3628 // CHECK11-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3629 // CHECK11-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4 3630 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 3631 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8 3632 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 3633 // CHECK11-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32* 3634 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4 3635 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 3636 // CHECK11-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 3637 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]]) 3638 // CHECK11-NEXT: ret void 3639 // 3640 // 3641 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 3642 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR3:[0-9]+]] { 3643 // CHECK11-NEXT: entry: 3644 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3645 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3646 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3647 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3648 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3649 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 3650 // CHECK11-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8 3651 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 3652 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 3653 // CHECK11-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8 3654 // CHECK11-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16 3655 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8 3656 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 3657 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3658 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3659 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3660 // CHECK11-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3661 // CHECK11-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3662 // CHECK11-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 3663 // CHECK11-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8 3664 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3665 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3666 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3667 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* 3668 // CHECK11-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8 3669 // CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 3670 // CHECK11-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 3671 // CHECK11-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8 3672 // CHECK11-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8 3673 // CHECK11-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* 3674 // CHECK11-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* 3675 // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) 3676 // CHECK11-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 3677 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 3678 // CHECK11-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[TMP5]], align 8 3679 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 3680 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[TMP]], align 8 3681 // CHECK11-NEXT: store i32* [[TMP7]], i32** [[TMP6]], align 8 3682 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 3683 // CHECK11-NEXT: store i32* [[CONV1]], i32** [[TMP8]], align 8 3684 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 3685 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[_TMP3]], align 8 3686 // CHECK11-NEXT: store i32* [[TMP10]], i32** [[TMP9]], align 8 3687 // CHECK11-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) 3688 // CHECK11-NEXT: ret void 3689 // 3690 // 3691 // CHECK11-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv 3692 // CHECK11-SAME: (%class.anon.0* nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2:[0-9]+]] align 2 { 3693 // CHECK11-NEXT: entry: 3694 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %class.anon.0*, align 8 3695 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3696 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3697 // CHECK11-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 3698 // CHECK11-NEXT: store %class.anon.0* [[THIS]], %class.anon.0** [[THIS_ADDR]], align 8 3699 // CHECK11-NEXT: [[THIS1:%.*]] = load %class.anon.0*, %class.anon.0** [[THIS_ADDR]], align 8 3700 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON_0:%.*]], %class.anon.0* [[THIS1]], i32 0, i32 0 3701 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.SS*, %struct.SS** [[TMP0]], align 8 3702 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 3703 // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[TMP2]], align 8 3704 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 3705 // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 3706 // CHECK11-NEXT: store i32 [[INC]], i32* [[TMP3]], align 4 3707 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 3708 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[TMP5]], align 8 3709 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4 3710 // CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 3711 // CHECK11-NEXT: store i32 [[DEC]], i32* [[TMP6]], align 4 3712 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 3713 // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[TMP8]], align 8 3714 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3715 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 3716 // CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP9]], align 4 3717 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 1 3718 // CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[TMP11]], align 8 3719 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 3720 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3721 // CHECK11-NEXT: store i32 [[TMP13]], i32* [[CONV]], align 4 3722 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[A_CASTED]], align 8 3723 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 2 3724 // CHECK11-NEXT: [[TMP16:%.*]] = load i32*, i32** [[TMP15]], align 8 3725 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4 3726 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3727 // CHECK11-NEXT: store i32 [[TMP17]], i32* [[CONV2]], align 4 3728 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[B_CASTED]], align 8 3729 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[THIS1]], i32 0, i32 3 3730 // CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[TMP19]], align 8 3731 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 3732 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[C_CASTED]] to i32* 3733 // CHECK11-NEXT: store i32 [[TMP21]], i32* [[CONV3]], align 4 3734 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[C_CASTED]], align 8 3735 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.SS* [[TMP1]], i64 [[TMP14]], i64 [[TMP18]], i64 [[TMP22]]) 3736 // CHECK11-NEXT: ret void 3737 // 3738 // 3739 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 3740 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR3]] { 3741 // CHECK11-NEXT: entry: 3742 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3743 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3744 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3745 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3746 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3747 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 3748 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 3749 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 3750 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3751 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3752 // CHECK11-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3753 // CHECK11-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3754 // CHECK11-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3755 // CHECK11-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 3756 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3757 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3758 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3759 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* 3760 // CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 3761 // CHECK11-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 3762 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 3763 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3764 // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 3765 // CHECK11-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 3766 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 3767 // CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 3768 // CHECK11-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 3769 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8 3770 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3771 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 3772 // CHECK11-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 3773 // CHECK11-NEXT: ret void 3774 // 3775 // 3776 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 3777 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR3]] { 3778 // CHECK11-NEXT: entry: 3779 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3780 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3781 // CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 3782 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 3783 // CHECK11-NEXT: [[G1:%.*]] = alloca i32, align 128 3784 // CHECK11-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 3785 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3786 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3787 // CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 3788 // CHECK11-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 3789 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 3790 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 3791 // CHECK11-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128 3792 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 3793 // CHECK11-NEXT: store i32 1, i32* [[G1]], align 128 3794 // CHECK11-NEXT: store i32 2, i32* [[CONV]], align 8 3795 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 0 3796 // CHECK11-NEXT: store i32* [[G1]], i32** [[TMP2]], align 8 3797 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[CLASS_ANON_1]], %class.anon.1* [[REF_TMP]], i32 0, i32 1 3798 // CHECK11-NEXT: store i32* [[CONV]], i32** [[TMP3]], align 8 3799 // CHECK11-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.1* nonnull align 8 dereferenceable(16) [[REF_TMP]]) 3800 // CHECK11-NEXT: ret void 3801 // 3802 // 3803 // CHECK12-LABEL: define {{[^@]+}}@main 3804 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 3805 // CHECK12-NEXT: entry: 3806 // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 3807 // CHECK12-NEXT: [[SS:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 3808 // CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, align 8 3809 // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 3810 // CHECK12-NEXT: call void @_ZN2SSC1ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[SS]], i32* nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) 3811 // CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 0 3812 // CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 3813 // CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 1 3814 // CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 3815 // CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 2 3816 // CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 3817 // CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 3 3818 // CHECK12-NEXT: store i8* bitcast (void (i8*)* @__main_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 8 3819 // CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 4 3820 // CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.1 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 3821 // CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], i32 0, i32 5 3822 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 3823 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[BLOCK_CAPTURED]], align 8 3824 // CHECK12-NEXT: [[TMP1:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]] to void ()* 3825 // CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP1]] to %struct.__block_literal_generic* 3826 // CHECK12-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 3827 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 3828 // CHECK12-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 8 3829 // CHECK12-NEXT: [[TMP5:%.*]] = bitcast i8* [[TMP4]] to void (i8*)* 3830 // CHECK12-NEXT: call void [[TMP5]](i8* [[TMP3]]) 3831 // CHECK12-NEXT: ret i32 0 3832 // 3833 // 3834 // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC1ERi 3835 // CHECK12-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 3836 // CHECK12-NEXT: entry: 3837 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3838 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 3839 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3840 // CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 3841 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3842 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 3843 // CHECK12-NEXT: call void @_ZN2SSC2ERi(%struct.SS* nonnull align 8 dereferenceable(32) [[THIS1]], i32* nonnull align 4 dereferenceable(4) [[TMP0]]) 3844 // CHECK12-NEXT: ret void 3845 // 3846 // 3847 // CHECK12-LABEL: define {{[^@]+}}@__main_block_invoke 3848 // CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 3849 // CHECK12-NEXT: entry: 3850 // CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 3851 // CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>*, align 8 3852 // CHECK12-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 3853 // CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 3854 // CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* 3855 // CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32 }>** [[BLOCK_ADDR]], align 8 3856 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* @_ZZ4mainE5sivar, align 4 3857 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_CASTED]] to i32* 3858 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 3859 // CHECK12-NEXT: [[TMP1:%.*]] = load i64, i64* [[SIVAR_CASTED]], align 8 3860 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @g, i64 [[TMP1]]) 3861 // CHECK12-NEXT: ret void 3862 // 3863 // 3864 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 3865 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]], i64 [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] { 3866 // CHECK12-NEXT: entry: 3867 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3868 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3869 // CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 3870 // CHECK12-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 3871 // CHECK12-NEXT: [[G1:%.*]] = alloca i32, align 128 3872 // CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, align 128 3873 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3874 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3875 // CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 3876 // CHECK12-NEXT: store i64 [[SIVAR]], i64* [[SIVAR_ADDR]], align 8 3877 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8 3878 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[SIVAR_ADDR]] to i32* 3879 // CHECK12-NEXT: [[TMP1:%.*]] = load volatile i32, i32* [[TMP0]], align 128 3880 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[G1]], align 128 3881 // CHECK12-NEXT: store i32 1, i32* [[G1]], align 128 3882 // CHECK12-NEXT: store i32 2, i32* [[CONV]], align 8 3883 // CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 0 3884 // CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 128 3885 // CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 1 3886 // CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 3887 // CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 2 3888 // CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 3889 // CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 3 3890 // CHECK12-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke to i8*), i8** [[BLOCK_INVOKE]], align 16 3891 // CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 4 3892 // CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 3893 // CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 3894 // CHECK12-NEXT: [[TMP2:%.*]] = load volatile i32, i32* [[G1]], align 128 3895 // CHECK12-NEXT: store volatile i32 [[TMP2]], i32* [[BLOCK_CAPTURED]], align 128 3896 // CHECK12-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 3897 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 3898 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[BLOCK_CAPTURED2]], align 32 3899 // CHECK12-NEXT: [[TMP4:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]] to void ()* 3900 // CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP4]] to %struct.__block_literal_generic* 3901 // CHECK12-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 3902 // CHECK12-NEXT: [[TMP6:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 3903 // CHECK12-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP5]], align 8 3904 // CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to void (i8*)* 3905 // CHECK12-NEXT: call void [[TMP8]](i8* [[TMP6]]) 3906 // CHECK12-NEXT: ret void 3907 // 3908 // 3909 // CHECK12-LABEL: define {{[^@]+}}@g_block_invoke 3910 // CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 3911 // CHECK12-NEXT: entry: 3912 // CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 3913 // CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>*, align 8 3914 // CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 3915 // CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* 3916 // CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>** [[BLOCK_ADDR]], align 8 3917 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 7 3918 // CHECK12-NEXT: store i32 2, i32* [[BLOCK_CAPTURE_ADDR]], align 128 3919 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i32, [92 x i8], i32 }>* [[BLOCK]], i32 0, i32 5 3920 // CHECK12-NEXT: store i32 4, i32* [[BLOCK_CAPTURE_ADDR1]], align 32 3921 // CHECK12-NEXT: ret void 3922 // 3923 // 3924 // CHECK12-LABEL: define {{[^@]+}}@_ZN2SSC2ERi 3925 // CHECK12-SAME: (%struct.SS* nonnull align 8 dereferenceable(32) [[THIS:%.*]], i32* nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 3926 // CHECK12-NEXT: entry: 3927 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3928 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca i32*, align 8 3929 // CHECK12-NEXT: [[A2:%.*]] = alloca i32*, align 8 3930 // CHECK12-NEXT: [[B4:%.*]] = alloca i32, align 4 3931 // CHECK12-NEXT: [[C7:%.*]] = alloca i32*, align 8 3932 // CHECK12-NEXT: [[E:%.*]] = alloca [4 x i32]*, align 8 3933 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3934 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3935 // CHECK12-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 3936 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3937 // CHECK12-NEXT: store i32* [[D]], i32** [[D_ADDR]], align 8 3938 // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 3939 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], %struct.SS* [[THIS1]], i32 0, i32 0 3940 // CHECK12-NEXT: store i32 0, i32* [[A]], align 8 3941 // CHECK12-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3942 // CHECK12-NEXT: [[BF_LOAD:%.*]] = load i8, i8* [[B]], align 4 3943 // CHECK12-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16 3944 // CHECK12-NEXT: store i8 [[BF_CLEAR]], i8* [[B]], align 4 3945 // CHECK12-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 3946 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[D_ADDR]], align 8 3947 // CHECK12-NEXT: store i32* [[TMP0]], i32** [[C]], align 8 3948 // CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 0 3949 // CHECK12-NEXT: store i32* [[A3]], i32** [[A2]], align 8 3950 // CHECK12-NEXT: [[B5:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 1 3951 // CHECK12-NEXT: [[BF_LOAD6:%.*]] = load i8, i8* [[B5]], align 4 3952 // CHECK12-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4 3953 // CHECK12-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4 3954 // CHECK12-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 3955 // CHECK12-NEXT: store i32 [[BF_CAST]], i32* [[B4]], align 4 3956 // CHECK12-NEXT: [[C8:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 2 3957 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[C8]], align 8 3958 // CHECK12-NEXT: store i32* [[TMP1]], i32** [[C7]], align 8 3959 // CHECK12-NEXT: [[E9:%.*]] = getelementptr inbounds [[STRUCT_SS]], %struct.SS* [[THIS1]], i32 0, i32 3 3960 // CHECK12-NEXT: store [4 x i32]* [[E9]], [4 x i32]** [[E]], align 8 3961 // CHECK12-NEXT: [[TMP2:%.*]] = load i32*, i32** [[A2]], align 8 3962 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 3963 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3964 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 3965 // CHECK12-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 3966 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B4]], align 4 3967 // CHECK12-NEXT: [[CONV10:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3968 // CHECK12-NEXT: store i32 [[TMP5]], i32* [[CONV10]], align 4 3969 // CHECK12-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 3970 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[C7]], align 8 3971 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 3972 // CHECK12-NEXT: [[CONV11:%.*]] = bitcast i64* [[C_CASTED]] to i32* 3973 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[CONV11]], align 4 3974 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[C_CASTED]], align 8 3975 // CHECK12-NEXT: [[TMP10:%.*]] = load [4 x i32]*, [4 x i32]** [[E]], align 8 3976 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64, [4 x i32]*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.SS* [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]], [4 x i32]* [[TMP10]]) 3977 // CHECK12-NEXT: ret void 3978 // 3979 // 3980 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 3981 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]], [4 x i32]* nonnull align 4 dereferenceable(16) [[E:%.*]]) #[[ATTR2]] { 3982 // CHECK12-NEXT: entry: 3983 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3984 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3985 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 3986 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3987 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3988 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 3989 // CHECK12-NEXT: [[E_ADDR:%.*]] = alloca [4 x i32]*, align 8 3990 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 3991 // CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 3992 // CHECK12-NEXT: [[_TMP4:%.*]] = alloca [4 x i32]*, align 8 3993 // CHECK12-NEXT: [[E5:%.*]] = alloca [4 x i32], align 16 3994 // CHECK12-NEXT: [[_TMP6:%.*]] = alloca [4 x i32]*, align 8 3995 // CHECK12-NEXT: [[BLOCK:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, align 8 3996 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3997 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3998 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 3999 // CHECK12-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4000 // CHECK12-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4001 // CHECK12-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 4002 // CHECK12-NEXT: store [4 x i32]* [[E]], [4 x i32]** [[E_ADDR]], align 8 4003 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 4004 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4005 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4006 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* 4007 // CHECK12-NEXT: [[TMP1:%.*]] = load [4 x i32]*, [4 x i32]** [[E_ADDR]], align 8 4008 // CHECK12-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 4009 // CHECK12-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 4010 // CHECK12-NEXT: store [4 x i32]* [[TMP1]], [4 x i32]** [[_TMP4]], align 8 4011 // CHECK12-NEXT: [[TMP2:%.*]] = load [4 x i32]*, [4 x i32]** [[_TMP4]], align 8 4012 // CHECK12-NEXT: [[TMP3:%.*]] = bitcast [4 x i32]* [[E5]] to i8* 4013 // CHECK12-NEXT: [[TMP4:%.*]] = bitcast [4 x i32]* [[TMP2]] to i8* 4014 // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 4 [[TMP4]], i64 16, i1 false) 4015 // CHECK12-NEXT: store [4 x i32]* [[E5]], [4 x i32]** [[_TMP6]], align 8 4016 // CHECK12-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 0 4017 // CHECK12-NEXT: store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** [[BLOCK_ISA]], align 8 4018 // CHECK12-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 1 4019 // CHECK12-NEXT: store i32 1073741824, i32* [[BLOCK_FLAGS]], align 8 4020 // CHECK12-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 2 4021 // CHECK12-NEXT: store i32 0, i32* [[BLOCK_RESERVED]], align 4 4022 // CHECK12-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 3 4023 // CHECK12-NEXT: store i8* bitcast (void (i8*)* @g_block_invoke_2 to i8*), i8** [[BLOCK_INVOKE]], align 8 4024 // CHECK12-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 4 4025 // CHECK12-NEXT: store %struct.__block_descriptor* bitcast ({ i64, i64, i8*, i8* }* @__block_descriptor_tmp.4 to %struct.__block_descriptor*), %struct.__block_descriptor** [[BLOCK_DESCRIPTOR]], align 8 4026 // CHECK12-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 4027 // CHECK12-NEXT: store %struct.SS* [[TMP0]], %struct.SS** [[BLOCK_CAPTURED_THIS_ADDR]], align 8 4028 // CHECK12-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 4029 // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[TMP]], align 8 4030 // CHECK12-NEXT: store i32* [[TMP5]], i32** [[BLOCK_CAPTURED]], align 8 4031 // CHECK12-NEXT: [[BLOCK_CAPTURED7:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 4032 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV1]], align 8 4033 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[BLOCK_CAPTURED7]], align 8 4034 // CHECK12-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 4035 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[_TMP3]], align 8 4036 // CHECK12-NEXT: store i32* [[TMP7]], i32** [[BLOCK_CAPTURED8]], align 8 4037 // CHECK12-NEXT: [[TMP8:%.*]] = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]] to void ()* 4038 // CHECK12-NEXT: [[BLOCK_LITERAL:%.*]] = bitcast void ()* [[TMP8]] to %struct.__block_literal_generic* 4039 // CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* [[BLOCK_LITERAL]], i32 0, i32 3 4040 // CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.__block_literal_generic* [[BLOCK_LITERAL]] to i8* 4041 // CHECK12-NEXT: [[TMP11:%.*]] = load i8*, i8** [[TMP9]], align 8 4042 // CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP11]] to void (i8*)* 4043 // CHECK12-NEXT: call void [[TMP12]](i8* [[TMP10]]) 4044 // CHECK12-NEXT: ret void 4045 // 4046 // 4047 // CHECK12-LABEL: define {{[^@]+}}@g_block_invoke_2 4048 // CHECK12-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR1]] { 4049 // CHECK12-NEXT: entry: 4050 // CHECK12-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8 4051 // CHECK12-NEXT: [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>*, align 8 4052 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4053 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4054 // CHECK12-NEXT: [[C_CASTED:%.*]] = alloca i64, align 8 4055 // CHECK12-NEXT: store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 4056 // CHECK12-NEXT: [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* 4057 // CHECK12-NEXT: store <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>** [[BLOCK_ADDR]], align 8 4058 // CHECK12-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 5 4059 // CHECK12-NEXT: [[THIS:%.*]] = load %struct.SS*, %struct.SS** [[BLOCK_CAPTURED_THIS]], align 8 4060 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 4061 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR]], align 8 4062 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4063 // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 4064 // CHECK12-NEXT: store i32 [[INC]], i32* [[TMP0]], align 4 4065 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 4066 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR1]], align 8 4067 // CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 4068 // CHECK12-NEXT: store i32 [[DEC]], i32* [[BLOCK_CAPTURE_ADDR1]], align 8 4069 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 4070 // CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR2]], align 8 4071 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 4072 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 4073 // CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP3]], align 4 4074 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 6 4075 // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR3]], align 8 4076 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 4077 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4078 // CHECK12-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 4079 // CHECK12-NEXT: [[TMP7:%.*]] = load i64, i64* [[A_CASTED]], align 8 4080 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 8 4081 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[BLOCK_CAPTURE_ADDR4]], align 8 4082 // CHECK12-NEXT: [[CONV5:%.*]] = bitcast i64* [[B_CASTED]] to i32* 4083 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 4084 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[B_CASTED]], align 8 4085 // CHECK12-NEXT: [[BLOCK_CAPTURE_ADDR6:%.*]] = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>, <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, %struct.SS*, i32*, i32*, i32 }>* [[BLOCK]], i32 0, i32 7 4086 // CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[BLOCK_CAPTURE_ADDR6]], align 8 4087 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 4088 // CHECK12-NEXT: [[CONV7:%.*]] = bitcast i64* [[C_CASTED]] to i32* 4089 // CHECK12-NEXT: store i32 [[TMP11]], i32* [[CONV7]], align 4 4090 // CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[C_CASTED]], align 8 4091 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.SS*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.SS* [[THIS]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP12]]) 4092 // CHECK12-NEXT: ret void 4093 // 4094 // 4095 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 4096 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.SS* [[THIS:%.*]], i64 [[A:%.*]], i64 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR2]] { 4097 // CHECK12-NEXT: entry: 4098 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4099 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4100 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.SS*, align 8 4101 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4102 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4103 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8 4104 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 4105 // CHECK12-NEXT: [[_TMP3:%.*]] = alloca i32*, align 8 4106 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4107 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4108 // CHECK12-NEXT: store %struct.SS* [[THIS]], %struct.SS** [[THIS_ADDR]], align 8 4109 // CHECK12-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4110 // CHECK12-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4111 // CHECK12-NEXT: store i64 [[C]], i64* [[C_ADDR]], align 8 4112 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.SS*, %struct.SS** [[THIS_ADDR]], align 8 4113 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4114 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4115 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i64* [[C_ADDR]] to i32* 4116 // CHECK12-NEXT: store i32* [[CONV]], i32** [[TMP]], align 8 4117 // CHECK12-NEXT: store i32* [[CONV2]], i32** [[_TMP3]], align 8 4118 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[TMP]], align 8 4119 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 4120 // CHECK12-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 4121 // CHECK12-NEXT: store i32 [[INC]], i32* [[TMP1]], align 4 4122 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV1]], align 8 4123 // CHECK12-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 4124 // CHECK12-NEXT: store i32 [[DEC]], i32* [[CONV1]], align 8 4125 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[_TMP3]], align 8 4126 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4127 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 4128 // CHECK12-NEXT: store i32 [[DIV]], i32* [[TMP4]], align 4 4129 // CHECK12-NEXT: ret void 4130 // 4131 // 4132 // CHECK17-LABEL: define {{[^@]+}}@_Z10array_funcPfP2StiPe 4133 // CHECK17-SAME: (float* [[A:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0:[0-9]+]] { 4134 // CHECK17-NEXT: entry: 4135 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4136 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4137 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4138 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 4139 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4140 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4141 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 4142 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4143 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4144 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4145 // CHECK17-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 4146 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4147 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 4148 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4149 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 4150 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4151 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 4152 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 4153 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 4154 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 4155 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 4156 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 4157 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 4158 // CHECK17-NEXT: [[TMP8:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4159 // CHECK17-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 4160 // CHECK17-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 4161 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.St*, i32*, i64, x86_fp80*, float*, i64, i64, double*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.St* [[TMP8]], i32* [[N_ADDR]], i64 [[TMP1]], x86_fp80* [[TMP9]], float* [[TMP10]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]]) 4162 // CHECK17-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4163 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) 4164 // CHECK17-NEXT: ret void 4165 // 4166 // 4167 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 4168 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.St* [[S:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], i64 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], float* [[A:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]]) #[[ATTR2:[0-9]+]] { 4169 // CHECK17-NEXT: entry: 4170 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4171 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4172 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4173 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 4174 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4175 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 4176 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4177 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 4178 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 4179 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 4180 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4181 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4182 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 4183 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4184 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4185 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4186 // CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 4187 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4188 // CHECK17-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 4189 // CHECK17-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4190 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 4191 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 4192 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 4193 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[N_ADDR]], align 8 4194 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4195 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 4196 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 4197 // CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 4198 // CHECK17-NEXT: [[TMP5:%.*]] = call i8* @llvm.stacksave() 4199 // CHECK17-NEXT: store i8* [[TMP5]], i8** [[SAVED_STACK]], align 8 4200 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4201 // CHECK17-NEXT: [[VLA7:%.*]] = alloca double, i64 [[TMP6]], align 128 4202 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 4203 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR1]], align 8 4204 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4205 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 [[TMP7]], 8 4206 // CHECK17-NEXT: [[TMP9:%.*]] = bitcast double* [[VLA7]] to i8* 4207 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast double* [[TMP4]] to i8* 4208 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 [[TMP10]], i64 [[TMP8]], i1 false) 4209 // CHECK17-NEXT: [[TMP11:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4210 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP11]], i64 0 4211 // CHECK17-NEXT: [[TMP12:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4212 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP0]], align 4 4213 // CHECK17-NEXT: [[TMP14:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 4214 // CHECK17-NEXT: call void @_ZN2St7St_funcEPS_iPe(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYIDX]], %struct.St* [[TMP12]], i32 [[TMP13]], x86_fp80* [[TMP14]]) 4215 // CHECK17-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4216 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 4217 // CHECK17-NEXT: ret void 4218 // 4219 // 4220 // CHECK17-LABEL: define {{[^@]+}}@_ZN2St7St_funcEPS_iPe 4221 // CHECK17-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* [[S:%.*]], i32 [[N:%.*]], x86_fp80* [[VLA1:%.*]]) #[[ATTR0]] align 2 { 4222 // CHECK17-NEXT: entry: 4223 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 4224 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4225 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4226 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 4227 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4228 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4229 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 4230 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 4231 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4232 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4233 // CHECK17-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 4234 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 4235 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4236 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 4237 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4238 // CHECK17-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64 4239 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4240 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 4241 // CHECK17-NEXT: [[TMP6:%.*]] = call i8* @llvm.stacksave() 4242 // CHECK17-NEXT: store i8* [[TMP6]], i8** [[SAVED_STACK]], align 8 4243 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP3]], [[TMP5]] 4244 // CHECK17-NEXT: [[VLA:%.*]] = alloca double, i64 [[TMP7]], align 128 4245 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[__VLA_EXPR0]], align 8 4246 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 4247 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 1 4248 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4 4249 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 0 4250 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[A]], align 4 4251 // CHECK17-NEXT: [[TMP9:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 4252 // CHECK17-NEXT: [[TMP10:%.*]] = load %struct.St*, %struct.St** [[S_ADDR]], align 8 4253 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 8, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, x86_fp80*, %struct.St*, i64, i64, double*, i32*, %struct.St*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], x86_fp80* [[TMP9]], %struct.St* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]], double* [[VLA]], i32* [[N_ADDR]], %struct.St* [[TMP10]]) 4254 // CHECK17-NEXT: [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4255 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP11]]) 4256 // CHECK17-NEXT: ret void 4257 // 4258 // 4259 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 4260 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], x86_fp80* [[VLA1:%.*]], %struct.St* [[THIS:%.*]], i64 [[VLA2:%.*]], i64 [[VLA4:%.*]], double* nonnull align 8 dereferenceable(8) [[VLA26:%.*]], i32* nonnull align 4 dereferenceable(4) [[N:%.*]], %struct.St* [[S:%.*]]) #[[ATTR2]] { 4261 // CHECK17-NEXT: entry: 4262 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4263 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4264 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4265 // CHECK17-NEXT: [[VLA1_ADDR:%.*]] = alloca x86_fp80*, align 8 4266 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8 4267 // CHECK17-NEXT: [[VLA_ADDR3:%.*]] = alloca i64, align 8 4268 // CHECK17-NEXT: [[VLA_ADDR5:%.*]] = alloca i64, align 8 4269 // CHECK17-NEXT: [[VLA2_ADDR:%.*]] = alloca double*, align 8 4270 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32*, align 8 4271 // CHECK17-NEXT: [[S_ADDR:%.*]] = alloca %struct.St*, align 8 4272 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4273 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4274 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4275 // CHECK17-NEXT: store x86_fp80* [[VLA1]], x86_fp80** [[VLA1_ADDR]], align 8 4276 // CHECK17-NEXT: store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8 4277 // CHECK17-NEXT: store i64 [[VLA2]], i64* [[VLA_ADDR3]], align 8 4278 // CHECK17-NEXT: store i64 [[VLA4]], i64* [[VLA_ADDR5]], align 8 4279 // CHECK17-NEXT: store double* [[VLA26]], double** [[VLA2_ADDR]], align 8 4280 // CHECK17-NEXT: store i32* [[N]], i32** [[N_ADDR]], align 8 4281 // CHECK17-NEXT: store %struct.St* [[S]], %struct.St** [[S_ADDR]], align 8 4282 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4283 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8 4284 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR3]], align 8 4285 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR5]], align 8 4286 // CHECK17-NEXT: [[TMP4:%.*]] = load double*, double** [[VLA2_ADDR]], align 8 4287 // CHECK17-NEXT: [[TMP5:%.*]] = load i32*, i32** [[N_ADDR]], align 8 4288 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4289 // CHECK17-NEXT: [[TMP7:%.*]] = mul nuw i64 [[TMP6]], 8 4290 // CHECK17-NEXT: [[TMP8:%.*]] = add nuw i64 [[TMP7]], 127 4291 // CHECK17-NEXT: [[TMP9:%.*]] = udiv i64 [[TMP8]], 128 4292 // CHECK17-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP9]], 128 4293 // CHECK17-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4294 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 4295 // CHECK17-NEXT: [[DOTVLA2__VOID_ADDR:%.*]] = call i8* @__kmpc_alloc(i32 [[TMP12]], i64 [[TMP10]], i8* inttoptr (i64 8 to i8*)) 4296 // CHECK17-NEXT: [[DOTVLA2__ADDR:%.*]] = bitcast i8* [[DOTVLA2__VOID_ADDR]] to double* 4297 // CHECK17-NEXT: [[TMP13:%.*]] = mul nuw i64 [[TMP2]], [[TMP3]] 4298 // CHECK17-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8 4299 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast double* [[DOTVLA2__ADDR]] to i8* 4300 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast double* [[TMP4]] to i8* 4301 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP15]], i8* align 128 [[TMP16]], i64 [[TMP14]], i1 false) 4302 // CHECK17-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[TMP1]], i32 0, i32 1 4303 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4 4304 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 0 4305 // CHECK17-NEXT: store i32 [[TMP17]], i32* [[A]], align 4 4306 // CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP17]] to double 4307 // CHECK17-NEXT: [[TMP18:%.*]] = mul nsw i64 1, [[TMP3]] 4308 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[DOTVLA2__ADDR]], i64 [[TMP18]] 4309 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP5]], align 4 4310 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP19]], 1 4311 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[SUB]] to i64 4312 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX]], i64 [[IDXPROM]] 4313 // CHECK17-NEXT: store double [[CONV]], double* [[ARRAYIDX7]], align 8 4314 // CHECK17-NEXT: [[CONV8:%.*]] = fpext double [[CONV]] to x86_fp80 4315 // CHECK17-NEXT: [[TMP20:%.*]] = load x86_fp80*, x86_fp80** [[VLA1_ADDR]], align 8 4316 // CHECK17-NEXT: [[B9:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[TMP1]], i32 0, i32 1 4317 // CHECK17-NEXT: [[TMP21:%.*]] = load i32, i32* [[B9]], align 4 4318 // CHECK17-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP21]] to i64 4319 // CHECK17-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds x86_fp80, x86_fp80* [[TMP20]], i64 [[IDXPROM10]] 4320 // CHECK17-NEXT: store x86_fp80 [[CONV8]], x86_fp80* [[ARRAYIDX11]], align 16 4321 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast double* [[DOTVLA2__ADDR]] to i8* 4322 // CHECK17-NEXT: call void @__kmpc_free(i32 [[TMP12]], i8* [[TMP22]], i8* inttoptr (i64 8 to i8*)) 4323 // CHECK17-NEXT: ret void 4324 // 4325