xref: /llvm-project/clang/test/OpenMP/nvptx_nested_parallel_codegen.cpp (revision f9c29878b04b2d0725eb05716363b27bcda22a5f) 
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test target codegen - host bc file has to be created first.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2
7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix=CHECK2
8 
9 // expected-no-diagnostics
10 #ifndef HEADER
11 #define HEADER
12 
13 void work(int *C) {
14   #pragma omp atomic
15   ++(*C);
16 }
17 
18 void use(int *C) {
19   #pragma omp parallel num_threads(2)
20   work(C);
21 }
22 
23 int main() {
24   int C = 0;
25   #pragma omp target map(C)
26   {
27     use(&C);
28     #pragma omp parallel num_threads(2)
29     use(&C);
30   }
31 
32   return C;
33 }
34 
35 #endif
36 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
37 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {
38 // CHECK1-NEXT:  entry:
39 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
40 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
41 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
42 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
43 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)
44 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
45 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
46 // CHECK1:       user_code.entry:
47 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
48 // CHECK1-NEXT:    call void @_Z3usePi(ptr noundef [[TMP0]]) #[[ATTR7:[0-9]+]]
49 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
50 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP3]], align 8
51 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 2, i32 -1, ptr @__omp_outlined__, ptr @__omp_outlined___wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 1)
52 // CHECK1-NEXT:    call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 1, i1 true)
53 // CHECK1-NEXT:    ret void
54 // CHECK1:       worker.exit:
55 // CHECK1-NEXT:    ret void
56 //
57 //
58 // CHECK1-LABEL: define {{[^@]+}}@_Z3usePi
59 // CHECK1-SAME: (ptr noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] {
60 // CHECK1-NEXT:  entry:
61 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
62 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 8
63 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
64 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
65 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
66 // CHECK1-NEXT:    store ptr [[C_ADDR]], ptr [[TMP1]], align 8
67 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 2, i32 -1, ptr @__omp_outlined__1, ptr @__omp_outlined__1_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 1)
68 // CHECK1-NEXT:    ret void
69 //
70 //
71 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
72 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2:[0-9]+]] {
73 // CHECK1-NEXT:  entry:
74 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
75 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
76 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
77 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
78 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
79 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
80 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
81 // CHECK1-NEXT:    call void @_Z3usePi(ptr noundef [[TMP0]]) #[[ATTR7]]
82 // CHECK1-NEXT:    ret void
83 //
84 //
85 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined___wrapper
86 // CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
87 // CHECK1-NEXT:  entry:
88 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
89 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
90 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
91 // CHECK1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
92 // CHECK1-NEXT:    store i16 [[TMP0]], ptr [[DOTADDR]], align 2
93 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTADDR1]], align 4
94 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
95 // CHECK1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
96 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ARGS]], align 8
97 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP2]], i64 0
98 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP3]], align 8
99 // CHECK1-NEXT:    call void @__omp_outlined__(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]], ptr [[TMP5]]) #[[ATTR4:[0-9]+]]
100 // CHECK1-NEXT:    ret void
101 //
102 //
103 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
104 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR2]] {
105 // CHECK1-NEXT:  entry:
106 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
107 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
108 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
109 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
110 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
111 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
112 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
113 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8
114 // CHECK1-NEXT:    call void @_Z4workPi(ptr noundef [[TMP1]]) #[[ATTR7]]
115 // CHECK1-NEXT:    ret void
116 //
117 //
118 // CHECK1-LABEL: define {{[^@]+}}@_Z4workPi
119 // CHECK1-SAME: (ptr noundef [[C:%.*]]) #[[ATTR1]] {
120 // CHECK1-NEXT:  entry:
121 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
122 // CHECK1-NEXT:    [[ATOMIC_TEMP:%.*]] = alloca i32, align 4
123 // CHECK1-NEXT:    [[ATOMIC_TEMP1:%.*]] = alloca i32, align 4
124 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
125 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
126 // CHECK1-NEXT:    call void @__atomic_load(i64 noundef 4, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 0) #[[ATTR7]]
127 // CHECK1-NEXT:    br label [[ATOMIC_CONT:%.*]]
128 // CHECK1:       atomic_cont:
129 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4
130 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
131 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[ATOMIC_TEMP1]], align 4
132 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i64 noundef 4, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], ptr noundef [[ATOMIC_TEMP1]], i32 noundef 0, i32 noundef 0) #[[ATTR7]]
133 // CHECK1-NEXT:    br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]]
134 // CHECK1:       atomic_exit:
135 // CHECK1-NEXT:    ret void
136 //
137 //
138 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
139 // CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] {
140 // CHECK1-NEXT:  entry:
141 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
142 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
143 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
144 // CHECK1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
145 // CHECK1-NEXT:    store i16 [[TMP0]], ptr [[DOTADDR]], align 2
146 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTADDR1]], align 4
147 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
148 // CHECK1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
149 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ARGS]], align 8
150 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP2]], i64 0
151 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP3]], align 8
152 // CHECK1-NEXT:    call void @__omp_outlined__1(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]], ptr [[TMP5]]) #[[ATTR4]]
153 // CHECK1-NEXT:    ret void
154 //
155 //
156 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l25
157 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR0:[0-9]+]] {
158 // CHECK2-NEXT:  entry:
159 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
160 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
161 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
162 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
163 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)
164 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
165 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
166 // CHECK2:       user_code.entry:
167 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
168 // CHECK2-NEXT:    call void @_Z3usePi(ptr noundef [[TMP0]]) #[[ATTR7:[0-9]+]]
169 // CHECK2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
170 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP3]], align 4
171 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 2, i32 -1, ptr @__omp_outlined__, ptr @__omp_outlined___wrapper, ptr [[CAPTURED_VARS_ADDRS]], i32 1)
172 // CHECK2-NEXT:    call void @__kmpc_target_deinit(ptr @[[GLOB1]], i8 1, i1 true)
173 // CHECK2-NEXT:    ret void
174 // CHECK2:       worker.exit:
175 // CHECK2-NEXT:    ret void
176 //
177 //
178 // CHECK2-LABEL: define {{[^@]+}}@_Z3usePi
179 // CHECK2-SAME: (ptr noundef [[C:%.*]]) #[[ATTR1:[0-9]+]] {
180 // CHECK2-NEXT:  entry:
181 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
182 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x ptr], align 4
183 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
184 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
185 // CHECK2-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
186 // CHECK2-NEXT:    store ptr [[C_ADDR]], ptr [[TMP1]], align 4
187 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 2, i32 -1, ptr @__omp_outlined__1, ptr @__omp_outlined__1_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i32 1)
188 // CHECK2-NEXT:    ret void
189 //
190 //
191 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
192 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2:[0-9]+]] {
193 // CHECK2-NEXT:  entry:
194 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
195 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
196 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
197 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
198 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
199 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
200 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
201 // CHECK2-NEXT:    call void @_Z3usePi(ptr noundef [[TMP0]]) #[[ATTR7]]
202 // CHECK2-NEXT:    ret void
203 //
204 //
205 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined___wrapper
206 // CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
207 // CHECK2-NEXT:  entry:
208 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
209 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
210 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
211 // CHECK2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 4
212 // CHECK2-NEXT:    store i16 [[TMP0]], ptr [[DOTADDR]], align 2
213 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTADDR1]], align 4
214 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
215 // CHECK2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
216 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ARGS]], align 4
217 // CHECK2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP2]], i32 0
218 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP3]], align 4
219 // CHECK2-NEXT:    call void @__omp_outlined__(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]], ptr [[TMP5]]) #[[ATTR4:[0-9]+]]
220 // CHECK2-NEXT:    ret void
221 //
222 //
223 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
224 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR2]] {
225 // CHECK2-NEXT:  entry:
226 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
227 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
228 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
229 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
230 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
231 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
232 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
233 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4
234 // CHECK2-NEXT:    call void @_Z4workPi(ptr noundef [[TMP1]]) #[[ATTR7]]
235 // CHECK2-NEXT:    ret void
236 //
237 //
238 // CHECK2-LABEL: define {{[^@]+}}@_Z4workPi
239 // CHECK2-SAME: (ptr noundef [[C:%.*]]) #[[ATTR1]] {
240 // CHECK2-NEXT:  entry:
241 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
242 // CHECK2-NEXT:    [[ATOMIC_TEMP:%.*]] = alloca i32, align 4
243 // CHECK2-NEXT:    [[ATOMIC_TEMP1:%.*]] = alloca i32, align 4
244 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
245 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
246 // CHECK2-NEXT:    call void @__atomic_load(i32 noundef 4, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], i32 noundef 0) #[[ATTR7]]
247 // CHECK2-NEXT:    br label [[ATOMIC_CONT:%.*]]
248 // CHECK2:       atomic_cont:
249 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4
250 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
251 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[ATOMIC_TEMP1]], align 4
252 // CHECK2-NEXT:    [[CALL:%.*]] = call noundef zeroext i1 @__atomic_compare_exchange(i32 noundef 4, ptr noundef [[TMP0]], ptr noundef [[ATOMIC_TEMP]], ptr noundef [[ATOMIC_TEMP1]], i32 noundef 0, i32 noundef 0) #[[ATTR7]]
253 // CHECK2-NEXT:    br i1 [[CALL]], label [[ATOMIC_EXIT:%.*]], label [[ATOMIC_CONT]]
254 // CHECK2:       atomic_exit:
255 // CHECK2-NEXT:    ret void
256 //
257 //
258 // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
259 // CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] {
260 // CHECK2-NEXT:  entry:
261 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
262 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
263 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
264 // CHECK2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 4
265 // CHECK2-NEXT:    store i16 [[TMP0]], ptr [[DOTADDR]], align 2
266 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTADDR1]], align 4
267 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
268 // CHECK2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
269 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[GLOBAL_ARGS]], align 4
270 // CHECK2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP2]], i32 0
271 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP3]], align 4
272 // CHECK2-NEXT:    call void @__omp_outlined__1(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]], ptr [[TMP5]]) #[[ATTR4]]
273 // CHECK2-NEXT:    ret void
274 //
275