1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 6 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 7 8 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 9 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s 10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // expected-no-diagnostics 14 #ifndef HEADER 15 #define HEADER 16 17 template <class T> 18 struct S { 19 T f; 20 S(T a) : f(a) {} 21 S() : f() {} 22 operator T() { return T(); } 23 ~S() {} 24 }; 25 26 volatile double g; 27 volatile double &g1 = g; 28 29 template <typename T> 30 T tmain() { 31 S<T> test; 32 T t_var = T(); 33 T vec[] = {1, 2}; 34 S<T> s_arr[] = {1, 2}; 35 S<T> &var = test; 36 #pragma omp parallel 37 #pragma omp for private(t_var, vec, s_arr, s_arr, var, var) 38 for (int i = 0; i < 2; ++i) { 39 vec[i] = t_var; 40 s_arr[i] = var; 41 } 42 return T(); 43 } 44 45 int main() { 46 static int svar; 47 #ifdef LAMBDA 48 [&]() { 49 static float sfvar; 50 #pragma omp parallel 51 #pragma omp for private(g, g1, svar, sfvar) 52 for (int i = 0; i < 2; ++i) { 53 g = 1; 54 g1 = 1; 55 svar = 3; 56 sfvar = 4.0; 57 [&]() { 58 g = 2; 59 g1 = 2; 60 svar = 4; 61 sfvar = 8.0; 62 }(); 63 } 64 }(); 65 return 0; 66 #elif defined(BLOCKS) 67 ^{ 68 static float sfvar; 69 #pragma omp parallel 70 #pragma omp for private(g, g1, svar, sfvar) 71 for (int i = 0; i < 2; ++i) { 72 g = 1; 73 g1 = 1; 74 svar = 2; 75 sfvar = 3.0; 76 ^{ 77 g = 2; 78 g1 = 2; 79 svar = 4; 80 sfvar = 9.0; 81 }(); 82 } 83 }(); 84 return 0; 85 #else 86 S<float> test; 87 int t_var = 0; 88 int vec[] = {1, 2}; 89 S<float> s_arr[] = {1, 2}; 90 S<float> &var = test; 91 #pragma omp parallel 92 #pragma omp for private(t_var, vec, s_arr, s_arr, var, var, svar) 93 for (int i = 0; i < 2; ++i) { 94 vec[i] = t_var; 95 s_arr[i] = var; 96 } 97 int i; 98 #pragma omp parallel 99 #pragma omp for private(i) 100 for (i = 0; i < 2; ++i) { 101 ; 102 } 103 return tmain<int>(); 104 #endif 105 } 106 107 108 #endif 109 110 // CHECK1-LABEL: define {{[^@]+}}@main 111 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 112 // CHECK1-NEXT: entry: 113 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 114 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 115 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 116 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 117 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 118 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 119 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 120 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 121 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 122 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 123 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false) 124 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 125 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00) 126 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1 127 // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) 128 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 129 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @.omp_outlined.) 130 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..1) 131 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() 132 // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 133 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 134 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 135 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 136 // CHECK1: arraydestroy.body: 137 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 138 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 139 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] 140 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 141 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 142 // CHECK1: arraydestroy.done1: 143 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 144 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4 145 // CHECK1-NEXT: ret i32 [[TMP2]] 146 // 147 // 148 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev 149 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { 150 // CHECK1-NEXT: entry: 151 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 152 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 153 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 154 // CHECK1-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 155 // CHECK1-NEXT: ret void 156 // 157 // 158 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef 159 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 160 // CHECK1-NEXT: entry: 161 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 162 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 163 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 164 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 165 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 166 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 167 // CHECK1-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]]) 168 // CHECK1-NEXT: ret void 169 // 170 // 171 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 172 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 173 // CHECK1-NEXT: entry: 174 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 175 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 176 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 177 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 178 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 179 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 180 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 181 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 182 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 183 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 184 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 185 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 186 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 187 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 188 // CHECK1-NEXT: [[SVAR:%.*]] = alloca i32, align 4 189 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 190 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 191 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 192 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 193 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 194 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 195 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 196 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 197 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 198 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 199 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 200 // CHECK1: arrayctor.loop: 201 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 202 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 203 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 204 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 205 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 206 // CHECK1: arrayctor.cont: 207 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 208 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 209 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 210 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 211 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 212 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 213 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 214 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 215 // CHECK1: cond.true: 216 // CHECK1-NEXT: br label [[COND_END:%.*]] 217 // CHECK1: cond.false: 218 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 219 // CHECK1-NEXT: br label [[COND_END]] 220 // CHECK1: cond.end: 221 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 222 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 223 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 224 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 225 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 226 // CHECK1: omp.inner.for.cond: 227 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 228 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 229 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 230 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 231 // CHECK1: omp.inner.for.cond.cleanup: 232 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 233 // CHECK1: omp.inner.for.body: 234 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 235 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 236 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 237 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 238 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 239 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 240 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 241 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 242 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 243 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 244 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 245 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 246 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] 247 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) 248 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 249 // CHECK1: omp.body.continue: 250 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 251 // CHECK1: omp.inner.for.inc: 252 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 253 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 254 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 255 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 256 // CHECK1: omp.inner.for.end: 257 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 258 // CHECK1: omp.loop.exit: 259 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 260 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 261 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP16]]) 262 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 263 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 264 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 265 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 266 // CHECK1: arraydestroy.body: 267 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 268 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 269 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 270 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 271 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 272 // CHECK1: arraydestroy.done8: 273 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 274 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 275 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP19]]) 276 // CHECK1-NEXT: ret void 277 // 278 // 279 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev 280 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 281 // CHECK1-NEXT: entry: 282 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 283 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 284 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 285 // CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 286 // CHECK1-NEXT: ret void 287 // 288 // 289 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 290 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 291 // CHECK1-NEXT: entry: 292 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 293 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 294 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 295 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 296 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 297 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 298 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 299 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 300 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 301 // CHECK1-NEXT: [[I1:%.*]] = alloca i32, align 4 302 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 303 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 304 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 305 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 306 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 307 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 308 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 309 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 310 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 311 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 312 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 313 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 314 // CHECK1: cond.true: 315 // CHECK1-NEXT: br label [[COND_END:%.*]] 316 // CHECK1: cond.false: 317 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 318 // CHECK1-NEXT: br label [[COND_END]] 319 // CHECK1: cond.end: 320 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 321 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 322 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 323 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 324 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 325 // CHECK1: omp.inner.for.cond: 326 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 327 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 328 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 329 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 330 // CHECK1: omp.inner.for.body: 331 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 332 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 333 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 334 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 335 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 336 // CHECK1: omp.body.continue: 337 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 338 // CHECK1: omp.inner.for.inc: 339 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 340 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 341 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 342 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 343 // CHECK1: omp.inner.for.end: 344 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 345 // CHECK1: omp.loop.exit: 346 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 347 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP1]]) 348 // CHECK1-NEXT: ret void 349 // 350 // 351 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v 352 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat { 353 // CHECK1-NEXT: entry: 354 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 355 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 356 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 357 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 358 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 359 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 360 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) 361 // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 362 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false) 363 // CHECK1-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 364 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1) 365 // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1 366 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) 367 // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 368 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @.omp_outlined..2) 369 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 370 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 371 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 372 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 373 // CHECK1: arraydestroy.body: 374 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 375 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 376 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 377 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] 378 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] 379 // CHECK1: arraydestroy.done1: 380 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] 381 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4 382 // CHECK1-NEXT: ret i32 [[TMP2]] 383 // 384 // 385 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev 386 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 387 // CHECK1-NEXT: entry: 388 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 389 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 390 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 391 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 392 // CHECK1-NEXT: store float 0.000000e+00, ptr [[F]], align 4 393 // CHECK1-NEXT: ret void 394 // 395 // 396 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef 397 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 398 // CHECK1-NEXT: entry: 399 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 400 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 401 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 402 // CHECK1-NEXT: store float [[A]], ptr [[A_ADDR]], align 4 403 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 404 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 405 // CHECK1-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4 406 // CHECK1-NEXT: store float [[TMP0]], ptr [[F]], align 4 407 // CHECK1-NEXT: ret void 408 // 409 // 410 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev 411 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 412 // CHECK1-NEXT: entry: 413 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 414 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 415 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 416 // CHECK1-NEXT: ret void 417 // 418 // 419 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev 420 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 421 // CHECK1-NEXT: entry: 422 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 423 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 424 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 425 // CHECK1-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) 426 // CHECK1-NEXT: ret void 427 // 428 // 429 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei 430 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 431 // CHECK1-NEXT: entry: 432 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 433 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 434 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 435 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 436 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 437 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 438 // CHECK1-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]) 439 // CHECK1-NEXT: ret void 440 // 441 // 442 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 443 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] { 444 // CHECK1-NEXT: entry: 445 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 446 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 447 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 448 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 449 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 450 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 451 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 452 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 453 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 454 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 455 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 456 // CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 457 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 458 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 459 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 460 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 461 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 462 // CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 463 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 464 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 465 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 466 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 467 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 468 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 469 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] 470 // CHECK1: arrayctor.loop: 471 // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] 472 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) 473 // CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 474 // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] 475 // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] 476 // CHECK1: arrayctor.cont: 477 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) 478 // CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 8 479 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 480 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 481 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 482 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 483 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 484 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 485 // CHECK1: cond.true: 486 // CHECK1-NEXT: br label [[COND_END:%.*]] 487 // CHECK1: cond.false: 488 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 489 // CHECK1-NEXT: br label [[COND_END]] 490 // CHECK1: cond.end: 491 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 492 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 493 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 494 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 495 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 496 // CHECK1: omp.inner.for.cond: 497 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 498 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 499 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 500 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 501 // CHECK1: omp.inner.for.cond.cleanup: 502 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 503 // CHECK1: omp.inner.for.body: 504 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 505 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 506 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 507 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 508 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 509 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 510 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 511 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] 512 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 513 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 514 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 515 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 516 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] 517 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) 518 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 519 // CHECK1: omp.body.continue: 520 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 521 // CHECK1: omp.inner.for.inc: 522 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 523 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], 1 524 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 525 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 526 // CHECK1: omp.inner.for.end: 527 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 528 // CHECK1: omp.loop.exit: 529 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 530 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 531 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP16]]) 532 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] 533 // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 534 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 535 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] 536 // CHECK1: arraydestroy.body: 537 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] 538 // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 539 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] 540 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] 541 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] 542 // CHECK1: arraydestroy.done8: 543 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 544 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 545 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP19]]) 546 // CHECK1-NEXT: ret void 547 // 548 // 549 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev 550 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 551 // CHECK1-NEXT: entry: 552 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 553 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 554 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 555 // CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] 556 // CHECK1-NEXT: ret void 557 // 558 // 559 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev 560 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 561 // CHECK1-NEXT: entry: 562 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 563 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 564 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 565 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 566 // CHECK1-NEXT: store i32 0, ptr [[F]], align 4 567 // CHECK1-NEXT: ret void 568 // 569 // 570 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei 571 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 572 // CHECK1-NEXT: entry: 573 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 574 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 575 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 576 // CHECK1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 577 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 578 // CHECK1-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 579 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 580 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[F]], align 4 581 // CHECK1-NEXT: ret void 582 // 583 // 584 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev 585 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { 586 // CHECK1-NEXT: entry: 587 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 588 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 589 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 590 // CHECK1-NEXT: ret void 591 // 592 // 593 // CHECK3-LABEL: define {{[^@]+}}@main 594 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 595 // CHECK3-NEXT: entry: 596 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 597 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 598 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 599 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]]) 600 // CHECK3-NEXT: ret i32 0 601 // 602 // 603 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 604 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { 605 // CHECK3-NEXT: entry: 606 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 607 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 608 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 609 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 610 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 611 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 612 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 613 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 614 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 615 // CHECK3-NEXT: [[G:%.*]] = alloca double, align 8 616 // CHECK3-NEXT: [[G1:%.*]] = alloca double, align 8 617 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 618 // CHECK3-NEXT: [[SVAR:%.*]] = alloca i32, align 4 619 // CHECK3-NEXT: [[SFVAR:%.*]] = alloca float, align 4 620 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 621 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 622 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 623 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 624 // CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 8 625 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 626 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 627 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 628 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 629 // CHECK3-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 630 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 631 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 632 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 633 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 634 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 635 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 636 // CHECK3: cond.true: 637 // CHECK3-NEXT: br label [[COND_END:%.*]] 638 // CHECK3: cond.false: 639 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 640 // CHECK3-NEXT: br label [[COND_END]] 641 // CHECK3: cond.end: 642 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 643 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 644 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 645 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 646 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 647 // CHECK3: omp.inner.for.cond: 648 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 649 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 650 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 651 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 652 // CHECK3: omp.inner.for.body: 653 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 654 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 655 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 656 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 657 // CHECK3-NEXT: store double 1.000000e+00, ptr [[G]], align 8 658 // CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 659 // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP8]], align 8 660 // CHECK3-NEXT: store i32 3, ptr [[SVAR]], align 4 661 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR]], align 4 662 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 663 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 664 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 665 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 666 // CHECK3-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 667 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 668 // CHECK3-NEXT: store ptr [[SVAR]], ptr [[TMP12]], align 8 669 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 670 // CHECK3-NEXT: store ptr [[SFVAR]], ptr [[TMP13]], align 8 671 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) 672 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 673 // CHECK3: omp.body.continue: 674 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 675 // CHECK3: omp.inner.for.inc: 676 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 677 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], 1 678 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 679 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 680 // CHECK3: omp.inner.for.end: 681 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 682 // CHECK3: omp.loop.exit: 683 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 684 // CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]]) 685 // CHECK3-NEXT: ret void 686 // 687 // 688 // CHECK4-LABEL: define {{[^@]+}}@main 689 // CHECK4-SAME: () #[[ATTR1:[0-9]+]] { 690 // CHECK4-NEXT: entry: 691 // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 692 // CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4 693 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8 694 // CHECK4-NEXT: call void [[TMP0]](ptr noundef @__block_literal_global) 695 // CHECK4-NEXT: ret i32 0 696 // 697 // 698 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke 699 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { 700 // CHECK4-NEXT: entry: 701 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 702 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 703 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 704 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 705 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @.omp_outlined.) 706 // CHECK4-NEXT: ret void 707 // 708 // 709 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 710 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 711 // CHECK4-NEXT: entry: 712 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 713 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 714 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 715 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 716 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 717 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 718 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 719 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 720 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 721 // CHECK4-NEXT: [[G:%.*]] = alloca double, align 8 722 // CHECK4-NEXT: [[G1:%.*]] = alloca double, align 8 723 // CHECK4-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 724 // CHECK4-NEXT: [[SVAR:%.*]] = alloca i32, align 4 725 // CHECK4-NEXT: [[SFVAR:%.*]] = alloca float, align 4 726 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 727 // CHECK4-NEXT: [[BLOCK:%.*]] = alloca <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, align 8 728 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 729 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 730 // CHECK4-NEXT: store ptr undef, ptr [[_TMP1]], align 8 731 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 732 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 733 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 734 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 735 // CHECK4-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 736 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 737 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 738 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) 739 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 740 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1 741 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 742 // CHECK4: cond.true: 743 // CHECK4-NEXT: br label [[COND_END:%.*]] 744 // CHECK4: cond.false: 745 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 746 // CHECK4-NEXT: br label [[COND_END]] 747 // CHECK4: cond.end: 748 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 749 // CHECK4-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 750 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 751 // CHECK4-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 752 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 753 // CHECK4: omp.inner.for.cond: 754 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 755 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 756 // CHECK4-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 757 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 758 // CHECK4: omp.inner.for.body: 759 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 760 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 761 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 762 // CHECK4-NEXT: store i32 [[ADD]], ptr [[I]], align 4 763 // CHECK4-NEXT: store double 1.000000e+00, ptr [[G]], align 8 764 // CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 765 // CHECK4-NEXT: store volatile double 1.000000e+00, ptr [[TMP8]], align 8 766 // CHECK4-NEXT: store i32 2, ptr [[SVAR]], align 4 767 // CHECK4-NEXT: store float 3.000000e+00, ptr [[SFVAR]], align 4 768 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 0 769 // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 770 // CHECK4-NEXT: [[BLOCK_FLAGS:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 1 771 // CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS]], align 8 772 // CHECK4-NEXT: [[BLOCK_RESERVED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 2 773 // CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED]], align 4 774 // CHECK4-NEXT: [[BLOCK_INVOKE:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 3 775 // CHECK4-NEXT: store ptr @g1_block_invoke_2, ptr [[BLOCK_INVOKE]], align 8 776 // CHECK4-NEXT: [[BLOCK_DESCRIPTOR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 4 777 // CHECK4-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR]], align 8 778 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 5 779 // CHECK4-NEXT: [[TMP9:%.*]] = load volatile double, ptr [[G]], align 8 780 // CHECK4-NEXT: store volatile double [[TMP9]], ptr [[BLOCK_CAPTURED]], align 8 781 // CHECK4-NEXT: [[BLOCK_CAPTURED4:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 6 782 // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 783 // CHECK4-NEXT: store ptr [[TMP10]], ptr [[BLOCK_CAPTURED4]], align 8 784 // CHECK4-NEXT: [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 7 785 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[SVAR]], align 4 786 // CHECK4-NEXT: store i32 [[TMP11]], ptr [[BLOCK_CAPTURED5]], align 8 787 // CHECK4-NEXT: [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 8 788 // CHECK4-NEXT: [[TMP12:%.*]] = load float, ptr [[SFVAR]], align 4 789 // CHECK4-NEXT: store float [[TMP12]], ptr [[BLOCK_CAPTURED6]], align 4 790 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 791 // CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP14]], align 8 792 // CHECK4-NEXT: call void [[TMP16]](ptr noundef [[BLOCK]]) 793 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 794 // CHECK4: omp.body.continue: 795 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 796 // CHECK4: omp.inner.for.inc: 797 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 798 // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP18]], 1 799 // CHECK4-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 800 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 801 // CHECK4: omp.inner.for.end: 802 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 803 // CHECK4: omp.loop.exit: 804 // CHECK4-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) 805 // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]]) 806 // CHECK4-NEXT: ret void 807 // 808 // 809 // CHECK4-LABEL: define {{[^@]+}}@g1_block_invoke_2 810 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { 811 // CHECK4-NEXT: entry: 812 // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 813 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 814 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 815 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 816 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 817 // CHECK4-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8 818 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 819 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 8 820 // CHECK4-NEXT: store double 2.000000e+00, ptr [[TMP0]], align 8 821 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 822 // CHECK4-NEXT: store i32 4, ptr [[BLOCK_CAPTURE_ADDR2]], align 8 823 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8 824 // CHECK4-NEXT: store float 9.000000e+00, ptr [[BLOCK_CAPTURE_ADDR3]], align 4 825 // CHECK4-NEXT: ret void 826 // 827