xref: /illumos-gate/usr/src/uts/intel/sys/vmm_data.h (revision 09ea9c53cd9ac02c506f68475d98e8f07b457ffc)
1d515dd77SPatrick Mooney /*
2d515dd77SPatrick Mooney  * This file and its contents are supplied under the terms of the
3d515dd77SPatrick Mooney  * Common Development and Distribution License ("CDDL"), version 1.0.
4d515dd77SPatrick Mooney  * You may only use this file in accordance with the terms of version
5d515dd77SPatrick Mooney  * 1.0 of the CDDL.
6d515dd77SPatrick Mooney  *
7d515dd77SPatrick Mooney  * A full copy of the text of the CDDL should have accompanied this
8d515dd77SPatrick Mooney  * source.  A copy of the CDDL is also available via the Internet at
9d515dd77SPatrick Mooney  * http://www.illumos.org/license/CDDL.
10d515dd77SPatrick Mooney  */
11d515dd77SPatrick Mooney /* This file is dual-licensed; see usr/src/contrib/bhyve/LICENSE */
12d515dd77SPatrick Mooney 
13d515dd77SPatrick Mooney /*
14*09ea9c53SPatrick Mooney  * Copyright 2025 Oxide Computer Company
15d515dd77SPatrick Mooney  */
16d515dd77SPatrick Mooney 
17d515dd77SPatrick Mooney #ifndef _VMM_DATA_H_
18d515dd77SPatrick Mooney #define	_VMM_DATA_H_
19d515dd77SPatrick Mooney 
20d515dd77SPatrick Mooney /* VMM Data Classes */
21d515dd77SPatrick Mooney #define	VDC_VERSION	1	/* Version information for each data class */
22d515dd77SPatrick Mooney 
23d515dd77SPatrick Mooney /* Classes bearing per-CPU data */
24d515dd77SPatrick Mooney #define	VDC_REGISTER	2	/* Registers (GPR, segment, etc) */
25d515dd77SPatrick Mooney #define	VDC_MSR		3	/* Model-specific registers */
26d515dd77SPatrick Mooney #define	VDC_FPU		4	/* FPU (and associated SIMD) */
27d515dd77SPatrick Mooney #define	VDC_LAPIC	5	/* Local APIC */
28d515dd77SPatrick Mooney #define	VDC_VMM_ARCH	6	/* Arch-specific VMM state (VMX/SVM) */
29*09ea9c53SPatrick Mooney #define	VDC_PMU_AMD	14	/* PMU for AMD CPUs */
30d515dd77SPatrick Mooney 
31d515dd77SPatrick Mooney /* Classes for system-wide devices */
32d515dd77SPatrick Mooney #define	VDC_IOAPIC	7	/* bhyve IO-APIC */
33d515dd77SPatrick Mooney #define	VDC_ATPIT	8	/* i8254 PIT */
34d515dd77SPatrick Mooney #define	VDC_ATPIC	9	/* i8259 PIC */
35d515dd77SPatrick Mooney #define	VDC_HPET	10	/* HPET */
36d515dd77SPatrick Mooney #define	VDC_PM_TIMER	11	/* ACPI Power Management Timer */
37d515dd77SPatrick Mooney #define	VDC_RTC		12	/* IBM PC Real Time Clock */
38d515dd77SPatrick Mooney 
39717646f7SJordan Paige Hendricks #define	VDC_VMM_TIME	13	/* Time-related VMM data */
40717646f7SJordan Paige Hendricks 
41d515dd77SPatrick Mooney /* Indicates top of VMM Data Class range, updated as classes are added */
42*09ea9c53SPatrick Mooney #define	VDC_MAX		(VDC_PMU_AMD + 1)
43d515dd77SPatrick Mooney 
44d515dd77SPatrick Mooney 
45d515dd77SPatrick Mooney /* VMM Data Identifiers */
46d515dd77SPatrick Mooney 
47d515dd77SPatrick Mooney /*
4854cf5b63SPatrick Mooney  * Generic field encoding for 64-bit (or smaller) data which are identified by a
4954cf5b63SPatrick Mooney  * 32-bit (or smaller) name.
50d515dd77SPatrick Mooney  *
5154cf5b63SPatrick Mooney  * Used by the following classes/version:
5254cf5b63SPatrick Mooney  * - VDC_REGISTER v1: `vm_reg_name` identifiers
5354cf5b63SPatrick Mooney  * - VDC_MSR v1: MSR identifiers
5454cf5b63SPatrick Mooney  * - VDC_VMM_ARCH v1: Identifiers described below
55d515dd77SPatrick Mooney  */
5654cf5b63SPatrick Mooney struct vdi_field_entry_v1 {
5754cf5b63SPatrick Mooney 	uint32_t	vfe_ident;
58d515dd77SPatrick Mooney 	uint32_t	_pad;
5954cf5b63SPatrick Mooney 	uint64_t	vfe_value;
6054cf5b63SPatrick Mooney };
6154cf5b63SPatrick Mooney 
6254cf5b63SPatrick Mooney /* VDC_VERSION */
6354cf5b63SPatrick Mooney struct vdi_version_entry_v1 {
6454cf5b63SPatrick Mooney 	uint16_t	vve_class;
6554cf5b63SPatrick Mooney 	uint16_t	vve_version;
6654cf5b63SPatrick Mooney 	uint16_t	vve_len_expect;
6754cf5b63SPatrick Mooney 	uint16_t	vve_len_per_item;
68d515dd77SPatrick Mooney };
69d515dd77SPatrick Mooney 
70d515dd77SPatrick Mooney /*
71d515dd77SPatrick Mooney  * VDC_FPU:
72d515dd77SPatrick Mooney  *
73d515dd77SPatrick Mooney  * Unimplemented for now.  Use VM_GET_FPU/VM_SET_FPU ioctls.
74d515dd77SPatrick Mooney  */
75d515dd77SPatrick Mooney 
76d515dd77SPatrick Mooney /* VDC_LAPIC: */
77d515dd77SPatrick Mooney 
78d515dd77SPatrick Mooney struct vdi_lapic_page_v1 {
79d515dd77SPatrick Mooney 	uint32_t	vlp_id;
80d515dd77SPatrick Mooney 	uint32_t	vlp_version;
81d515dd77SPatrick Mooney 	uint32_t	vlp_tpr;
82d515dd77SPatrick Mooney 	uint32_t	vlp_apr;
83d515dd77SPatrick Mooney 	uint32_t	vlp_ldr;
84d515dd77SPatrick Mooney 	uint32_t	vlp_dfr;
85d515dd77SPatrick Mooney 	uint32_t	vlp_svr;
86d515dd77SPatrick Mooney 	uint32_t	vlp_isr[8];
87d515dd77SPatrick Mooney 	uint32_t	vlp_tmr[8];
88d515dd77SPatrick Mooney 	uint32_t	vlp_irr[8];
89d515dd77SPatrick Mooney 	uint32_t	vlp_esr;
90d515dd77SPatrick Mooney 	uint32_t	vlp_lvt_cmci;
91d515dd77SPatrick Mooney 	uint64_t	vlp_icr;
92d515dd77SPatrick Mooney 	uint32_t	vlp_lvt_timer;
93d515dd77SPatrick Mooney 	uint32_t	vlp_lvt_thermal;
94d515dd77SPatrick Mooney 	uint32_t	vlp_lvt_pcint;
95d515dd77SPatrick Mooney 	uint32_t	vlp_lvt_lint0;
96d515dd77SPatrick Mooney 	uint32_t	vlp_lvt_lint1;
97d515dd77SPatrick Mooney 	uint32_t	vlp_lvt_error;
98d515dd77SPatrick Mooney 	uint32_t	vlp_icr_timer;
99d515dd77SPatrick Mooney 	uint32_t	vlp_dcr_timer;
100d515dd77SPatrick Mooney };
101d515dd77SPatrick Mooney 
102d515dd77SPatrick Mooney struct vdi_lapic_v1 {
103d515dd77SPatrick Mooney 	struct vdi_lapic_page_v1 vl_lapic;
104d515dd77SPatrick Mooney 	uint64_t		vl_msr_apicbase;
105d515dd77SPatrick Mooney 	int64_t			vl_timer_target;
106d515dd77SPatrick Mooney 	uint32_t		vl_esr_pending;
107d515dd77SPatrick Mooney };
108d515dd77SPatrick Mooney 
109d515dd77SPatrick Mooney /*
110d515dd77SPatrick Mooney  * VDC_VMM_ARCH:
111d515dd77SPatrick Mooney  */
112d515dd77SPatrick Mooney 
113*09ea9c53SPatrick Mooney /* VDC_PMU_AMD: */
114*09ea9c53SPatrick Mooney 
115*09ea9c53SPatrick Mooney struct vdi_pmu_amd_v1 {
116*09ea9c53SPatrick Mooney 	uint64_t	vpa_evtsel[6];
117*09ea9c53SPatrick Mooney 	uint64_t	vpa_ctr[6];
118*09ea9c53SPatrick Mooney };
119*09ea9c53SPatrick Mooney 
12054cf5b63SPatrick Mooney /*
12154cf5b63SPatrick Mooney  * Version 1 identifiers:
12254cf5b63SPatrick Mooney  */
12354cf5b63SPatrick Mooney 
124ad4335f7SPatrick Mooney /*
125ad4335f7SPatrick Mooney  * VM-wide:
126ad4335f7SPatrick Mooney  */
127ad4335f7SPatrick Mooney 
128ad4335f7SPatrick Mooney /* Is the VM currently in the "paused" state? (0 or 1) */
129ad4335f7SPatrick Mooney #define	VAI_VM_IS_PAUSED	4
130ad4335f7SPatrick Mooney 
131ad4335f7SPatrick Mooney /*
132ad4335f7SPatrick Mooney  * per-vCPU:
133ad4335f7SPatrick Mooney  *
134ad4335f7SPatrick Mooney  * Note: While these are currently defined with values disjoint from those in
135ad4335f7SPatrick Mooney  * the VM-wide category, it is not required that they be.  The VM-wide and
136ad4335f7SPatrick Mooney  * per-vCPU identifiers are distinguished by vm_data_xfer`vdx_vcpuid.
137ad4335f7SPatrick Mooney  */
138ad4335f7SPatrick Mooney 
139ad4335f7SPatrick Mooney /* NMI pending injection for vCPU (0 or 1) */
140ad4335f7SPatrick Mooney #define	VAI_PEND_NMI		10
141ad4335f7SPatrick Mooney /* extint pending injection for vCPU (0 or 1) */
142ad4335f7SPatrick Mooney #define	VAI_PEND_EXTINT		11
143ad4335f7SPatrick Mooney /* HW exception pending injection for vCPU */
144ad4335f7SPatrick Mooney #define	VAI_PEND_EXCP		12
145ad4335f7SPatrick Mooney /* exception/interrupt pending injection for vCPU */
146ad4335f7SPatrick Mooney #define	VAI_PEND_INTINFO	13
14754cf5b63SPatrick Mooney 
148d515dd77SPatrick Mooney /* VDC_IOAPIC: */
149d515dd77SPatrick Mooney 
150d515dd77SPatrick Mooney struct vdi_ioapic_v1 {
151d515dd77SPatrick Mooney 	uint64_t	vi_pin_reg[32];
152d515dd77SPatrick Mooney 	uint32_t	vi_pin_level[32];
153d515dd77SPatrick Mooney 	uint32_t	vi_id;
154d515dd77SPatrick Mooney 	uint32_t	vi_reg_sel;
155d515dd77SPatrick Mooney };
156d515dd77SPatrick Mooney 
157d515dd77SPatrick Mooney /* VDC_ATPIT: */
158d515dd77SPatrick Mooney 
159d515dd77SPatrick Mooney struct vdi_atpit_channel_v1 {
160d515dd77SPatrick Mooney 	uint16_t	vac_initial;
161d515dd77SPatrick Mooney 	uint16_t	vac_reg_cr;
162d515dd77SPatrick Mooney 	uint16_t	vac_reg_ol;
163d515dd77SPatrick Mooney 	uint8_t		vac_reg_status;
164d515dd77SPatrick Mooney 	uint8_t		vac_mode;
165d515dd77SPatrick Mooney 	/*
166d515dd77SPatrick Mooney 	 * vac_status bits:
167d515dd77SPatrick Mooney 	 * - 0b00001 status latched
168d515dd77SPatrick Mooney 	 * - 0b00010 output latched
169d515dd77SPatrick Mooney 	 * - 0b00100 control register sel
170d515dd77SPatrick Mooney 	 * - 0b01000 output latch sel
171d515dd77SPatrick Mooney 	 * - 0b10000 free-running timer
172d515dd77SPatrick Mooney 	 */
173d515dd77SPatrick Mooney 	uint8_t		vac_status;
174d515dd77SPatrick Mooney 
175d515dd77SPatrick Mooney 	int64_t		vac_time_target;
176d515dd77SPatrick Mooney };
177d515dd77SPatrick Mooney 
178d515dd77SPatrick Mooney struct vdi_atpit_v1 {
179d515dd77SPatrick Mooney 	struct vdi_atpit_channel_v1 va_channel[3];
180d515dd77SPatrick Mooney };
181d515dd77SPatrick Mooney 
182d515dd77SPatrick Mooney /* VDC_ATPIC: */
183d515dd77SPatrick Mooney 
184d515dd77SPatrick Mooney struct vdi_atpic_chip_v1 {
185d515dd77SPatrick Mooney 	uint8_t		vac_icw_state;
186d515dd77SPatrick Mooney 	/*
187d515dd77SPatrick Mooney 	 * vac_status bits:
188d515dd77SPatrick Mooney 	 * - 0b00000001 ready
189d515dd77SPatrick Mooney 	 * - 0b00000010 auto EOI
190d515dd77SPatrick Mooney 	 * - 0b00000100 poll
191d515dd77SPatrick Mooney 	 * - 0b00001000 rotate
192d515dd77SPatrick Mooney 	 * - 0b00010000 special full nested
193d515dd77SPatrick Mooney 	 * - 0b00100000 read isr next
194d515dd77SPatrick Mooney 	 * - 0b01000000 intr raised
195d515dd77SPatrick Mooney 	 * - 0b10000000 special mask mode
196d515dd77SPatrick Mooney 	 */
197d515dd77SPatrick Mooney 	uint8_t		vac_status;
198d515dd77SPatrick Mooney 	uint8_t		vac_reg_irr;
199d515dd77SPatrick Mooney 	uint8_t		vac_reg_isr;
200d515dd77SPatrick Mooney 	uint8_t		vac_reg_imr;
201d515dd77SPatrick Mooney 	uint8_t		vac_irq_base;
202d515dd77SPatrick Mooney 	uint8_t		vac_lowprio;
203d515dd77SPatrick Mooney 	uint8_t		vac_elc;
204d515dd77SPatrick Mooney 	uint32_t	vac_level[8];
205d515dd77SPatrick Mooney };
206d515dd77SPatrick Mooney 
207d515dd77SPatrick Mooney struct vdi_atpic_v1 {
208d515dd77SPatrick Mooney 	struct vdi_atpic_chip_v1 va_chip[2];
209d515dd77SPatrick Mooney };
210d515dd77SPatrick Mooney 
211d515dd77SPatrick Mooney /* VDC_HPET: */
212d515dd77SPatrick Mooney 
213d515dd77SPatrick Mooney struct vdi_hpet_timer_v1 {
214d515dd77SPatrick Mooney 	uint64_t	vht_config;
215d515dd77SPatrick Mooney 	uint64_t	vht_msi;
216d515dd77SPatrick Mooney 	uint32_t	vht_comp_val;
217d515dd77SPatrick Mooney 	uint32_t	vht_comp_rate;
218d515dd77SPatrick Mooney 	int64_t		vht_time_target;
219d515dd77SPatrick Mooney };
220d515dd77SPatrick Mooney 
221d515dd77SPatrick Mooney struct vdi_hpet_v1 {
222d515dd77SPatrick Mooney 	uint64_t	vh_config;
223d515dd77SPatrick Mooney 	uint64_t	vh_isr;
224d515dd77SPatrick Mooney 	uint32_t	vh_count_base;
225d515dd77SPatrick Mooney 	int64_t		vh_time_base;
226d515dd77SPatrick Mooney 
227d515dd77SPatrick Mooney 	struct vdi_hpet_timer_v1	vh_timers[8];
228d515dd77SPatrick Mooney };
229d515dd77SPatrick Mooney 
230d515dd77SPatrick Mooney /* VDC_PM_TIMER: */
231d515dd77SPatrick Mooney 
232d515dd77SPatrick Mooney struct vdi_pm_timer_v1 {
233d515dd77SPatrick Mooney 	int64_t		vpt_time_base;
234d515dd77SPatrick Mooney 	/*
235d515dd77SPatrick Mooney 	 * Since the PM-timer IO port registration can be set by a dedicated
236d515dd77SPatrick Mooney 	 * ioctl today, it is considered a read-only field in the vmm data
237d515dd77SPatrick Mooney 	 * interface and its contents will be ignored when writing state data to
238d515dd77SPatrick Mooney 	 * the timer.
239d515dd77SPatrick Mooney 	 */
240d515dd77SPatrick Mooney 	uint16_t	vpt_ioport;
241d515dd77SPatrick Mooney };
242d515dd77SPatrick Mooney 
243d515dd77SPatrick Mooney /* VDC_RTC: */
244d515dd77SPatrick Mooney 
245a1d41cf9SPatrick Mooney struct vdi_rtc_v2 {
246a1d41cf9SPatrick Mooney 	int64_t		vr_base_clock;
247a1d41cf9SPatrick Mooney 	int64_t		vr_last_period;
248d515dd77SPatrick Mooney 	uint8_t		vr_content[128];
249d515dd77SPatrick Mooney 	uint8_t		vr_addr;
250d515dd77SPatrick Mooney };
251d515dd77SPatrick Mooney 
252717646f7SJordan Paige Hendricks /* VDC_VMM_TIME: */
253717646f7SJordan Paige Hendricks 
254717646f7SJordan Paige Hendricks /*
255717646f7SJordan Paige Hendricks  * Interface for modifying time-related data of a guest, allowing the guest's
256717646f7SJordan Paige Hendricks  * TSC and device timers to continue working across inter-machine live
257717646f7SJordan Paige Hendricks  * migrations.
258717646f7SJordan Paige Hendricks  *
259717646f7SJordan Paige Hendricks  * Reads of this data will populate all fields, including:
260717646f7SJordan Paige Hendricks  * - current guest TSC (a calculated value)
261717646f7SJordan Paige Hendricks  * - guest TSC frequency
262717646f7SJordan Paige Hendricks  * - guest boot_time, which tracks the offset of the guest boot based on host
263717646f7SJordan Paige Hendricks  *   hrtime
264717646f7SJordan Paige Hendricks  * - current host hrtime and wall clock time (hrestime) at the time of read
265717646f7SJordan Paige Hendricks  *
266717646f7SJordan Paige Hendricks  * Callers writing this data may want to make adjustments to the guest TSC based
267717646f7SJordan Paige Hendricks  * on the time between read and write, such as in the case of a migration.
268717646f7SJordan Paige Hendricks  * For migrations between machines, the boot_hrtime must also be updated based
269717646f7SJordan Paige Hendricks  * on the hrtime of the target system. Callers should populate the host time
270717646f7SJordan Paige Hendricks  * fields for the host the write is performed on. These fields are used by the
271717646f7SJordan Paige Hendricks  * write interface to make additional adjustments to the guest fields to account
272717646f7SJordan Paige Hendricks  * for latency between the userspace adjustment and kernel receipt of those
273717646f7SJordan Paige Hendricks  * values.
274717646f7SJordan Paige Hendricks  */
275717646f7SJordan Paige Hendricks struct vdi_time_info_v1 {
276717646f7SJordan Paige Hendricks 	/* guest-related fields */
277717646f7SJordan Paige Hendricks 	uint64_t	vt_guest_freq;	/* guest TSC frequency (hz) */
278717646f7SJordan Paige Hendricks 	uint64_t	vt_guest_tsc;	/* current guest TSC */
279717646f7SJordan Paige Hendricks 	int64_t		vt_boot_hrtime; /* guest boot_hrtime */
280717646f7SJordan Paige Hendricks 
281717646f7SJordan Paige Hendricks 	/* host time fields */
282717646f7SJordan Paige Hendricks 	int64_t		vt_hrtime;	/* host hrtime (ns) */
283717646f7SJordan Paige Hendricks 	uint64_t	vt_hres_sec;	/* host hrestime (sec) */
284717646f7SJordan Paige Hendricks 	uint64_t	vt_hres_ns;	/* host hrestime (ns) */
285717646f7SJordan Paige Hendricks };
286717646f7SJordan Paige Hendricks 
287d515dd77SPatrick Mooney #endif /* _VMM_DATA_H_ */
288