1*5d9d9091SRichard Lowe/* 2*5d9d9091SRichard Lowe * CDDL HEADER START 3*5d9d9091SRichard Lowe * 4*5d9d9091SRichard Lowe * The contents of this file are subject to the terms of the 5*5d9d9091SRichard Lowe * Common Development and Distribution License (the "License"). 6*5d9d9091SRichard Lowe * You may not use this file except in compliance with the License. 7*5d9d9091SRichard Lowe * 8*5d9d9091SRichard Lowe * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*5d9d9091SRichard Lowe * or http://www.opensolaris.org/os/licensing. 10*5d9d9091SRichard Lowe * See the License for the specific language governing permissions 11*5d9d9091SRichard Lowe * and limitations under the License. 12*5d9d9091SRichard Lowe * 13*5d9d9091SRichard Lowe * When distributing Covered Code, include this CDDL HEADER in each 14*5d9d9091SRichard Lowe * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*5d9d9091SRichard Lowe * If applicable, add the following below this CDDL HEADER, with the 16*5d9d9091SRichard Lowe * fields enclosed by brackets "[]" replaced with your own identifying 17*5d9d9091SRichard Lowe * information: Portions Copyright [yyyy] [name of copyright owner] 18*5d9d9091SRichard Lowe * 19*5d9d9091SRichard Lowe * CDDL HEADER END 20*5d9d9091SRichard Lowe */ 21*5d9d9091SRichard Lowe 22*5d9d9091SRichard Lowe/* 23*5d9d9091SRichard Lowe * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24*5d9d9091SRichard Lowe * Use is subject to license terms. 25*5d9d9091SRichard Lowe */ 26*5d9d9091SRichard Lowe 27*5d9d9091SRichard Lowe/* 28*5d9d9091SRichard Lowe * Copyright (c) 2009, Intel Corporation 29*5d9d9091SRichard Lowe * All rights reserved. 30*5d9d9091SRichard Lowe */ 31*5d9d9091SRichard Lowe 32*5d9d9091SRichard Lowe/* 33*5d9d9091SRichard Lowe * Portions Copyright 2009 Advanced Micro Devices, Inc. 34*5d9d9091SRichard Lowe */ 35*5d9d9091SRichard Lowe 36*5d9d9091SRichard Lowe/* 37*5d9d9091SRichard Lowe * Assembler support routines to getcpuid information used to set 38*5d9d9091SRichard Lowe * cache size information. Cache information used by memset, strcpy, etc.. 39*5d9d9091SRichard Lowe */ 40*5d9d9091SRichard Lowe 41*5d9d9091SRichard Lowe#include <sys/asm_linkage.h> 42*5d9d9091SRichard Lowe#include "proc64_id.h" 43*5d9d9091SRichard Lowe 44*5d9d9091SRichard Lowe .global .memops_method 45*5d9d9091SRichard Lowe .global .amd64cache1, .amd64cache1half, .amd64cache2, .amd64cache2half 46*5d9d9091SRichard Lowe .global .largest_level_cache_size 47*5d9d9091SRichard Lowe 48*5d9d9091SRichard Lowe 49*5d9d9091SRichard Lowe/* 50*5d9d9091SRichard Lowe * Defaults for Core 2 Duo and AMD's SledgeHammer 51*5d9d9091SRichard Lowe */ 52*5d9d9091SRichard Lowe .data 53*5d9d9091SRichard Lowe .balign 8 54*5d9d9091SRichard Lowe.memops_method: 55*5d9d9091SRichard Lowe .int NO_SSE 56*5d9d9091SRichard Lowe 57*5d9d9091SRichard Lowe .balign 8 58*5d9d9091SRichard Lowe.amd64cache1: .quad AMD_DFLT_L1_CACHE_SIZE 59*5d9d9091SRichard Lowe.amd64cache1half: .quad AMD_DFLT_L1_CACHE_SIZE/2 60*5d9d9091SRichard Lowe.amd64cache2: .quad AMD_DFLT_L2_CACHE_SIZE 61*5d9d9091SRichard Lowe.amd64cache2half: .quad AMD_DFLT_L2_CACHE_SIZE/2 62*5d9d9091SRichard Lowe.largest_level_cache_size: 63*5d9d9091SRichard Lowe .int AMD_DFLT_L2_CACHE_SIZE 64*5d9d9091SRichard Lowe 65*5d9d9091SRichard Lowe/* 66*5d9d9091SRichard Lowe * Get cpuid data. 67*5d9d9091SRichard Lowe * (void)__libc_get_cpuid(int cpuid_function, void *out_reg, int cache_index ) 68*5d9d9091SRichard Lowe */ 69*5d9d9091SRichard Lowe .text 70*5d9d9091SRichard Lowe 71*5d9d9091SRichard Lowe ENTRY(__libc_get_cpuid) 72*5d9d9091SRichard Lowe # rdi = cpuid function, rsi = out_reg addr, rdx = cache index(fn 4) 73*5d9d9091SRichard Lowe push %rbx 74*5d9d9091SRichard Lowe mov %edx,%ecx 75*5d9d9091SRichard Lowe mov %edi,%eax 76*5d9d9091SRichard Lowe cpuid 77*5d9d9091SRichard Lowe mov %eax,(%rsi) 78*5d9d9091SRichard Lowe mov %ebx,0x4(%rsi) 79*5d9d9091SRichard Lowe mov %ecx,0x8(%rsi) 80*5d9d9091SRichard Lowe mov %edx,0xc(%rsi) 81*5d9d9091SRichard Lowe pop %rbx 82*5d9d9091SRichard Lowe ret 83*5d9d9091SRichard Lowe SET_SIZE(__libc_get_cpuid) 84*5d9d9091SRichard Lowe 85*5d9d9091SRichard Lowe/* 86*5d9d9091SRichard Lowe * Set memops SSE level to use. 87*5d9d9091SRichard Lowe * void __intel_set_memops_method(long sse_level); 88*5d9d9091SRichard Lowe */ 89*5d9d9091SRichard Lowe ENTRY(__intel_set_memops_method) 90*5d9d9091SRichard Lowe mov %edi,.memops_method(%rip) 91*5d9d9091SRichard Lowe ret 92*5d9d9091SRichard Lowe SET_SIZE(__intel_set_memops_method) 93*5d9d9091SRichard Lowe 94*5d9d9091SRichard Lowe/* 95*5d9d9091SRichard Lowe * Set cache info global variables used by various libc primitives. 96*5d9d9091SRichard Lowe * __set_cache_sizes(long l1_cache_size, long l2_cache_size, 97*5d9d9091SRichard Lowe * long largest_level_cache); 98*5d9d9091SRichard Lowe */ 99*5d9d9091SRichard Lowe ENTRY(__set_cache_sizes) 100*5d9d9091SRichard Lowe # rdi = l1_cache_size, rsi = l2_cache_size, rdx = largest_level_cache 101*5d9d9091SRichard Lowe 102*5d9d9091SRichard Lowe mov %rdi,.amd64cache1(%rip) 103*5d9d9091SRichard Lowe shr $1, %rdi 104*5d9d9091SRichard Lowe mov %rdi,.amd64cache1half(%rip) 105*5d9d9091SRichard Lowe 106*5d9d9091SRichard Lowe mov %rsi,.amd64cache2(%rip) 107*5d9d9091SRichard Lowe shr $1, %rsi 108*5d9d9091SRichard Lowe mov %rsi,.amd64cache2half(%rip) 109*5d9d9091SRichard Lowe 110*5d9d9091SRichard Lowe mov %rdx,.largest_level_cache_size(%rip) 111*5d9d9091SRichard Lowe ret 112*5d9d9091SRichard Lowe SET_SIZE(__set_cache_sizes) 113