1*5c4a5fe1SAndy Fiddaman /*-
2*5c4a5fe1SAndy Fiddaman * SPDX-License-Identifier: BSD-2-Clause
3*5c4a5fe1SAndy Fiddaman *
4*5c4a5fe1SAndy Fiddaman * Copyright (c) 2013 Hudson River Trading LLC
5*5c4a5fe1SAndy Fiddaman * Written by: John H. Baldwin <jhb@FreeBSD.org>
6*5c4a5fe1SAndy Fiddaman * All rights reserved.
7*5c4a5fe1SAndy Fiddaman *
8*5c4a5fe1SAndy Fiddaman * Redistribution and use in source and binary forms, with or without
9*5c4a5fe1SAndy Fiddaman * modification, are permitted provided that the following conditions
10*5c4a5fe1SAndy Fiddaman * are met:
11*5c4a5fe1SAndy Fiddaman * 1. Redistributions of source code must retain the above copyright
12*5c4a5fe1SAndy Fiddaman * notice, this list of conditions and the following disclaimer.
13*5c4a5fe1SAndy Fiddaman * 2. Redistributions in binary form must reproduce the above copyright
14*5c4a5fe1SAndy Fiddaman * notice, this list of conditions and the following disclaimer in the
15*5c4a5fe1SAndy Fiddaman * documentation and/or other materials provided with the distribution.
16*5c4a5fe1SAndy Fiddaman *
17*5c4a5fe1SAndy Fiddaman * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18*5c4a5fe1SAndy Fiddaman * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19*5c4a5fe1SAndy Fiddaman * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20*5c4a5fe1SAndy Fiddaman * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21*5c4a5fe1SAndy Fiddaman * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22*5c4a5fe1SAndy Fiddaman * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23*5c4a5fe1SAndy Fiddaman * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24*5c4a5fe1SAndy Fiddaman * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25*5c4a5fe1SAndy Fiddaman * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26*5c4a5fe1SAndy Fiddaman * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27*5c4a5fe1SAndy Fiddaman * SUCH DAMAGE.
28*5c4a5fe1SAndy Fiddaman */
29*5c4a5fe1SAndy Fiddaman /*
30*5c4a5fe1SAndy Fiddaman * Copyright 2018 Joyent, Inc.
31*5c4a5fe1SAndy Fiddaman * Copyright 2020 Oxide Computer Company
32*5c4a5fe1SAndy Fiddaman */
33*5c4a5fe1SAndy Fiddaman
34*5c4a5fe1SAndy Fiddaman
35*5c4a5fe1SAndy Fiddaman #include <sys/types.h>
36*5c4a5fe1SAndy Fiddaman #include <machine/vmm.h>
37*5c4a5fe1SAndy Fiddaman
38*5c4a5fe1SAndy Fiddaman #include <assert.h>
39*5c4a5fe1SAndy Fiddaman #include <errno.h>
40*5c4a5fe1SAndy Fiddaman #include <pthread.h>
41*5c4a5fe1SAndy Fiddaman #ifndef __FreeBSD__
42*5c4a5fe1SAndy Fiddaman #include <stdlib.h>
43*5c4a5fe1SAndy Fiddaman #endif
44*5c4a5fe1SAndy Fiddaman #include <signal.h>
45*5c4a5fe1SAndy Fiddaman #include <vmmapi.h>
46*5c4a5fe1SAndy Fiddaman
47*5c4a5fe1SAndy Fiddaman #include "acpi.h"
48*5c4a5fe1SAndy Fiddaman #include "inout.h"
49*5c4a5fe1SAndy Fiddaman #ifdef __FreeBSD__
50*5c4a5fe1SAndy Fiddaman #include "mevent.h"
51*5c4a5fe1SAndy Fiddaman #endif
52*5c4a5fe1SAndy Fiddaman #include "pci_irq.h"
53*5c4a5fe1SAndy Fiddaman #include "pci_lpc.h"
54*5c4a5fe1SAndy Fiddaman
55*5c4a5fe1SAndy Fiddaman static pthread_mutex_t pm_lock = PTHREAD_MUTEX_INITIALIZER;
56*5c4a5fe1SAndy Fiddaman #ifdef __FreeBSD__
57*5c4a5fe1SAndy Fiddaman static struct mevent *power_button;
58*5c4a5fe1SAndy Fiddaman static sig_t old_power_handler;
59*5c4a5fe1SAndy Fiddaman #else
60*5c4a5fe1SAndy Fiddaman struct vmctx *pwr_ctx;
61*5c4a5fe1SAndy Fiddaman #endif
62*5c4a5fe1SAndy Fiddaman
63*5c4a5fe1SAndy Fiddaman static unsigned gpe0_active;
64*5c4a5fe1SAndy Fiddaman static unsigned gpe0_enabled;
65*5c4a5fe1SAndy Fiddaman static const unsigned gpe0_valid = (1u << GPE_VMGENC);
66*5c4a5fe1SAndy Fiddaman
67*5c4a5fe1SAndy Fiddaman /*
68*5c4a5fe1SAndy Fiddaman * Reset Control register at I/O port 0xcf9. Bit 2 forces a system
69*5c4a5fe1SAndy Fiddaman * reset when it transitions from 0 to 1. Bit 1 selects the type of
70*5c4a5fe1SAndy Fiddaman * reset to attempt: 0 selects a "soft" reset, and 1 selects a "hard"
71*5c4a5fe1SAndy Fiddaman * reset.
72*5c4a5fe1SAndy Fiddaman */
73*5c4a5fe1SAndy Fiddaman static int
reset_handler(struct vmctx * ctx __unused,int in,int port __unused,int bytes,uint32_t * eax,void * arg __unused)74*5c4a5fe1SAndy Fiddaman reset_handler(struct vmctx *ctx __unused, int in,
75*5c4a5fe1SAndy Fiddaman int port __unused, int bytes, uint32_t *eax, void *arg __unused)
76*5c4a5fe1SAndy Fiddaman {
77*5c4a5fe1SAndy Fiddaman int error;
78*5c4a5fe1SAndy Fiddaman
79*5c4a5fe1SAndy Fiddaman static uint8_t reset_control;
80*5c4a5fe1SAndy Fiddaman
81*5c4a5fe1SAndy Fiddaman if (bytes != 1)
82*5c4a5fe1SAndy Fiddaman return (-1);
83*5c4a5fe1SAndy Fiddaman if (in)
84*5c4a5fe1SAndy Fiddaman *eax = reset_control;
85*5c4a5fe1SAndy Fiddaman else {
86*5c4a5fe1SAndy Fiddaman reset_control = *eax;
87*5c4a5fe1SAndy Fiddaman
88*5c4a5fe1SAndy Fiddaman /* Treat hard and soft resets the same. */
89*5c4a5fe1SAndy Fiddaman if (reset_control & 0x4) {
90*5c4a5fe1SAndy Fiddaman error = vm_suspend(ctx, VM_SUSPEND_RESET);
91*5c4a5fe1SAndy Fiddaman assert(error == 0 || errno == EALREADY);
92*5c4a5fe1SAndy Fiddaman }
93*5c4a5fe1SAndy Fiddaman }
94*5c4a5fe1SAndy Fiddaman return (0);
95*5c4a5fe1SAndy Fiddaman }
96*5c4a5fe1SAndy Fiddaman INOUT_PORT(reset_reg, 0xCF9, IOPORT_F_INOUT, reset_handler);
97*5c4a5fe1SAndy Fiddaman
98*5c4a5fe1SAndy Fiddaman /*
99*5c4a5fe1SAndy Fiddaman * ACPI's SCI is a level-triggered interrupt.
100*5c4a5fe1SAndy Fiddaman */
101*5c4a5fe1SAndy Fiddaman static int sci_active;
102*5c4a5fe1SAndy Fiddaman
103*5c4a5fe1SAndy Fiddaman static void
sci_assert(struct vmctx * ctx)104*5c4a5fe1SAndy Fiddaman sci_assert(struct vmctx *ctx)
105*5c4a5fe1SAndy Fiddaman {
106*5c4a5fe1SAndy Fiddaman
107*5c4a5fe1SAndy Fiddaman if (sci_active)
108*5c4a5fe1SAndy Fiddaman return;
109*5c4a5fe1SAndy Fiddaman vm_isa_assert_irq(ctx, SCI_INT, SCI_INT);
110*5c4a5fe1SAndy Fiddaman sci_active = 1;
111*5c4a5fe1SAndy Fiddaman }
112*5c4a5fe1SAndy Fiddaman
113*5c4a5fe1SAndy Fiddaman static void
sci_deassert(struct vmctx * ctx)114*5c4a5fe1SAndy Fiddaman sci_deassert(struct vmctx *ctx)
115*5c4a5fe1SAndy Fiddaman {
116*5c4a5fe1SAndy Fiddaman
117*5c4a5fe1SAndy Fiddaman if (!sci_active)
118*5c4a5fe1SAndy Fiddaman return;
119*5c4a5fe1SAndy Fiddaman vm_isa_deassert_irq(ctx, SCI_INT, SCI_INT);
120*5c4a5fe1SAndy Fiddaman sci_active = 0;
121*5c4a5fe1SAndy Fiddaman }
122*5c4a5fe1SAndy Fiddaman
123*5c4a5fe1SAndy Fiddaman /*
124*5c4a5fe1SAndy Fiddaman * Power Management 1 Event Registers
125*5c4a5fe1SAndy Fiddaman *
126*5c4a5fe1SAndy Fiddaman * The only power management event supported is a power button upon
127*5c4a5fe1SAndy Fiddaman * receiving SIGTERM.
128*5c4a5fe1SAndy Fiddaman */
129*5c4a5fe1SAndy Fiddaman static uint16_t pm1_enable, pm1_status;
130*5c4a5fe1SAndy Fiddaman
131*5c4a5fe1SAndy Fiddaman #define PM1_TMR_STS 0x0001
132*5c4a5fe1SAndy Fiddaman #define PM1_BM_STS 0x0010
133*5c4a5fe1SAndy Fiddaman #define PM1_GBL_STS 0x0020
134*5c4a5fe1SAndy Fiddaman #define PM1_PWRBTN_STS 0x0100
135*5c4a5fe1SAndy Fiddaman #define PM1_SLPBTN_STS 0x0200
136*5c4a5fe1SAndy Fiddaman #define PM1_RTC_STS 0x0400
137*5c4a5fe1SAndy Fiddaman #define PM1_WAK_STS 0x8000
138*5c4a5fe1SAndy Fiddaman
139*5c4a5fe1SAndy Fiddaman #define PM1_TMR_EN 0x0001
140*5c4a5fe1SAndy Fiddaman #define PM1_GBL_EN 0x0020
141*5c4a5fe1SAndy Fiddaman #define PM1_PWRBTN_EN 0x0100
142*5c4a5fe1SAndy Fiddaman #define PM1_SLPBTN_EN 0x0200
143*5c4a5fe1SAndy Fiddaman #define PM1_RTC_EN 0x0400
144*5c4a5fe1SAndy Fiddaman
145*5c4a5fe1SAndy Fiddaman static void
sci_update(struct vmctx * ctx)146*5c4a5fe1SAndy Fiddaman sci_update(struct vmctx *ctx)
147*5c4a5fe1SAndy Fiddaman {
148*5c4a5fe1SAndy Fiddaman int need_sci;
149*5c4a5fe1SAndy Fiddaman
150*5c4a5fe1SAndy Fiddaman /* See if the SCI should be active or not. */
151*5c4a5fe1SAndy Fiddaman need_sci = 0;
152*5c4a5fe1SAndy Fiddaman if ((pm1_enable & PM1_TMR_EN) && (pm1_status & PM1_TMR_STS))
153*5c4a5fe1SAndy Fiddaman need_sci = 1;
154*5c4a5fe1SAndy Fiddaman if ((pm1_enable & PM1_GBL_EN) && (pm1_status & PM1_GBL_STS))
155*5c4a5fe1SAndy Fiddaman need_sci = 1;
156*5c4a5fe1SAndy Fiddaman if ((pm1_enable & PM1_PWRBTN_EN) && (pm1_status & PM1_PWRBTN_STS))
157*5c4a5fe1SAndy Fiddaman need_sci = 1;
158*5c4a5fe1SAndy Fiddaman if ((pm1_enable & PM1_SLPBTN_EN) && (pm1_status & PM1_SLPBTN_STS))
159*5c4a5fe1SAndy Fiddaman need_sci = 1;
160*5c4a5fe1SAndy Fiddaman if ((pm1_enable & PM1_RTC_EN) && (pm1_status & PM1_RTC_STS))
161*5c4a5fe1SAndy Fiddaman need_sci = 1;
162*5c4a5fe1SAndy Fiddaman if ((gpe0_enabled & gpe0_active) != 0)
163*5c4a5fe1SAndy Fiddaman need_sci = 1;
164*5c4a5fe1SAndy Fiddaman
165*5c4a5fe1SAndy Fiddaman if (need_sci)
166*5c4a5fe1SAndy Fiddaman sci_assert(ctx);
167*5c4a5fe1SAndy Fiddaman else
168*5c4a5fe1SAndy Fiddaman sci_deassert(ctx);
169*5c4a5fe1SAndy Fiddaman }
170*5c4a5fe1SAndy Fiddaman
171*5c4a5fe1SAndy Fiddaman static int
pm1_status_handler(struct vmctx * ctx,int in,int port __unused,int bytes,uint32_t * eax,void * arg __unused)172*5c4a5fe1SAndy Fiddaman pm1_status_handler(struct vmctx *ctx, int in,
173*5c4a5fe1SAndy Fiddaman int port __unused, int bytes, uint32_t *eax, void *arg __unused)
174*5c4a5fe1SAndy Fiddaman {
175*5c4a5fe1SAndy Fiddaman
176*5c4a5fe1SAndy Fiddaman if (bytes != 2)
177*5c4a5fe1SAndy Fiddaman return (-1);
178*5c4a5fe1SAndy Fiddaman
179*5c4a5fe1SAndy Fiddaman pthread_mutex_lock(&pm_lock);
180*5c4a5fe1SAndy Fiddaman if (in)
181*5c4a5fe1SAndy Fiddaman *eax = pm1_status;
182*5c4a5fe1SAndy Fiddaman else {
183*5c4a5fe1SAndy Fiddaman /*
184*5c4a5fe1SAndy Fiddaman * Writes are only permitted to clear certain bits by
185*5c4a5fe1SAndy Fiddaman * writing 1 to those flags.
186*5c4a5fe1SAndy Fiddaman */
187*5c4a5fe1SAndy Fiddaman pm1_status &= ~(*eax & (PM1_WAK_STS | PM1_RTC_STS |
188*5c4a5fe1SAndy Fiddaman PM1_SLPBTN_STS | PM1_PWRBTN_STS | PM1_BM_STS));
189*5c4a5fe1SAndy Fiddaman sci_update(ctx);
190*5c4a5fe1SAndy Fiddaman }
191*5c4a5fe1SAndy Fiddaman pthread_mutex_unlock(&pm_lock);
192*5c4a5fe1SAndy Fiddaman return (0);
193*5c4a5fe1SAndy Fiddaman }
194*5c4a5fe1SAndy Fiddaman
195*5c4a5fe1SAndy Fiddaman static int
pm1_enable_handler(struct vmctx * ctx,int in,int port __unused,int bytes,uint32_t * eax,void * arg __unused)196*5c4a5fe1SAndy Fiddaman pm1_enable_handler(struct vmctx *ctx, int in,
197*5c4a5fe1SAndy Fiddaman int port __unused, int bytes, uint32_t *eax, void *arg __unused)
198*5c4a5fe1SAndy Fiddaman {
199*5c4a5fe1SAndy Fiddaman
200*5c4a5fe1SAndy Fiddaman if (bytes != 2)
201*5c4a5fe1SAndy Fiddaman return (-1);
202*5c4a5fe1SAndy Fiddaman
203*5c4a5fe1SAndy Fiddaman pthread_mutex_lock(&pm_lock);
204*5c4a5fe1SAndy Fiddaman if (in)
205*5c4a5fe1SAndy Fiddaman *eax = pm1_enable;
206*5c4a5fe1SAndy Fiddaman else {
207*5c4a5fe1SAndy Fiddaman /*
208*5c4a5fe1SAndy Fiddaman * Only permit certain bits to be set. We never use
209*5c4a5fe1SAndy Fiddaman * the global lock, but ACPI-CA whines profusely if it
210*5c4a5fe1SAndy Fiddaman * can't set GBL_EN.
211*5c4a5fe1SAndy Fiddaman */
212*5c4a5fe1SAndy Fiddaman pm1_enable = *eax & (PM1_RTC_EN | PM1_PWRBTN_EN | PM1_GBL_EN);
213*5c4a5fe1SAndy Fiddaman sci_update(ctx);
214*5c4a5fe1SAndy Fiddaman }
215*5c4a5fe1SAndy Fiddaman pthread_mutex_unlock(&pm_lock);
216*5c4a5fe1SAndy Fiddaman return (0);
217*5c4a5fe1SAndy Fiddaman }
218*5c4a5fe1SAndy Fiddaman INOUT_PORT(pm1_status, PM1A_EVT_ADDR, IOPORT_F_INOUT, pm1_status_handler);
219*5c4a5fe1SAndy Fiddaman INOUT_PORT(pm1_enable, PM1A_EVT_ADDR + 2, IOPORT_F_INOUT, pm1_enable_handler);
220*5c4a5fe1SAndy Fiddaman
221*5c4a5fe1SAndy Fiddaman #ifdef __FreeBSD__
222*5c4a5fe1SAndy Fiddaman static void
power_button_handler(int signal __unused,enum ev_type type __unused,void * arg)223*5c4a5fe1SAndy Fiddaman power_button_handler(int signal __unused, enum ev_type type __unused, void *arg)
224*5c4a5fe1SAndy Fiddaman {
225*5c4a5fe1SAndy Fiddaman struct vmctx *ctx;
226*5c4a5fe1SAndy Fiddaman
227*5c4a5fe1SAndy Fiddaman ctx = arg;
228*5c4a5fe1SAndy Fiddaman pthread_mutex_lock(&pm_lock);
229*5c4a5fe1SAndy Fiddaman if (!(pm1_status & PM1_PWRBTN_STS)) {
230*5c4a5fe1SAndy Fiddaman pm1_status |= PM1_PWRBTN_STS;
231*5c4a5fe1SAndy Fiddaman sci_update(ctx);
232*5c4a5fe1SAndy Fiddaman }
233*5c4a5fe1SAndy Fiddaman pthread_mutex_unlock(&pm_lock);
234*5c4a5fe1SAndy Fiddaman }
235*5c4a5fe1SAndy Fiddaman
236*5c4a5fe1SAndy Fiddaman #else
237*5c4a5fe1SAndy Fiddaman /*
238*5c4a5fe1SAndy Fiddaman * Initiate graceful power off.
239*5c4a5fe1SAndy Fiddaman */
240*5c4a5fe1SAndy Fiddaman /*ARGSUSED*/
241*5c4a5fe1SAndy Fiddaman static void
power_button_handler(int signal,siginfo_t * type,void * cp)242*5c4a5fe1SAndy Fiddaman power_button_handler(int signal, siginfo_t *type, void *cp)
243*5c4a5fe1SAndy Fiddaman {
244*5c4a5fe1SAndy Fiddaman /*
245*5c4a5fe1SAndy Fiddaman * In theory, taking the 'pm_lock' mutex from within this signal
246*5c4a5fe1SAndy Fiddaman * handler could lead to deadlock if the main thread already held this
247*5c4a5fe1SAndy Fiddaman * mutex. In reality, this mutex is local to this file and all of the
248*5c4a5fe1SAndy Fiddaman * other usage in this file only occurs in functions which are FreeBSD
249*5c4a5fe1SAndy Fiddaman * specific (and thus currently not used). Thus, for consistency with
250*5c4a5fe1SAndy Fiddaman * the other code in this file, we take the mutex, but in the future,
251*5c4a5fe1SAndy Fiddaman * if these other functions are ever enabled for use on non-FreeBSD
252*5c4a5fe1SAndy Fiddaman * systems and these functions could be called directly by a thread
253*5c4a5fe1SAndy Fiddaman * (which would then hold the mutex), then we need to revisit the use
254*5c4a5fe1SAndy Fiddaman * of this mutex in this signal handler.
255*5c4a5fe1SAndy Fiddaman */
256*5c4a5fe1SAndy Fiddaman pthread_mutex_lock(&pm_lock);
257*5c4a5fe1SAndy Fiddaman if (!(pm1_status & PM1_PWRBTN_STS)) {
258*5c4a5fe1SAndy Fiddaman pm1_status |= PM1_PWRBTN_STS;
259*5c4a5fe1SAndy Fiddaman sci_update(pwr_ctx);
260*5c4a5fe1SAndy Fiddaman }
261*5c4a5fe1SAndy Fiddaman pthread_mutex_unlock(&pm_lock);
262*5c4a5fe1SAndy Fiddaman }
263*5c4a5fe1SAndy Fiddaman #endif
264*5c4a5fe1SAndy Fiddaman
265*5c4a5fe1SAndy Fiddaman /*
266*5c4a5fe1SAndy Fiddaman * Power Management 1 Control Register
267*5c4a5fe1SAndy Fiddaman *
268*5c4a5fe1SAndy Fiddaman * This is mostly unimplemented except that we wish to handle writes that
269*5c4a5fe1SAndy Fiddaman * set SPL_EN to handle S5 (soft power off).
270*5c4a5fe1SAndy Fiddaman */
271*5c4a5fe1SAndy Fiddaman static uint16_t pm1_control;
272*5c4a5fe1SAndy Fiddaman
273*5c4a5fe1SAndy Fiddaman #define PM1_SCI_EN 0x0001
274*5c4a5fe1SAndy Fiddaman #define PM1_SLP_TYP 0x1c00
275*5c4a5fe1SAndy Fiddaman #define PM1_SLP_EN 0x2000
276*5c4a5fe1SAndy Fiddaman #define PM1_ALWAYS_ZERO 0xc003
277*5c4a5fe1SAndy Fiddaman
278*5c4a5fe1SAndy Fiddaman static int
pm1_control_handler(struct vmctx * ctx,int in,int port __unused,int bytes,uint32_t * eax,void * arg __unused)279*5c4a5fe1SAndy Fiddaman pm1_control_handler(struct vmctx *ctx, int in,
280*5c4a5fe1SAndy Fiddaman int port __unused, int bytes, uint32_t *eax, void *arg __unused)
281*5c4a5fe1SAndy Fiddaman {
282*5c4a5fe1SAndy Fiddaman int error;
283*5c4a5fe1SAndy Fiddaman
284*5c4a5fe1SAndy Fiddaman if (bytes != 2)
285*5c4a5fe1SAndy Fiddaman return (-1);
286*5c4a5fe1SAndy Fiddaman if (in)
287*5c4a5fe1SAndy Fiddaman *eax = pm1_control;
288*5c4a5fe1SAndy Fiddaman else {
289*5c4a5fe1SAndy Fiddaman /*
290*5c4a5fe1SAndy Fiddaman * Various bits are write-only or reserved, so force them
291*5c4a5fe1SAndy Fiddaman * to zero in pm1_control. Always preserve SCI_EN as OSPM
292*5c4a5fe1SAndy Fiddaman * can never change it.
293*5c4a5fe1SAndy Fiddaman */
294*5c4a5fe1SAndy Fiddaman pm1_control = (pm1_control & PM1_SCI_EN) |
295*5c4a5fe1SAndy Fiddaman (*eax & ~(PM1_SLP_EN | PM1_ALWAYS_ZERO));
296*5c4a5fe1SAndy Fiddaman
297*5c4a5fe1SAndy Fiddaman /*
298*5c4a5fe1SAndy Fiddaman * If SLP_EN is set, check for S5. Bhyve's _S5_ method
299*5c4a5fe1SAndy Fiddaman * says that '5' should be stored in SLP_TYP for S5.
300*5c4a5fe1SAndy Fiddaman */
301*5c4a5fe1SAndy Fiddaman if (*eax & PM1_SLP_EN) {
302*5c4a5fe1SAndy Fiddaman if ((pm1_control & PM1_SLP_TYP) >> 10 == 5) {
303*5c4a5fe1SAndy Fiddaman error = vm_suspend(ctx, VM_SUSPEND_POWEROFF);
304*5c4a5fe1SAndy Fiddaman assert(error == 0 || errno == EALREADY);
305*5c4a5fe1SAndy Fiddaman }
306*5c4a5fe1SAndy Fiddaman }
307*5c4a5fe1SAndy Fiddaman }
308*5c4a5fe1SAndy Fiddaman return (0);
309*5c4a5fe1SAndy Fiddaman }
310*5c4a5fe1SAndy Fiddaman INOUT_PORT(pm1_control, PM1A_CNT_ADDR, IOPORT_F_INOUT, pm1_control_handler);
311*5c4a5fe1SAndy Fiddaman #ifdef __FreeBSD__
312*5c4a5fe1SAndy Fiddaman SYSRES_IO(PM1A_EVT_ADDR, 8);
313*5c4a5fe1SAndy Fiddaman #endif
314*5c4a5fe1SAndy Fiddaman
315*5c4a5fe1SAndy Fiddaman void
acpi_raise_gpe(struct vmctx * ctx,unsigned bit)316*5c4a5fe1SAndy Fiddaman acpi_raise_gpe(struct vmctx *ctx, unsigned bit)
317*5c4a5fe1SAndy Fiddaman {
318*5c4a5fe1SAndy Fiddaman unsigned mask;
319*5c4a5fe1SAndy Fiddaman
320*5c4a5fe1SAndy Fiddaman assert(bit < (IO_GPE0_LEN * (8 / 2)));
321*5c4a5fe1SAndy Fiddaman mask = (1u << bit);
322*5c4a5fe1SAndy Fiddaman assert((mask & ~gpe0_valid) == 0);
323*5c4a5fe1SAndy Fiddaman
324*5c4a5fe1SAndy Fiddaman pthread_mutex_lock(&pm_lock);
325*5c4a5fe1SAndy Fiddaman gpe0_active |= mask;
326*5c4a5fe1SAndy Fiddaman sci_update(ctx);
327*5c4a5fe1SAndy Fiddaman pthread_mutex_unlock(&pm_lock);
328*5c4a5fe1SAndy Fiddaman }
329*5c4a5fe1SAndy Fiddaman
330*5c4a5fe1SAndy Fiddaman static int
gpe0_sts(struct vmctx * ctx,int in,int port __unused,int bytes,uint32_t * eax,void * arg __unused)331*5c4a5fe1SAndy Fiddaman gpe0_sts(struct vmctx *ctx, int in, int port __unused,
332*5c4a5fe1SAndy Fiddaman int bytes, uint32_t *eax, void *arg __unused)
333*5c4a5fe1SAndy Fiddaman {
334*5c4a5fe1SAndy Fiddaman /*
335*5c4a5fe1SAndy Fiddaman * ACPI 6.2 specifies the GPE register blocks are accessed
336*5c4a5fe1SAndy Fiddaman * byte-at-a-time.
337*5c4a5fe1SAndy Fiddaman */
338*5c4a5fe1SAndy Fiddaman if (bytes != 1)
339*5c4a5fe1SAndy Fiddaman return (-1);
340*5c4a5fe1SAndy Fiddaman
341*5c4a5fe1SAndy Fiddaman pthread_mutex_lock(&pm_lock);
342*5c4a5fe1SAndy Fiddaman if (in)
343*5c4a5fe1SAndy Fiddaman *eax = gpe0_active;
344*5c4a5fe1SAndy Fiddaman else {
345*5c4a5fe1SAndy Fiddaman /* W1C */
346*5c4a5fe1SAndy Fiddaman gpe0_active &= ~(*eax & gpe0_valid);
347*5c4a5fe1SAndy Fiddaman sci_update(ctx);
348*5c4a5fe1SAndy Fiddaman }
349*5c4a5fe1SAndy Fiddaman pthread_mutex_unlock(&pm_lock);
350*5c4a5fe1SAndy Fiddaman return (0);
351*5c4a5fe1SAndy Fiddaman }
352*5c4a5fe1SAndy Fiddaman INOUT_PORT(gpe0_sts, IO_GPE0_STS, IOPORT_F_INOUT, gpe0_sts);
353*5c4a5fe1SAndy Fiddaman
354*5c4a5fe1SAndy Fiddaman static int
gpe0_en(struct vmctx * ctx,int in,int port __unused,int bytes,uint32_t * eax,void * arg __unused)355*5c4a5fe1SAndy Fiddaman gpe0_en(struct vmctx *ctx, int in, int port __unused,
356*5c4a5fe1SAndy Fiddaman int bytes, uint32_t *eax, void *arg __unused)
357*5c4a5fe1SAndy Fiddaman {
358*5c4a5fe1SAndy Fiddaman if (bytes != 1)
359*5c4a5fe1SAndy Fiddaman return (-1);
360*5c4a5fe1SAndy Fiddaman
361*5c4a5fe1SAndy Fiddaman pthread_mutex_lock(&pm_lock);
362*5c4a5fe1SAndy Fiddaman if (in)
363*5c4a5fe1SAndy Fiddaman *eax = gpe0_enabled;
364*5c4a5fe1SAndy Fiddaman else {
365*5c4a5fe1SAndy Fiddaman gpe0_enabled = (*eax & gpe0_valid);
366*5c4a5fe1SAndy Fiddaman sci_update(ctx);
367*5c4a5fe1SAndy Fiddaman }
368*5c4a5fe1SAndy Fiddaman pthread_mutex_unlock(&pm_lock);
369*5c4a5fe1SAndy Fiddaman return (0);
370*5c4a5fe1SAndy Fiddaman }
371*5c4a5fe1SAndy Fiddaman INOUT_PORT(gpe0_en, IO_GPE0_EN, IOPORT_F_INOUT, gpe0_en);
372*5c4a5fe1SAndy Fiddaman
373*5c4a5fe1SAndy Fiddaman /*
374*5c4a5fe1SAndy Fiddaman * ACPI SMI Command Register
375*5c4a5fe1SAndy Fiddaman *
376*5c4a5fe1SAndy Fiddaman * This write-only register is used to enable and disable ACPI.
377*5c4a5fe1SAndy Fiddaman */
378*5c4a5fe1SAndy Fiddaman static int
smi_cmd_handler(struct vmctx * ctx,int in,int port __unused,int bytes,uint32_t * eax,void * arg __unused)379*5c4a5fe1SAndy Fiddaman smi_cmd_handler(struct vmctx *ctx, int in, int port __unused,
380*5c4a5fe1SAndy Fiddaman int bytes, uint32_t *eax, void *arg __unused)
381*5c4a5fe1SAndy Fiddaman {
382*5c4a5fe1SAndy Fiddaman
383*5c4a5fe1SAndy Fiddaman assert(!in);
384*5c4a5fe1SAndy Fiddaman if (bytes != 1)
385*5c4a5fe1SAndy Fiddaman return (-1);
386*5c4a5fe1SAndy Fiddaman
387*5c4a5fe1SAndy Fiddaman pthread_mutex_lock(&pm_lock);
388*5c4a5fe1SAndy Fiddaman switch (*eax) {
389*5c4a5fe1SAndy Fiddaman case BHYVE_ACPI_ENABLE:
390*5c4a5fe1SAndy Fiddaman pm1_control |= PM1_SCI_EN;
391*5c4a5fe1SAndy Fiddaman #ifdef __FreeBSD__
392*5c4a5fe1SAndy Fiddaman if (power_button == NULL) {
393*5c4a5fe1SAndy Fiddaman power_button = mevent_add(SIGTERM, EVF_SIGNAL,
394*5c4a5fe1SAndy Fiddaman power_button_handler, ctx);
395*5c4a5fe1SAndy Fiddaman old_power_handler = signal(SIGTERM, SIG_IGN);
396*5c4a5fe1SAndy Fiddaman }
397*5c4a5fe1SAndy Fiddaman #endif
398*5c4a5fe1SAndy Fiddaman break;
399*5c4a5fe1SAndy Fiddaman case BHYVE_ACPI_DISABLE:
400*5c4a5fe1SAndy Fiddaman pm1_control &= ~PM1_SCI_EN;
401*5c4a5fe1SAndy Fiddaman #ifdef __FreeBSD__
402*5c4a5fe1SAndy Fiddaman if (power_button != NULL) {
403*5c4a5fe1SAndy Fiddaman mevent_delete(power_button);
404*5c4a5fe1SAndy Fiddaman power_button = NULL;
405*5c4a5fe1SAndy Fiddaman signal(SIGTERM, old_power_handler);
406*5c4a5fe1SAndy Fiddaman }
407*5c4a5fe1SAndy Fiddaman #endif
408*5c4a5fe1SAndy Fiddaman break;
409*5c4a5fe1SAndy Fiddaman }
410*5c4a5fe1SAndy Fiddaman pthread_mutex_unlock(&pm_lock);
411*5c4a5fe1SAndy Fiddaman return (0);
412*5c4a5fe1SAndy Fiddaman }
413*5c4a5fe1SAndy Fiddaman INOUT_PORT(smi_cmd, SMI_CMD, IOPORT_F_OUT, smi_cmd_handler);
414*5c4a5fe1SAndy Fiddaman #ifdef __FreeBSD__
415*5c4a5fe1SAndy Fiddaman SYSRES_IO(SMI_CMD, 1);
416*5c4a5fe1SAndy Fiddaman #endif
417*5c4a5fe1SAndy Fiddaman
418*5c4a5fe1SAndy Fiddaman void
sci_init(struct vmctx * ctx)419*5c4a5fe1SAndy Fiddaman sci_init(struct vmctx *ctx)
420*5c4a5fe1SAndy Fiddaman {
421*5c4a5fe1SAndy Fiddaman
422*5c4a5fe1SAndy Fiddaman /*
423*5c4a5fe1SAndy Fiddaman * Mark ACPI's SCI as level trigger and bump its use count
424*5c4a5fe1SAndy Fiddaman * in the PIRQ router.
425*5c4a5fe1SAndy Fiddaman */
426*5c4a5fe1SAndy Fiddaman pci_irq_use(SCI_INT);
427*5c4a5fe1SAndy Fiddaman vm_isa_set_irq_trigger(ctx, SCI_INT, LEVEL_TRIGGER);
428*5c4a5fe1SAndy Fiddaman
429*5c4a5fe1SAndy Fiddaman #ifndef __FreeBSD__
430*5c4a5fe1SAndy Fiddaman {
431*5c4a5fe1SAndy Fiddaman /*
432*5c4a5fe1SAndy Fiddaman * Install SIGTERM signal handler for graceful power off.
433*5c4a5fe1SAndy Fiddaman */
434*5c4a5fe1SAndy Fiddaman struct sigaction act;
435*5c4a5fe1SAndy Fiddaman
436*5c4a5fe1SAndy Fiddaman pwr_ctx = ctx;
437*5c4a5fe1SAndy Fiddaman act.sa_flags = 0;
438*5c4a5fe1SAndy Fiddaman act.sa_sigaction = power_button_handler;
439*5c4a5fe1SAndy Fiddaman (void) sigaction(SIGTERM, &act, NULL);
440*5c4a5fe1SAndy Fiddaman }
441*5c4a5fe1SAndy Fiddaman #endif
442*5c4a5fe1SAndy Fiddaman }
443*5c4a5fe1SAndy Fiddaman
444*5c4a5fe1SAndy Fiddaman #ifndef __FreeBSD__
pmtmr_init(struct vmctx * ctx)445*5c4a5fe1SAndy Fiddaman void pmtmr_init(struct vmctx *ctx)
446*5c4a5fe1SAndy Fiddaman {
447*5c4a5fe1SAndy Fiddaman int err;
448*5c4a5fe1SAndy Fiddaman
449*5c4a5fe1SAndy Fiddaman /* Attach in-kernel PM timer emulation to correct IO port */
450*5c4a5fe1SAndy Fiddaman err = vm_pmtmr_set_location(ctx, IO_PMTMR);
451*5c4a5fe1SAndy Fiddaman assert(err == 0);
452*5c4a5fe1SAndy Fiddaman }
453*5c4a5fe1SAndy Fiddaman #endif
454