1*f2635e84SEric Joyner /* SPDX-License-Identifier: BSD-3-Clause */ 2*f2635e84SEric Joyner /* Copyright (c) 2024, Intel Corporation 3*f2635e84SEric Joyner * All rights reserved. 4*f2635e84SEric Joyner * 5*f2635e84SEric Joyner * Redistribution and use in source and binary forms, with or without 6*f2635e84SEric Joyner * modification, are permitted provided that the following conditions are met: 7*f2635e84SEric Joyner * 8*f2635e84SEric Joyner * 1. Redistributions of source code must retain the above copyright notice, 9*f2635e84SEric Joyner * this list of conditions and the following disclaimer. 10*f2635e84SEric Joyner * 11*f2635e84SEric Joyner * 2. Redistributions in binary form must reproduce the above copyright 12*f2635e84SEric Joyner * notice, this list of conditions and the following disclaimer in the 13*f2635e84SEric Joyner * documentation and/or other materials provided with the distribution. 14*f2635e84SEric Joyner * 15*f2635e84SEric Joyner * 3. Neither the name of the Intel Corporation nor the names of its 16*f2635e84SEric Joyner * contributors may be used to endorse or promote products derived from 17*f2635e84SEric Joyner * this software without specific prior written permission. 18*f2635e84SEric Joyner * 19*f2635e84SEric Joyner * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20*f2635e84SEric Joyner * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21*f2635e84SEric Joyner * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22*f2635e84SEric Joyner * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23*f2635e84SEric Joyner * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24*f2635e84SEric Joyner * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25*f2635e84SEric Joyner * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26*f2635e84SEric Joyner * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27*f2635e84SEric Joyner * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28*f2635e84SEric Joyner * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29*f2635e84SEric Joyner * POSSIBILITY OF SUCH DAMAGE. 30*f2635e84SEric Joyner */ 31*f2635e84SEric Joyner 32*f2635e84SEric Joyner #ifndef _ICE_SBQ_CMD_H_ 33*f2635e84SEric Joyner #define _ICE_SBQ_CMD_H_ 34*f2635e84SEric Joyner 35*f2635e84SEric Joyner /* This header file defines the Sideband Queue commands, error codes and 36*f2635e84SEric Joyner * descriptor format. It is shared between Firmware and Software. 37*f2635e84SEric Joyner */ 38*f2635e84SEric Joyner 39*f2635e84SEric Joyner /* Sideband Queue command structure and opcodes */ 40*f2635e84SEric Joyner enum ice_sbq_opc { 41*f2635e84SEric Joyner /* Sideband Queue commands */ 42*f2635e84SEric Joyner ice_sbq_opc_neigh_dev_req = 0x0C00, 43*f2635e84SEric Joyner ice_sbq_opc_neigh_dev_ev = 0x0C01 44*f2635e84SEric Joyner }; 45*f2635e84SEric Joyner 46*f2635e84SEric Joyner /* Sideband Queue descriptor. Indirect command 47*f2635e84SEric Joyner * and non posted 48*f2635e84SEric Joyner */ 49*f2635e84SEric Joyner struct ice_sbq_cmd_desc { 50*f2635e84SEric Joyner __le16 flags; 51*f2635e84SEric Joyner __le16 opcode; 52*f2635e84SEric Joyner __le16 datalen; 53*f2635e84SEric Joyner __le16 cmd_retval; 54*f2635e84SEric Joyner 55*f2635e84SEric Joyner /* Opaque message data */ 56*f2635e84SEric Joyner __le32 cookie_high; 57*f2635e84SEric Joyner __le32 cookie_low; 58*f2635e84SEric Joyner 59*f2635e84SEric Joyner union { 60*f2635e84SEric Joyner __le16 cmd_len; 61*f2635e84SEric Joyner __le16 cmpl_len; 62*f2635e84SEric Joyner } param0; 63*f2635e84SEric Joyner 64*f2635e84SEric Joyner u8 reserved[6]; 65*f2635e84SEric Joyner __le32 addr_high; 66*f2635e84SEric Joyner __le32 addr_low; 67*f2635e84SEric Joyner }; 68*f2635e84SEric Joyner 69*f2635e84SEric Joyner struct ice_sbq_evt_desc { 70*f2635e84SEric Joyner __le16 flags; 71*f2635e84SEric Joyner __le16 opcode; 72*f2635e84SEric Joyner __le16 datalen; 73*f2635e84SEric Joyner __le16 cmd_retval; 74*f2635e84SEric Joyner u8 data[24]; 75*f2635e84SEric Joyner }; 76*f2635e84SEric Joyner 77*f2635e84SEric Joyner enum ice_sbq_msg_dev { 78*f2635e84SEric Joyner rmn_0 = 0x02, 79*f2635e84SEric Joyner rmn_1 = 0x03, 80*f2635e84SEric Joyner rmn_2 = 0x04, 81*f2635e84SEric Joyner cgu = 0x06 82*f2635e84SEric Joyner }; 83*f2635e84SEric Joyner 84*f2635e84SEric Joyner enum ice_sbq_msg_opcode { 85*f2635e84SEric Joyner ice_sbq_msg_rd = 0x00, 86*f2635e84SEric Joyner ice_sbq_msg_wr = 0x01 87*f2635e84SEric Joyner }; 88*f2635e84SEric Joyner 89*f2635e84SEric Joyner #define ICE_SBQ_MSG_FLAGS 0x40 90*f2635e84SEric Joyner #define ICE_SBQ_MSG_SBE_FBE 0x0F 91*f2635e84SEric Joyner 92*f2635e84SEric Joyner struct ice_sbq_msg_req { 93*f2635e84SEric Joyner u8 dest_dev; 94*f2635e84SEric Joyner u8 src_dev; 95*f2635e84SEric Joyner u8 opcode; 96*f2635e84SEric Joyner u8 flags; 97*f2635e84SEric Joyner u8 sbe_fbe; 98*f2635e84SEric Joyner u8 func_id; 99*f2635e84SEric Joyner __le16 msg_addr_low; 100*f2635e84SEric Joyner __le32 msg_addr_high; 101*f2635e84SEric Joyner __le32 data; 102*f2635e84SEric Joyner }; 103*f2635e84SEric Joyner 104*f2635e84SEric Joyner struct ice_sbq_msg_cmpl { 105*f2635e84SEric Joyner u8 dest_dev; 106*f2635e84SEric Joyner u8 src_dev; 107*f2635e84SEric Joyner u8 opcode; 108*f2635e84SEric Joyner u8 flags; 109*f2635e84SEric Joyner __le32 data; 110*f2635e84SEric Joyner }; 111*f2635e84SEric Joyner 112*f2635e84SEric Joyner /* Internal struct */ 113*f2635e84SEric Joyner struct ice_sbq_msg_input { 114*f2635e84SEric Joyner u8 dest_dev; 115*f2635e84SEric Joyner u8 opcode; 116*f2635e84SEric Joyner u16 msg_addr_low; 117*f2635e84SEric Joyner u32 msg_addr_high; 118*f2635e84SEric Joyner u32 data; 119*f2635e84SEric Joyner }; 120*f2635e84SEric Joyner #endif /* _ICE_SBQ_CMD_H_ */ 121