171d10453SEric Joyner /* SPDX-License-Identifier: BSD-3-Clause */ 2015f8cc5SEric Joyner /* Copyright (c) 2024, Intel Corporation 371d10453SEric Joyner * All rights reserved. 471d10453SEric Joyner * 571d10453SEric Joyner * Redistribution and use in source and binary forms, with or without 671d10453SEric Joyner * modification, are permitted provided that the following conditions are met: 771d10453SEric Joyner * 871d10453SEric Joyner * 1. Redistributions of source code must retain the above copyright notice, 971d10453SEric Joyner * this list of conditions and the following disclaimer. 1071d10453SEric Joyner * 1171d10453SEric Joyner * 2. Redistributions in binary form must reproduce the above copyright 1271d10453SEric Joyner * notice, this list of conditions and the following disclaimer in the 1371d10453SEric Joyner * documentation and/or other materials provided with the distribution. 1471d10453SEric Joyner * 1571d10453SEric Joyner * 3. Neither the name of the Intel Corporation nor the names of its 1671d10453SEric Joyner * contributors may be used to endorse or promote products derived from 1771d10453SEric Joyner * this software without specific prior written permission. 1871d10453SEric Joyner * 1971d10453SEric Joyner * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2071d10453SEric Joyner * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2171d10453SEric Joyner * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2271d10453SEric Joyner * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2371d10453SEric Joyner * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2471d10453SEric Joyner * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2571d10453SEric Joyner * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2671d10453SEric Joyner * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2771d10453SEric Joyner * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2871d10453SEric Joyner * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2971d10453SEric Joyner * POSSIBILITY OF SUCH DAMAGE. 3071d10453SEric Joyner */ 3171d10453SEric Joyner 3271d10453SEric Joyner #ifndef _ICE_CONTROLQ_H_ 3371d10453SEric Joyner #define _ICE_CONTROLQ_H_ 3471d10453SEric Joyner 3571d10453SEric Joyner #include "ice_adminq_cmd.h" 3671d10453SEric Joyner 3771d10453SEric Joyner /* Maximum buffer lengths for all control queue types */ 3871d10453SEric Joyner #define ICE_AQ_MAX_BUF_LEN 4096 3971d10453SEric Joyner #define ICE_MBXQ_MAX_BUF_LEN 4096 40*f2635e84SEric Joyner #define ICE_SBQ_MAX_BUF_LEN 512 4171d10453SEric Joyner 4271d10453SEric Joyner #define ICE_CTL_Q_DESC(R, i) \ 4371d10453SEric Joyner (&(((struct ice_aq_desc *)((R).desc_buf.va))[i])) 4471d10453SEric Joyner 4571d10453SEric Joyner #define ICE_CTL_Q_DESC_UNUSED(R) \ 469cf1841cSEric Joyner ((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 479cf1841cSEric Joyner (R)->next_to_clean - (R)->next_to_use - 1)) 4871d10453SEric Joyner 4971d10453SEric Joyner /* Defines that help manage the driver vs FW API checks. 5071d10453SEric Joyner * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage. 5171d10453SEric Joyner */ 52*f2635e84SEric Joyner #define EXP_FW_API_VER_BRANCH_E830 0x00 53*f2635e84SEric Joyner #define EXP_FW_API_VER_MAJOR_E830 0x01 54*f2635e84SEric Joyner #define EXP_FW_API_VER_MINOR_E830 0x07 55*f2635e84SEric Joyner 56*f2635e84SEric Joyner #define EXP_FW_API_VER_BRANCH_E810 0x00 57*f2635e84SEric Joyner #define EXP_FW_API_VER_MAJOR_E810 0x01 58*f2635e84SEric Joyner #define EXP_FW_API_VER_MINOR_E810 0x05 59*f2635e84SEric Joyner 60*f2635e84SEric Joyner #define EXP_FW_API_VER_BRANCH_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? \ 61*f2635e84SEric Joyner EXP_FW_API_VER_BRANCH_E830 : \ 62*f2635e84SEric Joyner EXP_FW_API_VER_BRANCH_E810) 63*f2635e84SEric Joyner 64*f2635e84SEric Joyner #define EXP_FW_API_VER_MAJOR_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? \ 65*f2635e84SEric Joyner EXP_FW_API_VER_MAJOR_E830 : \ 66*f2635e84SEric Joyner EXP_FW_API_VER_MAJOR_E810) 67*f2635e84SEric Joyner 68*f2635e84SEric Joyner #define EXP_FW_API_VER_MINOR_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? \ 69*f2635e84SEric Joyner EXP_FW_API_VER_MINOR_E830 : \ 70*f2635e84SEric Joyner EXP_FW_API_VER_MINOR_E810) 7171d10453SEric Joyner 7271d10453SEric Joyner /* Different control queue types: These are mainly for SW consumption. */ 7371d10453SEric Joyner enum ice_ctl_q { 7471d10453SEric Joyner ICE_CTL_Q_UNKNOWN = 0, 7571d10453SEric Joyner ICE_CTL_Q_ADMIN, 7671d10453SEric Joyner ICE_CTL_Q_MAILBOX, 77*f2635e84SEric Joyner ICE_CTL_Q_SB, 7871d10453SEric Joyner }; 7971d10453SEric Joyner 80d08b8680SEric Joyner /* Control Queue timeout settings - max delay 1s */ 819e54973fSEric Joyner #define ICE_CTL_Q_SQ_CMD_TIMEOUT 100000 /* Count 100000 times */ 827d7af7f8SEric Joyner #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */ 837d7af7f8SEric Joyner #define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */ 8471d10453SEric Joyner 8571d10453SEric Joyner struct ice_ctl_q_ring { 8671d10453SEric Joyner void *dma_head; /* Virtual address to DMA head */ 8771d10453SEric Joyner struct ice_dma_mem desc_buf; /* descriptor ring memory */ 8871d10453SEric Joyner 8971d10453SEric Joyner union { 9071d10453SEric Joyner struct ice_dma_mem *sq_bi; 9171d10453SEric Joyner struct ice_dma_mem *rq_bi; 9271d10453SEric Joyner } r; 9371d10453SEric Joyner 9471d10453SEric Joyner u16 count; /* Number of descriptors */ 9571d10453SEric Joyner 9671d10453SEric Joyner /* used for interrupt processing */ 9771d10453SEric Joyner u16 next_to_use; 9871d10453SEric Joyner u16 next_to_clean; 9971d10453SEric Joyner 10071d10453SEric Joyner /* used for queue tracking */ 10171d10453SEric Joyner u32 head; 10271d10453SEric Joyner u32 tail; 10371d10453SEric Joyner u32 len; 10471d10453SEric Joyner u32 bah; 10571d10453SEric Joyner u32 bal; 10671d10453SEric Joyner u32 len_mask; 10771d10453SEric Joyner u32 len_ena_mask; 1087d7af7f8SEric Joyner u32 len_crit_mask; 10971d10453SEric Joyner u32 head_mask; 11071d10453SEric Joyner }; 11171d10453SEric Joyner 11271d10453SEric Joyner /* sq transaction details */ 11371d10453SEric Joyner struct ice_sq_cd { 11471d10453SEric Joyner struct ice_aq_desc *wb_desc; 11571d10453SEric Joyner }; 11671d10453SEric Joyner 11771d10453SEric Joyner /* rq event information */ 11871d10453SEric Joyner struct ice_rq_event_info { 11971d10453SEric Joyner struct ice_aq_desc desc; 12071d10453SEric Joyner u16 msg_len; 12171d10453SEric Joyner u16 buf_len; 12271d10453SEric Joyner u8 *msg_buf; 12371d10453SEric Joyner }; 12471d10453SEric Joyner 12571d10453SEric Joyner /* Control Queue information */ 12671d10453SEric Joyner struct ice_ctl_q_info { 12771d10453SEric Joyner enum ice_ctl_q qtype; 12871d10453SEric Joyner struct ice_ctl_q_ring rq; /* receive queue */ 12971d10453SEric Joyner struct ice_ctl_q_ring sq; /* send queue */ 13071d10453SEric Joyner u32 sq_cmd_timeout; /* send queue cmd write back timeout */ 13171d10453SEric Joyner u16 num_rq_entries; /* receive queue depth */ 13271d10453SEric Joyner u16 num_sq_entries; /* send queue depth */ 13371d10453SEric Joyner u16 rq_buf_size; /* receive queue buffer size */ 13471d10453SEric Joyner u16 sq_buf_size; /* send queue buffer size */ 13571d10453SEric Joyner enum ice_aq_err sq_last_status; /* last status on send queue */ 13671d10453SEric Joyner struct ice_lock sq_lock; /* Send queue lock */ 13771d10453SEric Joyner struct ice_lock rq_lock; /* Receive queue lock */ 13871d10453SEric Joyner }; 13971d10453SEric Joyner 14071d10453SEric Joyner #endif /* _ICE_CONTROLQ_H_ */ 141