19c067b84SDoug Ambrisko /* SPDX-License-Identifier: BSD-3-Clause 29c067b84SDoug Ambrisko * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 39c067b84SDoug Ambrisko * Copyright 2007 Nuova Systems, Inc. All rights reserved. 49c067b84SDoug Ambrisko */ 59c067b84SDoug Ambrisko 69c067b84SDoug Ambrisko #ifndef _VNIC_RESOURCE_H_ 79c067b84SDoug Ambrisko #define _VNIC_RESOURCE_H_ 89c067b84SDoug Ambrisko 99c067b84SDoug Ambrisko #define VNIC_RES_MAGIC 0x766E6963L /* 'vnic' */ 109c067b84SDoug Ambrisko #define VNIC_RES_VERSION 0x00000000L 119c067b84SDoug Ambrisko #define MGMTVNIC_MAGIC 0x544d474dL /* 'MGMT' */ 129c067b84SDoug Ambrisko #define MGMTVNIC_VERSION 0x00000000L 139c067b84SDoug Ambrisko 149c067b84SDoug Ambrisko /* The MAC address assigned to the CFG vNIC is fixed. */ 159c067b84SDoug Ambrisko #define MGMTVNIC_MAC { 0x02, 0x00, 0x54, 0x4d, 0x47, 0x4d } 169c067b84SDoug Ambrisko 179c067b84SDoug Ambrisko /* vNIC resource types */ 189c067b84SDoug Ambrisko enum vnic_res_type { 199c067b84SDoug Ambrisko RES_TYPE_EOL, /* End-of-list */ 209c067b84SDoug Ambrisko RES_TYPE_WQ, /* Work queues */ 219c067b84SDoug Ambrisko RES_TYPE_RQ, /* Receive queues */ 229c067b84SDoug Ambrisko RES_TYPE_CQ, /* Completion queues */ 239c067b84SDoug Ambrisko RES_TYPE_MEM, /* Window to dev memory */ 249c067b84SDoug Ambrisko RES_TYPE_NIC_CFG, /* Enet NIC config registers */ 259c067b84SDoug Ambrisko RES_TYPE_RSS_KEY, /* Enet RSS secret key */ 269c067b84SDoug Ambrisko RES_TYPE_RSS_CPU, /* Enet RSS indirection table */ 279c067b84SDoug Ambrisko RES_TYPE_TX_STATS, /* Netblock Tx statistic regs */ 289c067b84SDoug Ambrisko RES_TYPE_RX_STATS, /* Netblock Rx statistic regs */ 299c067b84SDoug Ambrisko RES_TYPE_INTR_CTRL, /* Interrupt ctrl table */ 309c067b84SDoug Ambrisko RES_TYPE_INTR_TABLE, /* MSI/MSI-X Interrupt table */ 319c067b84SDoug Ambrisko RES_TYPE_INTR_PBA, /* MSI/MSI-X PBA table */ 329c067b84SDoug Ambrisko RES_TYPE_INTR_PBA_LEGACY, /* Legacy intr status */ 339c067b84SDoug Ambrisko RES_TYPE_DEBUG, /* Debug-only info */ 349c067b84SDoug Ambrisko RES_TYPE_DEV, /* Device-specific region */ 359c067b84SDoug Ambrisko RES_TYPE_DEVCMD, /* Device command region */ 369c067b84SDoug Ambrisko RES_TYPE_PASS_THRU_PAGE, /* Pass-thru page */ 379c067b84SDoug Ambrisko RES_TYPE_SUBVNIC, /* subvnic resource type */ 389c067b84SDoug Ambrisko RES_TYPE_MQ_WQ, /* MQ Work queues */ 399c067b84SDoug Ambrisko RES_TYPE_MQ_RQ, /* MQ Receive queues */ 409c067b84SDoug Ambrisko RES_TYPE_MQ_CQ, /* MQ Completion queues */ 419c067b84SDoug Ambrisko RES_TYPE_DEPRECATED1, /* Old version of devcmd 2 */ 42*0acab8b3SDoug Ambrisko RES_TYPE_DEPRECATED2, /* Old version of devcmd 2 */ 439c067b84SDoug Ambrisko RES_TYPE_DEVCMD2, /* Device control region */ 449c067b84SDoug Ambrisko RES_TYPE_MAX, /* Count of resource types */ 459c067b84SDoug Ambrisko }; 469c067b84SDoug Ambrisko 479c067b84SDoug Ambrisko struct vnic_resource_header { 489c067b84SDoug Ambrisko u32 magic; 499c067b84SDoug Ambrisko u32 version; 509c067b84SDoug Ambrisko }; 519c067b84SDoug Ambrisko 529c067b84SDoug Ambrisko struct mgmt_barmap_hdr { 539c067b84SDoug Ambrisko u32 magic; /* magic number */ 549c067b84SDoug Ambrisko u32 version; /* header format version */ 559c067b84SDoug Ambrisko u16 lif; /* loopback lif for mgmt frames */ 569c067b84SDoug Ambrisko u16 pci_slot; /* installed pci slot */ 579c067b84SDoug Ambrisko char serial[16]; /* card serial number */ 589c067b84SDoug Ambrisko }; 599c067b84SDoug Ambrisko 609c067b84SDoug Ambrisko struct vnic_resource { 619c067b84SDoug Ambrisko u8 type; 629c067b84SDoug Ambrisko u8 bar; 639c067b84SDoug Ambrisko u8 pad[2]; 649c067b84SDoug Ambrisko u32 bar_offset; 659c067b84SDoug Ambrisko u32 count; 669c067b84SDoug Ambrisko }; 679c067b84SDoug Ambrisko 689c067b84SDoug Ambrisko #endif /* _VNIC_RESOURCE_H_ */ 69