1*9c067b84SDoug Ambrisko /* SPDX-License-Identifier: BSD-3-Clause 2*9c067b84SDoug Ambrisko * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3*9c067b84SDoug Ambrisko * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4*9c067b84SDoug Ambrisko */ 5*9c067b84SDoug Ambrisko 6*9c067b84SDoug Ambrisko #ifndef _VNIC_ENIC_H_ 7*9c067b84SDoug Ambrisko #define _VNIC_ENIC_H_ 8*9c067b84SDoug Ambrisko 9*9c067b84SDoug Ambrisko /* Hardware intr coalesce timer is in units of 1.5us */ 10*9c067b84SDoug Ambrisko #define INTR_COALESCE_USEC_TO_HW(usec) ((usec) * 2 / 3) 11*9c067b84SDoug Ambrisko #define INTR_COALESCE_HW_TO_USEC(usec) ((usec) * 3 / 2) 12*9c067b84SDoug Ambrisko 13*9c067b84SDoug Ambrisko /* Device-specific region: enet configuration */ 14*9c067b84SDoug Ambrisko struct vnic_enet_config { 15*9c067b84SDoug Ambrisko u32 flags; 16*9c067b84SDoug Ambrisko u32 wq_desc_count; 17*9c067b84SDoug Ambrisko u32 rq_desc_count; 18*9c067b84SDoug Ambrisko u16 mtu; 19*9c067b84SDoug Ambrisko u16 intr_timer_deprecated; 20*9c067b84SDoug Ambrisko u8 intr_timer_type; 21*9c067b84SDoug Ambrisko u8 intr_mode; 22*9c067b84SDoug Ambrisko char devname[16]; 23*9c067b84SDoug Ambrisko u32 intr_timer_usec; 24*9c067b84SDoug Ambrisko u16 loop_tag; 25*9c067b84SDoug Ambrisko u16 vf_rq_count; 26*9c067b84SDoug Ambrisko u16 num_arfs; 27*9c067b84SDoug Ambrisko u64 mem_paddr; 28*9c067b84SDoug Ambrisko u16 rdma_qp_id; 29*9c067b84SDoug Ambrisko u16 rdma_qp_count; 30*9c067b84SDoug Ambrisko u16 rdma_resgrp; 31*9c067b84SDoug Ambrisko u32 rdma_mr_id; 32*9c067b84SDoug Ambrisko u32 rdma_mr_count; 33*9c067b84SDoug Ambrisko u32 max_pkt_size; 34*9c067b84SDoug Ambrisko }; 35*9c067b84SDoug Ambrisko 36*9c067b84SDoug Ambrisko #define VENETF_TSO 0x1 /* TSO enabled */ 37*9c067b84SDoug Ambrisko #define VENETF_LRO 0x2 /* LRO enabled */ 38*9c067b84SDoug Ambrisko #define VENETF_RXCSUM 0x4 /* RX csum enabled */ 39*9c067b84SDoug Ambrisko #define VENETF_TXCSUM 0x8 /* TX csum enabled */ 40*9c067b84SDoug Ambrisko #define VENETF_RSS 0x10 /* RSS enabled */ 41*9c067b84SDoug Ambrisko #define VENETF_RSSHASH_IPV4 0x20 /* Hash on IPv4 fields */ 42*9c067b84SDoug Ambrisko #define VENETF_RSSHASH_TCPIPV4 0x40 /* Hash on TCP + IPv4 fields */ 43*9c067b84SDoug Ambrisko #define VENETF_RSSHASH_IPV6 0x80 /* Hash on IPv6 fields */ 44*9c067b84SDoug Ambrisko #define VENETF_RSSHASH_TCPIPV6 0x100 /* Hash on TCP + IPv6 fields */ 45*9c067b84SDoug Ambrisko #define VENETF_RSSHASH_IPV6_EX 0x200 /* Hash on IPv6 extended fields */ 46*9c067b84SDoug Ambrisko #define VENETF_RSSHASH_TCPIPV6_EX 0x400 /* Hash on TCP + IPv6 ext. fields */ 47*9c067b84SDoug Ambrisko #define VENETF_LOOP 0x800 /* Loopback enabled */ 48*9c067b84SDoug Ambrisko #define VENETF_FAILOVER 0x1000 /* Fabric failover enabled */ 49*9c067b84SDoug Ambrisko #define VENETF_USPACE_NIC 0x2000 /* vHPC enabled */ 50*9c067b84SDoug Ambrisko #define VENETF_VMQ 0x4000 /* VMQ enabled */ 51*9c067b84SDoug Ambrisko #define VENETF_ARFS 0x8000 /* ARFS enabled */ 52*9c067b84SDoug Ambrisko #define VENETF_VXLAN 0x10000 /* VxLAN offload */ 53*9c067b84SDoug Ambrisko #define VENETF_NVGRE 0x20000 /* NVGRE offload */ 54*9c067b84SDoug Ambrisko #define VENETF_GRPINTR 0x40000 /* group interrupt */ 55*9c067b84SDoug Ambrisko #define VENETF_NICSWITCH 0x80000 /* NICSWITCH enabled */ 56*9c067b84SDoug Ambrisko #define VENETF_RSSHASH_UDPIPV4 0x100000 /* Hash on UDP + IPv4 fields */ 57*9c067b84SDoug Ambrisko #define VENETF_RSSHASH_UDPIPV6 0x200000 /* Hash on UDP + IPv6 fields */ 58*9c067b84SDoug Ambrisko 59*9c067b84SDoug Ambrisko #define VENET_INTR_TYPE_MIN 0 /* Timer specs min interrupt spacing */ 60*9c067b84SDoug Ambrisko #define VENET_INTR_TYPE_IDLE 1 /* Timer specs idle time before irq */ 61*9c067b84SDoug Ambrisko 62*9c067b84SDoug Ambrisko #define VENET_INTR_MODE_ANY 0 /* Try MSI-X, then MSI, then INTx */ 63*9c067b84SDoug Ambrisko #define VENET_INTR_MODE_MSI 1 /* Try MSI then INTx */ 64*9c067b84SDoug Ambrisko #define VENET_INTR_MODE_INTX 2 /* Try INTx only */ 65*9c067b84SDoug Ambrisko 66*9c067b84SDoug Ambrisko #endif /* _VNIC_ENIC_H_ */ 67