1e67e8565SEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2e67e8565SEmmanuel Vadot /* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */ 3e67e8565SEmmanuel Vadot 4e67e8565SEmmanuel Vadot /* 5e67e8565SEmmanuel Vadot * This header provides constants for binding nvidia,tegra234-gpio*. 6e67e8565SEmmanuel Vadot * 7e67e8565SEmmanuel Vadot * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 8e67e8565SEmmanuel Vadot * provide names for this. 9e67e8565SEmmanuel Vadot * 10e67e8565SEmmanuel Vadot * The second cell contains standard flag values specified in gpio.h. 11e67e8565SEmmanuel Vadot */ 12e67e8565SEmmanuel Vadot 13e67e8565SEmmanuel Vadot #ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H 14e67e8565SEmmanuel Vadot #define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H 15e67e8565SEmmanuel Vadot 16e67e8565SEmmanuel Vadot #include <dt-bindings/gpio/gpio.h> 17e67e8565SEmmanuel Vadot 18e67e8565SEmmanuel Vadot /* GPIOs implemented by main GPIO controller */ 19e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_A 0 20e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_B 1 21e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_C 2 22e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_D 3 23e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_E 4 24e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_F 5 25e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_G 6 26e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_H 7 27e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_I 8 28e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_J 9 29e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_K 10 30e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_L 11 31e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_M 12 32e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_N 13 33e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_P 14 34e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_Q 15 35e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_R 16 36*f126890aSEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_X 17 37*f126890aSEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_Y 18 38*f126890aSEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_Z 19 39*f126890aSEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_AC 20 40*f126890aSEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_AD 21 41*f126890aSEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_AE 22 42*f126890aSEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_AF 23 43*f126890aSEmmanuel Vadot #define TEGRA234_MAIN_GPIO_PORT_AG 24 44e67e8565SEmmanuel Vadot 45e67e8565SEmmanuel Vadot #define TEGRA234_MAIN_GPIO(port, offset) \ 46e67e8565SEmmanuel Vadot ((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset) 47e67e8565SEmmanuel Vadot 48e67e8565SEmmanuel Vadot /* GPIOs implemented by AON GPIO controller */ 49e67e8565SEmmanuel Vadot #define TEGRA234_AON_GPIO_PORT_AA 0 50e67e8565SEmmanuel Vadot #define TEGRA234_AON_GPIO_PORT_BB 1 51e67e8565SEmmanuel Vadot #define TEGRA234_AON_GPIO_PORT_CC 2 52e67e8565SEmmanuel Vadot #define TEGRA234_AON_GPIO_PORT_DD 3 53e67e8565SEmmanuel Vadot #define TEGRA234_AON_GPIO_PORT_EE 4 54e67e8565SEmmanuel Vadot #define TEGRA234_AON_GPIO_PORT_GG 5 55e67e8565SEmmanuel Vadot 56e67e8565SEmmanuel Vadot #define TEGRA234_AON_GPIO(port, offset) \ 57e67e8565SEmmanuel Vadot ((TEGRA234_AON_GPIO_PORT_##port * 8) + offset) 58e67e8565SEmmanuel Vadot 59e67e8565SEmmanuel Vadot #endif 60