1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 4*c66ec88fSEmmanuel Vadot */ 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel Vadot #ifndef __DTS_HISTB_CLOCK_H 7*c66ec88fSEmmanuel Vadot #define __DTS_HISTB_CLOCK_H 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot /* clocks provided by core CRG */ 10*c66ec88fSEmmanuel Vadot #define HISTB_OSC_CLK 0 11*c66ec88fSEmmanuel Vadot #define HISTB_APB_CLK 1 12*c66ec88fSEmmanuel Vadot #define HISTB_AHB_CLK 2 13*c66ec88fSEmmanuel Vadot #define HISTB_UART1_CLK 3 14*c66ec88fSEmmanuel Vadot #define HISTB_UART2_CLK 4 15*c66ec88fSEmmanuel Vadot #define HISTB_UART3_CLK 5 16*c66ec88fSEmmanuel Vadot #define HISTB_I2C0_CLK 6 17*c66ec88fSEmmanuel Vadot #define HISTB_I2C1_CLK 7 18*c66ec88fSEmmanuel Vadot #define HISTB_I2C2_CLK 8 19*c66ec88fSEmmanuel Vadot #define HISTB_I2C3_CLK 9 20*c66ec88fSEmmanuel Vadot #define HISTB_I2C4_CLK 10 21*c66ec88fSEmmanuel Vadot #define HISTB_I2C5_CLK 11 22*c66ec88fSEmmanuel Vadot #define HISTB_SPI0_CLK 12 23*c66ec88fSEmmanuel Vadot #define HISTB_SPI1_CLK 13 24*c66ec88fSEmmanuel Vadot #define HISTB_SPI2_CLK 14 25*c66ec88fSEmmanuel Vadot #define HISTB_SCI_CLK 15 26*c66ec88fSEmmanuel Vadot #define HISTB_FMC_CLK 16 27*c66ec88fSEmmanuel Vadot #define HISTB_MMC_BIU_CLK 17 28*c66ec88fSEmmanuel Vadot #define HISTB_MMC_CIU_CLK 18 29*c66ec88fSEmmanuel Vadot #define HISTB_MMC_DRV_CLK 19 30*c66ec88fSEmmanuel Vadot #define HISTB_MMC_SAMPLE_CLK 20 31*c66ec88fSEmmanuel Vadot #define HISTB_SDIO0_BIU_CLK 21 32*c66ec88fSEmmanuel Vadot #define HISTB_SDIO0_CIU_CLK 22 33*c66ec88fSEmmanuel Vadot #define HISTB_SDIO0_DRV_CLK 23 34*c66ec88fSEmmanuel Vadot #define HISTB_SDIO0_SAMPLE_CLK 24 35*c66ec88fSEmmanuel Vadot #define HISTB_PCIE_AUX_CLK 25 36*c66ec88fSEmmanuel Vadot #define HISTB_PCIE_PIPE_CLK 26 37*c66ec88fSEmmanuel Vadot #define HISTB_PCIE_SYS_CLK 27 38*c66ec88fSEmmanuel Vadot #define HISTB_PCIE_BUS_CLK 28 39*c66ec88fSEmmanuel Vadot #define HISTB_ETH0_MAC_CLK 29 40*c66ec88fSEmmanuel Vadot #define HISTB_ETH0_MACIF_CLK 30 41*c66ec88fSEmmanuel Vadot #define HISTB_ETH1_MAC_CLK 31 42*c66ec88fSEmmanuel Vadot #define HISTB_ETH1_MACIF_CLK 32 43*c66ec88fSEmmanuel Vadot #define HISTB_COMBPHY1_CLK 33 44*c66ec88fSEmmanuel Vadot #define HISTB_USB2_BUS_CLK 34 45*c66ec88fSEmmanuel Vadot #define HISTB_USB2_PHY_CLK 35 46*c66ec88fSEmmanuel Vadot #define HISTB_USB2_UTMI_CLK 36 47*c66ec88fSEmmanuel Vadot #define HISTB_USB2_12M_CLK 37 48*c66ec88fSEmmanuel Vadot #define HISTB_USB2_48M_CLK 38 49*c66ec88fSEmmanuel Vadot #define HISTB_USB2_OTG_UTMI_CLK 39 50*c66ec88fSEmmanuel Vadot #define HISTB_USB2_PHY1_REF_CLK 40 51*c66ec88fSEmmanuel Vadot #define HISTB_USB2_PHY2_REF_CLK 41 52*c66ec88fSEmmanuel Vadot #define HISTB_COMBPHY0_CLK 42 53*c66ec88fSEmmanuel Vadot #define HISTB_USB3_BUS_CLK 43 54*c66ec88fSEmmanuel Vadot #define HISTB_USB3_UTMI_CLK 44 55*c66ec88fSEmmanuel Vadot #define HISTB_USB3_PIPE_CLK 45 56*c66ec88fSEmmanuel Vadot #define HISTB_USB3_SUSPEND_CLK 46 57*c66ec88fSEmmanuel Vadot #define HISTB_USB3_BUS_CLK1 47 58*c66ec88fSEmmanuel Vadot #define HISTB_USB3_UTMI_CLK1 48 59*c66ec88fSEmmanuel Vadot #define HISTB_USB3_PIPE_CLK1 49 60*c66ec88fSEmmanuel Vadot #define HISTB_USB3_SUSPEND_CLK1 50 61*c66ec88fSEmmanuel Vadot 62*c66ec88fSEmmanuel Vadot /* clocks provided by mcu CRG */ 63*c66ec88fSEmmanuel Vadot #define HISTB_MCE_CLK 1 64*c66ec88fSEmmanuel Vadot #define HISTB_IR_CLK 2 65*c66ec88fSEmmanuel Vadot #define HISTB_TIMER01_CLK 3 66*c66ec88fSEmmanuel Vadot #define HISTB_LEDC_CLK 4 67*c66ec88fSEmmanuel Vadot #define HISTB_UART0_CLK 5 68*c66ec88fSEmmanuel Vadot #define HISTB_LSADC_CLK 6 69*c66ec88fSEmmanuel Vadot 70*c66ec88fSEmmanuel Vadot #endif /* __DTS_HISTB_CLOCK_H */ 71