1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (C) 2019, Intel Corporation 4*c66ec88fSEmmanuel Vadot */ 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel Vadot #ifndef __AGILEX_CLOCK_H 7*c66ec88fSEmmanuel Vadot #define __AGILEX_CLOCK_H 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot /* fixed rate clocks */ 10*c66ec88fSEmmanuel Vadot #define AGILEX_OSC1 0 11*c66ec88fSEmmanuel Vadot #define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 12*c66ec88fSEmmanuel Vadot #define AGILEX_CB_INTOSC_LS_CLK 2 13*c66ec88fSEmmanuel Vadot #define AGILEX_L4_SYS_FREE_CLK 3 14*c66ec88fSEmmanuel Vadot #define AGILEX_F2S_FREE_CLK 4 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel Vadot /* PLL clocks */ 17*c66ec88fSEmmanuel Vadot #define AGILEX_MAIN_PLL_CLK 5 18*c66ec88fSEmmanuel Vadot #define AGILEX_MAIN_PLL_C0_CLK 6 19*c66ec88fSEmmanuel Vadot #define AGILEX_MAIN_PLL_C1_CLK 7 20*c66ec88fSEmmanuel Vadot #define AGILEX_MAIN_PLL_C2_CLK 8 21*c66ec88fSEmmanuel Vadot #define AGILEX_MAIN_PLL_C3_CLK 9 22*c66ec88fSEmmanuel Vadot #define AGILEX_PERIPH_PLL_CLK 10 23*c66ec88fSEmmanuel Vadot #define AGILEX_PERIPH_PLL_C0_CLK 11 24*c66ec88fSEmmanuel Vadot #define AGILEX_PERIPH_PLL_C1_CLK 12 25*c66ec88fSEmmanuel Vadot #define AGILEX_PERIPH_PLL_C2_CLK 13 26*c66ec88fSEmmanuel Vadot #define AGILEX_PERIPH_PLL_C3_CLK 14 27*c66ec88fSEmmanuel Vadot #define AGILEX_MPU_FREE_CLK 15 28*c66ec88fSEmmanuel Vadot #define AGILEX_MPU_CCU_CLK 16 29*c66ec88fSEmmanuel Vadot #define AGILEX_BOOT_CLK 17 30*c66ec88fSEmmanuel Vadot 31*c66ec88fSEmmanuel Vadot /* fixed factor clocks */ 32*c66ec88fSEmmanuel Vadot #define AGILEX_L3_MAIN_FREE_CLK 18 33*c66ec88fSEmmanuel Vadot #define AGILEX_NOC_FREE_CLK 19 34*c66ec88fSEmmanuel Vadot #define AGILEX_S2F_USR0_CLK 20 35*c66ec88fSEmmanuel Vadot #define AGILEX_NOC_CLK 21 36*c66ec88fSEmmanuel Vadot #define AGILEX_EMAC_A_FREE_CLK 22 37*c66ec88fSEmmanuel Vadot #define AGILEX_EMAC_B_FREE_CLK 23 38*c66ec88fSEmmanuel Vadot #define AGILEX_EMAC_PTP_FREE_CLK 24 39*c66ec88fSEmmanuel Vadot #define AGILEX_GPIO_DB_FREE_CLK 25 40*c66ec88fSEmmanuel Vadot #define AGILEX_SDMMC_FREE_CLK 26 41*c66ec88fSEmmanuel Vadot #define AGILEX_S2F_USER0_FREE_CLK 27 42*c66ec88fSEmmanuel Vadot #define AGILEX_S2F_USER1_FREE_CLK 28 43*c66ec88fSEmmanuel Vadot #define AGILEX_PSI_REF_FREE_CLK 29 44*c66ec88fSEmmanuel Vadot 45*c66ec88fSEmmanuel Vadot /* Gate clocks */ 46*c66ec88fSEmmanuel Vadot #define AGILEX_MPU_CLK 30 47*c66ec88fSEmmanuel Vadot #define AGILEX_MPU_L2RAM_CLK 31 48*c66ec88fSEmmanuel Vadot #define AGILEX_MPU_PERIPH_CLK 32 49*c66ec88fSEmmanuel Vadot #define AGILEX_L4_MAIN_CLK 33 50*c66ec88fSEmmanuel Vadot #define AGILEX_L4_MP_CLK 34 51*c66ec88fSEmmanuel Vadot #define AGILEX_L4_SP_CLK 35 52*c66ec88fSEmmanuel Vadot #define AGILEX_CS_AT_CLK 36 53*c66ec88fSEmmanuel Vadot #define AGILEX_CS_TRACE_CLK 37 54*c66ec88fSEmmanuel Vadot #define AGILEX_CS_PDBG_CLK 38 55*c66ec88fSEmmanuel Vadot #define AGILEX_CS_TIMER_CLK 39 56*c66ec88fSEmmanuel Vadot #define AGILEX_S2F_USER0_CLK 40 57*c66ec88fSEmmanuel Vadot #define AGILEX_EMAC0_CLK 41 58*c66ec88fSEmmanuel Vadot #define AGILEX_EMAC1_CLK 43 59*c66ec88fSEmmanuel Vadot #define AGILEX_EMAC2_CLK 44 60*c66ec88fSEmmanuel Vadot #define AGILEX_EMAC_PTP_CLK 45 61*c66ec88fSEmmanuel Vadot #define AGILEX_GPIO_DB_CLK 46 62*c66ec88fSEmmanuel Vadot #define AGILEX_NAND_CLK 47 63*c66ec88fSEmmanuel Vadot #define AGILEX_PSI_REF_CLK 48 64*c66ec88fSEmmanuel Vadot #define AGILEX_S2F_USER1_CLK 49 65*c66ec88fSEmmanuel Vadot #define AGILEX_SDMMC_CLK 50 66*c66ec88fSEmmanuel Vadot #define AGILEX_SPI_M_CLK 51 67*c66ec88fSEmmanuel Vadot #define AGILEX_USB_CLK 52 68*c66ec88fSEmmanuel Vadot #define AGILEX_NAND_X_CLK 53 69*c66ec88fSEmmanuel Vadot #define AGILEX_NAND_ECC_CLK 54 70*c66ec88fSEmmanuel Vadot #define AGILEX_NUM_CLKS 55 71*c66ec88fSEmmanuel Vadot 72*c66ec88fSEmmanuel Vadot #endif /* __AGILEX_CLOCK_H */ 73