18cc087a1SEmmanuel Vadot# SPDX-License-Identifier: GPL-2.0 28cc087a1SEmmanuel Vadot%YAML 1.2 38cc087a1SEmmanuel Vadot--- 48cc087a1SEmmanuel Vadot$id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml# 58cc087a1SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 68cc087a1SEmmanuel Vadot 7*8bab661aSEmmanuel Vadottitle: Simple memory mapped IO fixed-rate clock sources 88cc087a1SEmmanuel Vadot 98cc087a1SEmmanuel Vadotdescription: 108cc087a1SEmmanuel Vadot This binding describes a fixed-rate clock for which the frequency can 118cc087a1SEmmanuel Vadot be read from a single 32-bit memory mapped I/O register. 128cc087a1SEmmanuel Vadot 138cc087a1SEmmanuel Vadot It was designed for test systems, like FPGA, not for complete, 148cc087a1SEmmanuel Vadot finished SoCs. 158cc087a1SEmmanuel Vadot 168cc087a1SEmmanuel Vadotmaintainers: 178cc087a1SEmmanuel Vadot - Jan Kotas <jank@cadence.com> 188cc087a1SEmmanuel Vadot 198cc087a1SEmmanuel Vadotproperties: 208cc087a1SEmmanuel Vadot compatible: 218cc087a1SEmmanuel Vadot const: fixed-mmio-clock 228cc087a1SEmmanuel Vadot 238cc087a1SEmmanuel Vadot reg: 248cc087a1SEmmanuel Vadot maxItems: 1 258cc087a1SEmmanuel Vadot 268cc087a1SEmmanuel Vadot "#clock-cells": 278cc087a1SEmmanuel Vadot const: 0 288cc087a1SEmmanuel Vadot 298cc087a1SEmmanuel Vadot clock-output-names: 308cc087a1SEmmanuel Vadot maxItems: 1 318cc087a1SEmmanuel Vadot 328cc087a1SEmmanuel Vadotrequired: 338cc087a1SEmmanuel Vadot - compatible 348cc087a1SEmmanuel Vadot - reg 358cc087a1SEmmanuel Vadot - "#clock-cells" 368cc087a1SEmmanuel Vadot 378cc087a1SEmmanuel VadotadditionalProperties: false 388cc087a1SEmmanuel Vadot 398cc087a1SEmmanuel Vadotexamples: 408cc087a1SEmmanuel Vadot - | 418cc087a1SEmmanuel Vadot sysclock: sysclock@fd020004 { 428cc087a1SEmmanuel Vadot compatible = "fixed-mmio-clock"; 438cc087a1SEmmanuel Vadot #clock-cells = <0>; 448cc087a1SEmmanuel Vadot reg = <0xfd020004 0x4>; 458cc087a1SEmmanuel Vadot clock-output-names = "sysclk"; 468cc087a1SEmmanuel Vadot }; 478cc087a1SEmmanuel Vadot... 48