1*0fca6ea1SDimitry Andric //===- X86RecognizableInstr.h - Disassembler instruction spec ---*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file is part of the X86 Disassembler Emitter. 100b57cec5SDimitry Andric // It contains the interface of a single recognizable instruction. 110b57cec5SDimitry Andric // Documentation for the disassembler emitter in general can be found in 120b57cec5SDimitry Andric // X86DisassemblerEmitter.h. 130b57cec5SDimitry Andric // 140b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H 170b57cec5SDimitry Andric #define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H 180b57cec5SDimitry Andric 19*0fca6ea1SDimitry Andric #include "Common/CodeGenInstruction.h" 201fd87a68SDimitry Andric #include "llvm/Support/X86DisassemblerDecoderCommon.h" 2106c3fb27SDimitry Andric #include <cstdint> 2206c3fb27SDimitry Andric #include <string> 2306c3fb27SDimitry Andric #include <vector> 241fd87a68SDimitry Andric 251fd87a68SDimitry Andric struct InstructionSpecifier; 260b57cec5SDimitry Andric 270b57cec5SDimitry Andric namespace llvm { 281fd87a68SDimitry Andric class Record; 290b57cec5SDimitry Andric #define X86_INSTR_MRM_MAPPING \ 300b57cec5SDimitry Andric MAP(C0, 64) \ 310b57cec5SDimitry Andric MAP(C1, 65) \ 320b57cec5SDimitry Andric MAP(C2, 66) \ 330b57cec5SDimitry Andric MAP(C3, 67) \ 340b57cec5SDimitry Andric MAP(C4, 68) \ 350b57cec5SDimitry Andric MAP(C5, 69) \ 360b57cec5SDimitry Andric MAP(C6, 70) \ 370b57cec5SDimitry Andric MAP(C7, 71) \ 380b57cec5SDimitry Andric MAP(C8, 72) \ 390b57cec5SDimitry Andric MAP(C9, 73) \ 400b57cec5SDimitry Andric MAP(CA, 74) \ 410b57cec5SDimitry Andric MAP(CB, 75) \ 420b57cec5SDimitry Andric MAP(CC, 76) \ 430b57cec5SDimitry Andric MAP(CD, 77) \ 440b57cec5SDimitry Andric MAP(CE, 78) \ 450b57cec5SDimitry Andric MAP(CF, 79) \ 460b57cec5SDimitry Andric MAP(D0, 80) \ 470b57cec5SDimitry Andric MAP(D1, 81) \ 480b57cec5SDimitry Andric MAP(D2, 82) \ 490b57cec5SDimitry Andric MAP(D3, 83) \ 500b57cec5SDimitry Andric MAP(D4, 84) \ 510b57cec5SDimitry Andric MAP(D5, 85) \ 520b57cec5SDimitry Andric MAP(D6, 86) \ 530b57cec5SDimitry Andric MAP(D7, 87) \ 540b57cec5SDimitry Andric MAP(D8, 88) \ 550b57cec5SDimitry Andric MAP(D9, 89) \ 560b57cec5SDimitry Andric MAP(DA, 90) \ 570b57cec5SDimitry Andric MAP(DB, 91) \ 580b57cec5SDimitry Andric MAP(DC, 92) \ 590b57cec5SDimitry Andric MAP(DD, 93) \ 600b57cec5SDimitry Andric MAP(DE, 94) \ 610b57cec5SDimitry Andric MAP(DF, 95) \ 620b57cec5SDimitry Andric MAP(E0, 96) \ 630b57cec5SDimitry Andric MAP(E1, 97) \ 640b57cec5SDimitry Andric MAP(E2, 98) \ 650b57cec5SDimitry Andric MAP(E3, 99) \ 660b57cec5SDimitry Andric MAP(E4, 100) \ 670b57cec5SDimitry Andric MAP(E5, 101) \ 680b57cec5SDimitry Andric MAP(E6, 102) \ 690b57cec5SDimitry Andric MAP(E7, 103) \ 700b57cec5SDimitry Andric MAP(E8, 104) \ 710b57cec5SDimitry Andric MAP(E9, 105) \ 720b57cec5SDimitry Andric MAP(EA, 106) \ 730b57cec5SDimitry Andric MAP(EB, 107) \ 740b57cec5SDimitry Andric MAP(EC, 108) \ 750b57cec5SDimitry Andric MAP(ED, 109) \ 760b57cec5SDimitry Andric MAP(EE, 110) \ 770b57cec5SDimitry Andric MAP(EF, 111) \ 780b57cec5SDimitry Andric MAP(F0, 112) \ 790b57cec5SDimitry Andric MAP(F1, 113) \ 800b57cec5SDimitry Andric MAP(F2, 114) \ 810b57cec5SDimitry Andric MAP(F3, 115) \ 820b57cec5SDimitry Andric MAP(F4, 116) \ 830b57cec5SDimitry Andric MAP(F5, 117) \ 840b57cec5SDimitry Andric MAP(F6, 118) \ 850b57cec5SDimitry Andric MAP(F7, 119) \ 860b57cec5SDimitry Andric MAP(F8, 120) \ 870b57cec5SDimitry Andric MAP(F9, 121) \ 880b57cec5SDimitry Andric MAP(FA, 122) \ 890b57cec5SDimitry Andric MAP(FB, 123) \ 900b57cec5SDimitry Andric MAP(FC, 124) \ 910b57cec5SDimitry Andric MAP(FD, 125) \ 920b57cec5SDimitry Andric MAP(FE, 126) \ 930b57cec5SDimitry Andric MAP(FF, 127) 940b57cec5SDimitry Andric 950b57cec5SDimitry Andric // A clone of X86 since we can't depend on something that is generated. 960b57cec5SDimitry Andric namespace X86Local { 970b57cec5SDimitry Andric enum { 980b57cec5SDimitry Andric Pseudo = 0, 990b57cec5SDimitry Andric RawFrm = 1, 1000b57cec5SDimitry Andric AddRegFrm = 2, 1010b57cec5SDimitry Andric RawFrmMemOffs = 3, 1020b57cec5SDimitry Andric RawFrmSrc = 4, 1030b57cec5SDimitry Andric RawFrmDst = 5, 1040b57cec5SDimitry Andric RawFrmDstSrc = 6, 1050b57cec5SDimitry Andric RawFrmImm8 = 7, 1060b57cec5SDimitry Andric RawFrmImm16 = 8, 1070b57cec5SDimitry Andric AddCCFrm = 9, 1085ffd83dbSDimitry Andric PrefixByte = 10, 109*0fca6ea1SDimitry Andric MRMDestRegCC = 18, 110*0fca6ea1SDimitry Andric MRMDestMemCC = 19, 111bdd1243dSDimitry Andric MRMDestMem4VOp3CC = 20, 1125ffd83dbSDimitry Andric MRMr0 = 21, 1135ffd83dbSDimitry Andric MRMSrcMemFSIB = 22, 1145ffd83dbSDimitry Andric MRMDestMemFSIB = 23, 1155ffd83dbSDimitry Andric MRMDestMem = 24, 1165ffd83dbSDimitry Andric MRMSrcMem = 25, 1175ffd83dbSDimitry Andric MRMSrcMem4VOp3 = 26, 1185ffd83dbSDimitry Andric MRMSrcMemOp4 = 27, 1195ffd83dbSDimitry Andric MRMSrcMemCC = 28, 1205f757f3fSDimitry Andric MRMXmCC = 30, 1215f757f3fSDimitry Andric MRMXm = 31, 1225f757f3fSDimitry Andric MRM0m = 32, 1235f757f3fSDimitry Andric MRM1m = 33, 1245f757f3fSDimitry Andric MRM2m = 34, 1255f757f3fSDimitry Andric MRM3m = 35, 1265f757f3fSDimitry Andric MRM4m = 36, 1275f757f3fSDimitry Andric MRM5m = 37, 1285f757f3fSDimitry Andric MRM6m = 38, 1295f757f3fSDimitry Andric MRM7m = 39, 1305ffd83dbSDimitry Andric MRMDestReg = 40, 1315ffd83dbSDimitry Andric MRMSrcReg = 41, 1325ffd83dbSDimitry Andric MRMSrcReg4VOp3 = 42, 1335ffd83dbSDimitry Andric MRMSrcRegOp4 = 43, 1345ffd83dbSDimitry Andric MRMSrcRegCC = 44, 1355f757f3fSDimitry Andric MRMXrCC = 46, 1365f757f3fSDimitry Andric MRMXr = 47, 1375f757f3fSDimitry Andric MRM0r = 48, 1385f757f3fSDimitry Andric MRM1r = 49, 1395f757f3fSDimitry Andric MRM2r = 50, 1405f757f3fSDimitry Andric MRM3r = 51, 1415f757f3fSDimitry Andric MRM4r = 52, 1425f757f3fSDimitry Andric MRM5r = 53, 1435f757f3fSDimitry Andric MRM6r = 54, 1445f757f3fSDimitry Andric MRM7r = 55, 1455f757f3fSDimitry Andric MRM0X = 56, 1465f757f3fSDimitry Andric MRM1X = 57, 1475f757f3fSDimitry Andric MRM2X = 58, 1485f757f3fSDimitry Andric MRM3X = 59, 1495f757f3fSDimitry Andric MRM4X = 60, 1505f757f3fSDimitry Andric MRM5X = 61, 1515f757f3fSDimitry Andric MRM6X = 62, 1525f757f3fSDimitry Andric MRM7X = 63, 1530b57cec5SDimitry Andric #define MAP(from, to) MRM_##from = to, 1540b57cec5SDimitry Andric X86_INSTR_MRM_MAPPING 1550b57cec5SDimitry Andric #undef MAP 1560b57cec5SDimitry Andric }; 1570b57cec5SDimitry Andric 1580b57cec5SDimitry Andric enum { 1595f757f3fSDimitry Andric OB = 0, 1605f757f3fSDimitry Andric TB = 1, 1615f757f3fSDimitry Andric T8 = 2, 1625f757f3fSDimitry Andric TA = 3, 1635f757f3fSDimitry Andric XOP8 = 4, 1645f757f3fSDimitry Andric XOP9 = 5, 1655f757f3fSDimitry Andric XOPA = 6, 1665f757f3fSDimitry Andric ThreeDNow = 7, 1675f757f3fSDimitry Andric T_MAP4 = 8, 1685f757f3fSDimitry Andric T_MAP5 = 9, 1695f757f3fSDimitry Andric T_MAP6 = 10, 1705f757f3fSDimitry Andric T_MAP7 = 11 1710b57cec5SDimitry Andric }; 1720b57cec5SDimitry Andric 1735f757f3fSDimitry Andric enum { PD = 1, XS = 2, XD = 3, PS = 4 }; 1745f757f3fSDimitry Andric enum { VEX = 1, XOP = 2, EVEX = 3 }; 1755f757f3fSDimitry Andric enum { OpSize16 = 1, OpSize32 = 2 }; 1765f757f3fSDimitry Andric enum { AdSize16 = 1, AdSize32 = 2, AdSize64 = 3 }; 177647cbc5dSDimitry Andric enum { ExplicitREX2 = 1, ExplicitEVEX = 3 }; 1785f757f3fSDimitry Andric } // namespace X86Local 1790b57cec5SDimitry Andric 1800b57cec5SDimitry Andric namespace X86Disassembler { 1811fd87a68SDimitry Andric class DisassemblerTables; 18281ad6265SDimitry Andric /// Extract common fields of a single X86 instruction from a CodeGenInstruction 18381ad6265SDimitry Andric struct RecognizableInstrBase { 1840b57cec5SDimitry Andric /// The OpPrefix field from the record 1850b57cec5SDimitry Andric uint8_t OpPrefix; 1860b57cec5SDimitry Andric /// The OpMap field from the record 1870b57cec5SDimitry Andric uint8_t OpMap; 1880b57cec5SDimitry Andric /// The opcode field from the record; this is the opcode used in the Intel 1890b57cec5SDimitry Andric /// encoding and therefore distinct from the UID 1900b57cec5SDimitry Andric uint8_t Opcode; 1910b57cec5SDimitry Andric /// The form field from the record 1920b57cec5SDimitry Andric uint8_t Form; 1930b57cec5SDimitry Andric // The encoding field from the record 1940b57cec5SDimitry Andric uint8_t Encoding; 1950b57cec5SDimitry Andric /// The OpSize field from the record 1960b57cec5SDimitry Andric uint8_t OpSize; 1970b57cec5SDimitry Andric /// The AdSize field from the record 1980b57cec5SDimitry Andric uint8_t AdSize; 19981ad6265SDimitry Andric /// The hasREX_W field from the record 20081ad6265SDimitry Andric bool HasREX_W; 2010b57cec5SDimitry Andric /// The hasVEX_4V field from the record 2020b57cec5SDimitry Andric bool HasVEX_4V; 20306c3fb27SDimitry Andric /// The IgnoresW field from the record 20406c3fb27SDimitry Andric bool IgnoresW; 20581ad6265SDimitry Andric /// The hasVEX_L field from the record 20681ad6265SDimitry Andric bool HasVEX_L; 2070b57cec5SDimitry Andric /// The ignoreVEX_L field from the record 2080b57cec5SDimitry Andric bool IgnoresVEX_L; 2090b57cec5SDimitry Andric /// The hasEVEX_L2Prefix field from the record 21081ad6265SDimitry Andric bool HasEVEX_L2; 2110b57cec5SDimitry Andric /// The hasEVEX_K field from the record 2120b57cec5SDimitry Andric bool HasEVEX_K; 2130b57cec5SDimitry Andric /// The hasEVEX_KZ field from the record 2140b57cec5SDimitry Andric bool HasEVEX_KZ; 2150b57cec5SDimitry Andric /// The hasEVEX_B field from the record 2160b57cec5SDimitry Andric bool HasEVEX_B; 217647cbc5dSDimitry Andric /// The hasEVEX_NF field from the record 218647cbc5dSDimitry Andric bool HasEVEX_NF; 219*0fca6ea1SDimitry Andric /// The hasTwoConditionalOps field from the record 220*0fca6ea1SDimitry Andric bool HasTwoConditionalOps; 2210b57cec5SDimitry Andric /// Indicates that the instruction uses the L and L' fields for RC. 2220b57cec5SDimitry Andric bool EncodeRC; 2230b57cec5SDimitry Andric /// The isCodeGenOnly field from the record 2240b57cec5SDimitry Andric bool IsCodeGenOnly; 22581ad6265SDimitry Andric /// The isAsmParserOnly field from the record 22681ad6265SDimitry Andric bool IsAsmParserOnly; 2270b57cec5SDimitry Andric /// The ForceDisassemble field from the record 2280b57cec5SDimitry Andric bool ForceDisassemble; 2290b57cec5SDimitry Andric // The CD8_Scale field from the record 2300b57cec5SDimitry Andric uint8_t CD8_Scale; 2315f757f3fSDimitry Andric /// If explicitOpPrefix field from the record equals ExplicitREX2 2325f757f3fSDimitry Andric bool ExplicitREX2Prefix; 23381ad6265SDimitry Andric /// \param insn The CodeGenInstruction to extract information from. 23481ad6265SDimitry Andric RecognizableInstrBase(const CodeGenInstruction &insn); 23581ad6265SDimitry Andric /// \returns true if this instruction should be emitted 23681ad6265SDimitry Andric bool shouldBeEmitted() const; 23781ad6265SDimitry Andric }; 2380b57cec5SDimitry Andric 23981ad6265SDimitry Andric /// RecognizableInstr - Encapsulates all information required to decode a single 24081ad6265SDimitry Andric /// instruction, as extracted from the LLVM instruction tables. Has methods 24181ad6265SDimitry Andric /// to interpret the information available in the LLVM tables, and to emit the 24281ad6265SDimitry Andric /// instruction into DisassemblerTables. 24381ad6265SDimitry Andric class RecognizableInstr : public RecognizableInstrBase { 24481ad6265SDimitry Andric private: 24581ad6265SDimitry Andric /// The record from the .td files corresponding to this instruction 24681ad6265SDimitry Andric const Record *Rec; 2470b57cec5SDimitry Andric /// The instruction name as listed in the tables 2480b57cec5SDimitry Andric std::string Name; 24981ad6265SDimitry Andric // Whether the instruction has the predicate "In32BitMode" 25081ad6265SDimitry Andric bool Is32Bit; 25181ad6265SDimitry Andric // Whether the instruction has the predicate "In64BitMode" 25281ad6265SDimitry Andric bool Is64Bit; 2530b57cec5SDimitry Andric /// The operands of the instruction, as listed in the CodeGenInstruction. 2540b57cec5SDimitry Andric /// They are not one-to-one with operands listed in the MCInst; for example, 2550b57cec5SDimitry Andric /// memory operands expand to 5 operands in the MCInst 2560b57cec5SDimitry Andric const std::vector<CGIOperandList::OperandInfo> *Operands; 2570b57cec5SDimitry Andric 25881ad6265SDimitry Andric /// The opcode of the instruction, as used in an MCInst 25981ad6265SDimitry Andric InstrUID UID; 2600b57cec5SDimitry Andric /// The description of the instruction that is emitted into the instruction 2610b57cec5SDimitry Andric /// info table 2620b57cec5SDimitry Andric InstructionSpecifier *Spec; 2630b57cec5SDimitry Andric 2640b57cec5SDimitry Andric /// insnContext - Returns the primary context in which the instruction is 2650b57cec5SDimitry Andric /// valid. 2660b57cec5SDimitry Andric /// 2670b57cec5SDimitry Andric /// @return - The context in which the instruction is valid. 2680b57cec5SDimitry Andric InstructionContext insnContext() const; 2690b57cec5SDimitry Andric 2700b57cec5SDimitry Andric /// typeFromString - Translates an operand type from the string provided in 2710b57cec5SDimitry Andric /// the LLVM tables to an OperandType for use in the operand specifier. 2720b57cec5SDimitry Andric /// 2730b57cec5SDimitry Andric /// @param s - The string, as extracted by calling Rec->getName() 2740b57cec5SDimitry Andric /// on a CodeGenInstruction::OperandInfo. 27581ad6265SDimitry Andric /// @param hasREX_W - Indicates whether the instruction has a REX.W 2760b57cec5SDimitry Andric /// prefix. If it does, 32-bit register operands stay 2770b57cec5SDimitry Andric /// 32-bit regardless of the operand size. 2780b57cec5SDimitry Andric /// @param OpSize Indicates the operand size of the instruction. 2790b57cec5SDimitry Andric /// If register size does not match OpSize, then 2800b57cec5SDimitry Andric /// register sizes keep their size. 2810b57cec5SDimitry Andric /// @return - The operand's type. 2825f757f3fSDimitry Andric static OperandType typeFromString(const std::string &s, bool hasREX_W, 2835f757f3fSDimitry Andric uint8_t OpSize); 2840b57cec5SDimitry Andric 2850b57cec5SDimitry Andric /// immediateEncodingFromString - Translates an immediate encoding from the 2860b57cec5SDimitry Andric /// string provided in the LLVM tables to an OperandEncoding for use in 2870b57cec5SDimitry Andric /// the operand specifier. 2880b57cec5SDimitry Andric /// 2890b57cec5SDimitry Andric /// @param s - See typeFromString(). 2900b57cec5SDimitry Andric /// @param OpSize - Indicates whether this is an OpSize16 instruction. 2910b57cec5SDimitry Andric /// If it is not, then 16-bit immediate operands stay 16-bit. 2920b57cec5SDimitry Andric /// @return - The operand's encoding. 2930b57cec5SDimitry Andric static OperandEncoding immediateEncodingFromString(const std::string &s, 2940b57cec5SDimitry Andric uint8_t OpSize); 2950b57cec5SDimitry Andric 2960b57cec5SDimitry Andric /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 2970b57cec5SDimitry Andric /// handles operands that are in the REG field of the ModR/M byte. 2980b57cec5SDimitry Andric static OperandEncoding rmRegisterEncodingFromString(const std::string &s, 2990b57cec5SDimitry Andric uint8_t OpSize); 3000b57cec5SDimitry Andric 3010b57cec5SDimitry Andric /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 3020b57cec5SDimitry Andric /// handles operands that are in the REG field of the ModR/M byte. 3030b57cec5SDimitry Andric static OperandEncoding roRegisterEncodingFromString(const std::string &s, 3040b57cec5SDimitry Andric uint8_t OpSize); 3050b57cec5SDimitry Andric static OperandEncoding memoryEncodingFromString(const std::string &s, 3060b57cec5SDimitry Andric uint8_t OpSize); 3070b57cec5SDimitry Andric static OperandEncoding relocationEncodingFromString(const std::string &s, 3080b57cec5SDimitry Andric uint8_t OpSize); 3090b57cec5SDimitry Andric static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, 3100b57cec5SDimitry Andric uint8_t OpSize); 3110b57cec5SDimitry Andric static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, 3120b57cec5SDimitry Andric uint8_t OpSize); 3135f757f3fSDimitry Andric static OperandEncoding 3145f757f3fSDimitry Andric writemaskRegisterEncodingFromString(const std::string &s, uint8_t OpSize); 3150b57cec5SDimitry Andric 3160b57cec5SDimitry Andric /// Adjust the encoding type for an operand based on the instruction. 3170b57cec5SDimitry Andric void adjustOperandEncoding(OperandEncoding &encoding); 3180b57cec5SDimitry Andric 3190b57cec5SDimitry Andric /// handleOperand - Converts a single operand from the LLVM table format to 3200b57cec5SDimitry Andric /// the emitted table format, handling any duplicate operands it encounters 3210b57cec5SDimitry Andric /// and then one non-duplicate. 3220b57cec5SDimitry Andric /// 3230b57cec5SDimitry Andric /// @param optional - Determines whether to assert that the 3240b57cec5SDimitry Andric /// operand exists. 3250b57cec5SDimitry Andric /// @param operandIndex - The index into the generated operand table. 3260b57cec5SDimitry Andric /// Incremented by this function one or more 3270b57cec5SDimitry Andric /// times to reflect possible duplicate 3280b57cec5SDimitry Andric /// operands). 3290b57cec5SDimitry Andric /// @param physicalOperandIndex - The index of the current operand into the 3300b57cec5SDimitry Andric /// set of non-duplicate ('physical') operands. 3310b57cec5SDimitry Andric /// Incremented by this function once. 3320b57cec5SDimitry Andric /// @param numPhysicalOperands - The number of non-duplicate operands in the 3330b57cec5SDimitry Andric /// instructions. 3340b57cec5SDimitry Andric /// @param operandMapping - The operand mapping, which has an entry for 3350b57cec5SDimitry Andric /// each operand that indicates whether it is a 3360b57cec5SDimitry Andric /// duplicate, and of what. 3375f757f3fSDimitry Andric void handleOperand(bool optional, unsigned &operandIndex, 3380b57cec5SDimitry Andric unsigned &physicalOperandIndex, 3390b57cec5SDimitry Andric unsigned numPhysicalOperands, 3400b57cec5SDimitry Andric const unsigned *operandMapping, 3415f757f3fSDimitry Andric OperandEncoding (*encodingFromString)(const std::string &, 3420b57cec5SDimitry Andric uint8_t OpSize)); 3430b57cec5SDimitry Andric 3440b57cec5SDimitry Andric /// emitInstructionSpecifier - Loads the instruction specifier for the current 3450b57cec5SDimitry Andric /// instruction into a DisassemblerTables. 3460b57cec5SDimitry Andric /// 3470b57cec5SDimitry Andric void emitInstructionSpecifier(); 3480b57cec5SDimitry Andric 3490b57cec5SDimitry Andric /// emitDecodePath - Populates the proper fields in the decode tables 3500b57cec5SDimitry Andric /// corresponding to the decode paths for this instruction. 3510b57cec5SDimitry Andric /// 3520b57cec5SDimitry Andric /// \param tables The DisassemblerTables to populate with the decode 3530b57cec5SDimitry Andric /// decode information for the current instruction. 3540b57cec5SDimitry Andric void emitDecodePath(DisassemblerTables &tables) const; 3550b57cec5SDimitry Andric 35681ad6265SDimitry Andric public: 3570b57cec5SDimitry Andric /// Constructor - Initializes a RecognizableInstr with the appropriate fields 3580b57cec5SDimitry Andric /// from a CodeGenInstruction. 3590b57cec5SDimitry Andric /// 3600b57cec5SDimitry Andric /// \param tables The DisassemblerTables that the specifier will be added to. 3610b57cec5SDimitry Andric /// \param insn The CodeGenInstruction to extract information from. 3620b57cec5SDimitry Andric /// \param uid The unique ID of the current instruction. 3635f757f3fSDimitry Andric RecognizableInstr(DisassemblerTables &tables, const CodeGenInstruction &insn, 3640b57cec5SDimitry Andric InstrUID uid); 3650b57cec5SDimitry Andric /// processInstr - Accepts a CodeGenInstruction and loads decode information 3660b57cec5SDimitry Andric /// for it into a DisassemblerTables if appropriate. 3670b57cec5SDimitry Andric /// 3680b57cec5SDimitry Andric /// \param tables The DiassemblerTables to be populated with decode 3690b57cec5SDimitry Andric /// information. 3700b57cec5SDimitry Andric /// \param insn The CodeGenInstruction to be used as a source for this 3710b57cec5SDimitry Andric /// information. 3720b57cec5SDimitry Andric /// \param uid The unique ID of the instruction. 3730b57cec5SDimitry Andric static void processInstr(DisassemblerTables &tables, 3745f757f3fSDimitry Andric const CodeGenInstruction &insn, InstrUID uid); 3750b57cec5SDimitry Andric }; 3760b57cec5SDimitry Andric 37781ad6265SDimitry Andric std::string getMnemonic(const CodeGenInstruction *I, unsigned Variant); 37881ad6265SDimitry Andric bool isRegisterOperand(const Record *Rec); 37981ad6265SDimitry Andric bool isMemoryOperand(const Record *Rec); 38081ad6265SDimitry Andric bool isImmediateOperand(const Record *Rec); 38181ad6265SDimitry Andric unsigned getRegOperandSize(const Record *RegRec); 38281ad6265SDimitry Andric unsigned getMemOperandSize(const Record *MemRec); 3830b57cec5SDimitry Andric } // namespace X86Disassembler 3840b57cec5SDimitry Andric } // namespace llvm 3850b57cec5SDimitry Andric #endif 386