10b57cec5SDimitry Andric //===- X86DisassemblerShared.h - Emitter shared header ----------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric 90b57cec5SDimitry Andric #ifndef LLVM_UTILS_TABLEGEN_X86DISASSEMBLERSHARED_H 100b57cec5SDimitry Andric #define LLVM_UTILS_TABLEGEN_X86DISASSEMBLERSHARED_H 110b57cec5SDimitry Andric 120b57cec5SDimitry Andric #include <cstring> 130b57cec5SDimitry Andric #include <string> 140b57cec5SDimitry Andric 150b57cec5SDimitry Andric #include "llvm/Support/X86DisassemblerDecoderCommon.h" 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric struct InstructionSpecifier { 180b57cec5SDimitry Andric llvm::X86Disassembler::OperandSpecifier 190b57cec5SDimitry Andric operands[llvm::X86Disassembler::X86_MAX_OPERANDS]; 200b57cec5SDimitry Andric llvm::X86Disassembler::InstructionContext insnContext; 210b57cec5SDimitry Andric std::string name; 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric InstructionSpecifier() { 240b57cec5SDimitry Andric insnContext = llvm::X86Disassembler::IC; 250b57cec5SDimitry Andric name = ""; 260b57cec5SDimitry Andric memset(operands, 0, sizeof(operands)); 270b57cec5SDimitry Andric } 280b57cec5SDimitry Andric }; 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric /// Specifies whether a ModR/M byte is needed and (if so) which 310b57cec5SDimitry Andric /// instruction each possible value of the ModR/M byte corresponds to. Once 320b57cec5SDimitry Andric /// this information is known, we have narrowed down to a single instruction. 330b57cec5SDimitry Andric struct ModRMDecision { 340b57cec5SDimitry Andric uint8_t modrm_type; 350b57cec5SDimitry Andric llvm::X86Disassembler::InstrUID instructionIDs[256]; 360b57cec5SDimitry Andric }; 370b57cec5SDimitry Andric 380b57cec5SDimitry Andric /// Specifies which set of ModR/M->instruction tables to look at 390b57cec5SDimitry Andric /// given a particular opcode. 400b57cec5SDimitry Andric struct OpcodeDecision { 410b57cec5SDimitry Andric ModRMDecision modRMDecisions[256]; 420b57cec5SDimitry Andric }; 430b57cec5SDimitry Andric 440b57cec5SDimitry Andric /// Specifies which opcode->instruction tables to look at given 450b57cec5SDimitry Andric /// a particular context (set of attributes). Since there are many possible 460b57cec5SDimitry Andric /// contexts, the decoder first uses CONTEXTS_SYM to determine which context 470b57cec5SDimitry Andric /// applies given a specific set of attributes. Hence there are only IC_max 480b57cec5SDimitry Andric /// entries in this table, rather than 2^(ATTR_max). 490b57cec5SDimitry Andric struct ContextDecision { 500b57cec5SDimitry Andric OpcodeDecision opcodeDecisions[llvm::X86Disassembler::IC_max]; 510b57cec5SDimitry Andric 52*0fca6ea1SDimitry Andric ContextDecision() { memset(opcodeDecisions, 0, sizeof(opcodeDecisions)); } 530b57cec5SDimitry Andric }; 540b57cec5SDimitry Andric 550b57cec5SDimitry Andric #endif 56