10b57cec5SDimitry Andric //===--------------------- DispatchStatistics.h -----------------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric /// \file 90b57cec5SDimitry Andric /// 100b57cec5SDimitry Andric /// This file implements a view that prints a few statistics related to the 110b57cec5SDimitry Andric /// dispatch logic. It collects and analyzes instruction dispatch events as 120b57cec5SDimitry Andric /// well as static/dynamic dispatch stall events. 130b57cec5SDimitry Andric /// 140b57cec5SDimitry Andric /// Example: 150b57cec5SDimitry Andric /// ======== 160b57cec5SDimitry Andric /// 170b57cec5SDimitry Andric /// Dynamic Dispatch Stall Cycles: 180b57cec5SDimitry Andric /// RAT - Register unavailable: 0 190b57cec5SDimitry Andric /// RCU - Retire tokens unavailable: 0 200b57cec5SDimitry Andric /// SCHEDQ - Scheduler full: 42 210b57cec5SDimitry Andric /// LQ - Load queue full: 0 220b57cec5SDimitry Andric /// SQ - Store queue full: 0 230b57cec5SDimitry Andric /// GROUP - Static restrictions on the dispatch group: 0 240b57cec5SDimitry Andric /// 250b57cec5SDimitry Andric /// 260b57cec5SDimitry Andric /// Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: 270b57cec5SDimitry Andric /// [# dispatched], [# cycles] 280b57cec5SDimitry Andric /// 0, 15 (11.5%) 290b57cec5SDimitry Andric /// 2, 4 (3.1%) 300b57cec5SDimitry Andric /// 310b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 320b57cec5SDimitry Andric 330b57cec5SDimitry Andric #ifndef LLVM_TOOLS_LLVM_MCA_DISPATCHVIEW_H 340b57cec5SDimitry Andric #define LLVM_TOOLS_LLVM_MCA_DISPATCHVIEW_H 350b57cec5SDimitry Andric 360b57cec5SDimitry Andric #include "llvm/ADT/SmallVector.h" 370b57cec5SDimitry Andric #include "llvm/MC/MCSubtargetInfo.h" 38*349cc55cSDimitry Andric #include "llvm/MCA/View.h" 390b57cec5SDimitry Andric #include <map> 400b57cec5SDimitry Andric 410b57cec5SDimitry Andric namespace llvm { 420b57cec5SDimitry Andric namespace mca { 430b57cec5SDimitry Andric 440b57cec5SDimitry Andric class DispatchStatistics : public View { 450b57cec5SDimitry Andric unsigned NumDispatched; 460b57cec5SDimitry Andric unsigned NumCycles; 470b57cec5SDimitry Andric 480b57cec5SDimitry Andric // Counts dispatch stall events caused by unavailability of resources. There 490b57cec5SDimitry Andric // is one counter for every generic stall kind (see class HWStallEvent). 500b57cec5SDimitry Andric llvm::SmallVector<unsigned, 8> HWStalls; 510b57cec5SDimitry Andric 520b57cec5SDimitry Andric using Histogram = std::map<unsigned, unsigned>; 530b57cec5SDimitry Andric Histogram DispatchGroupSizePerCycle; 540b57cec5SDimitry Andric updateHistograms()550b57cec5SDimitry Andric void updateHistograms() { 560b57cec5SDimitry Andric DispatchGroupSizePerCycle[NumDispatched]++; 570b57cec5SDimitry Andric NumDispatched = 0; 580b57cec5SDimitry Andric } 590b57cec5SDimitry Andric 600b57cec5SDimitry Andric void printDispatchHistogram(llvm::raw_ostream &OS) const; 610b57cec5SDimitry Andric 620b57cec5SDimitry Andric void printDispatchStalls(llvm::raw_ostream &OS) const; 630b57cec5SDimitry Andric 640b57cec5SDimitry Andric public: DispatchStatistics()650b57cec5SDimitry Andric DispatchStatistics() 660b57cec5SDimitry Andric : NumDispatched(0), NumCycles(0), 670b57cec5SDimitry Andric HWStalls(HWStallEvent::LastGenericEvent) {} 680b57cec5SDimitry Andric 690b57cec5SDimitry Andric void onEvent(const HWStallEvent &Event) override; 700b57cec5SDimitry Andric 710b57cec5SDimitry Andric void onEvent(const HWInstructionEvent &Event) override; 720b57cec5SDimitry Andric onCycleBegin()730b57cec5SDimitry Andric void onCycleBegin() override { NumCycles++; } 740b57cec5SDimitry Andric onCycleEnd()750b57cec5SDimitry Andric void onCycleEnd() override { updateHistograms(); } 760b57cec5SDimitry Andric printView(llvm::raw_ostream & OS)770b57cec5SDimitry Andric void printView(llvm::raw_ostream &OS) const override { 780b57cec5SDimitry Andric printDispatchStalls(OS); 790b57cec5SDimitry Andric printDispatchHistogram(OS); 800b57cec5SDimitry Andric } getNameAsString()81e8d8bef9SDimitry Andric StringRef getNameAsString() const override { return "DispatchStatistics"; } 82fe6060f1SDimitry Andric json::Value toJSON() const override; 830b57cec5SDimitry Andric }; 840b57cec5SDimitry Andric } // namespace mca 850b57cec5SDimitry Andric } // namespace llvm 860b57cec5SDimitry Andric 870b57cec5SDimitry Andric #endif 88