10b57cec5SDimitry Andric//===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file describes the instructions that make up the Intel TSX instruction 100b57cec5SDimitry Andric// set. 110b57cec5SDimitry Andric// 120b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 150b57cec5SDimitry Andric// TSX instructions 160b57cec5SDimitry Andric 170b57cec5SDimitry Andricdef X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>, 180b57cec5SDimitry Andric [SDNPHasChain, SDNPSideEffect]>; 190b57cec5SDimitry Andric 200b57cec5SDimitry Andriclet SchedRW = [WriteSystem] in { 210b57cec5SDimitry Andric 220b57cec5SDimitry Andriclet usesCustomInserter = 1 in 230b57cec5SDimitry Andricdef XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins), 240b57cec5SDimitry Andric "# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>, 250b57cec5SDimitry Andric Requires<[HasRTM]>; 260b57cec5SDimitry Andric 270b57cec5SDimitry Andriclet isBranch = 1, isTerminator = 1, Defs = [EAX] in { 280b57cec5SDimitry Andricdef XBEGIN_2 : Ii16PCRel<0xc7, MRM_F8, (outs), (ins brtarget16:$dst), 290b57cec5SDimitry Andric "xbegin\t$dst", []>, OpSize16; 300b57cec5SDimitry Andricdef XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst), 310b57cec5SDimitry Andric "xbegin\t$dst", []>, OpSize32; 320b57cec5SDimitry Andric} 330b57cec5SDimitry Andric 34480093f4SDimitry Andric// Pseudo instruction to fake the definition of EAX on the fallback code path. 350b57cec5SDimitry Andriclet isPseudo = 1, Defs = [EAX] in { 360b57cec5SDimitry Andricdef XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>; 370b57cec5SDimitry Andric} 380b57cec5SDimitry Andric 390b57cec5SDimitry Andricdef XEND : I<0x01, MRM_D5, (outs), (ins), 40*cb14a3feSDimitry Andric "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>; 410b57cec5SDimitry Andric 420b57cec5SDimitry Andriclet Defs = [EFLAGS] in 430b57cec5SDimitry Andricdef XTEST : I<0x01, MRM_D6, (outs), (ins), 44*cb14a3feSDimitry Andric "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasRTM]>; 450b57cec5SDimitry Andric 460b57cec5SDimitry Andricdef XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm), 470b57cec5SDimitry Andric "xabort\t$imm", 488bcb0991SDimitry Andric [(int_x86_xabort timm:$imm)]>, Requires<[HasRTM]>; 490b57cec5SDimitry Andric} // SchedRW 500b57cec5SDimitry Andric 510b57cec5SDimitry Andric// HLE prefixes 520b57cec5SDimitry Andriclet SchedRW = [WriteSystem] in { 530b57cec5SDimitry Andric 5481ad6265SDimitry Andric// XACQUIRE and XRELEASE reuse REPNE and REP respectively. 5581ad6265SDimitry Andric// For now, just prefer the REP versions. 560b57cec5SDimitry Andriclet isAsmParserOnly = 1 in { 575ffd83dbSDimitry Andricdef XACQUIRE_PREFIX : I<0xF2, PrefixByte, (outs), (ins), "xacquire", []>; 585ffd83dbSDimitry Andricdef XRELEASE_PREFIX : I<0xF3, PrefixByte, (outs), (ins), "xrelease", []>; 590b57cec5SDimitry Andric} 600b57cec5SDimitry Andric 610b57cec5SDimitry Andric} // SchedRW 62