1bdd1243dSDimitry Andric//===---- X86InstrRAOINT.td -------------------------------*- tablegen -*--===// 2bdd1243dSDimitry Andric// 3bdd1243dSDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4bdd1243dSDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5bdd1243dSDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6bdd1243dSDimitry Andric// 7bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 8bdd1243dSDimitry Andric// 9bdd1243dSDimitry Andric// This file describes the instructions that make up the Intel RAO-INT 10bdd1243dSDimitry Andric// instruction set. 11bdd1243dSDimitry Andric// 12bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 13bdd1243dSDimitry Andric 14bdd1243dSDimitry Andric//===----------------------------------------------------------------------===// 15bdd1243dSDimitry Andric// RAO-INT instructions 16bdd1243dSDimitry Andric 17bdd1243dSDimitry Andricdef SDTRAOBinaryArith : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 18bdd1243dSDimitry Andric 19bdd1243dSDimitry Andricdef X86rao_add : SDNode<"X86ISD::AADD", SDTRAOBinaryArith, 20bdd1243dSDimitry Andric [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 21bdd1243dSDimitry Andricdef X86rao_or : SDNode<"X86ISD::AOR", SDTRAOBinaryArith, 22bdd1243dSDimitry Andric [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 23bdd1243dSDimitry Andricdef X86rao_xor : SDNode<"X86ISD::AXOR", SDTRAOBinaryArith, 24bdd1243dSDimitry Andric [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 25bdd1243dSDimitry Andricdef X86rao_and : SDNode<"X86ISD::AAND", SDTRAOBinaryArith, 26bdd1243dSDimitry Andric [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 27bdd1243dSDimitry Andric 28*0fca6ea1SDimitry Andricmulticlass RaoInt<string m, string suffix = ""> { 29*0fca6ea1SDimitry Andric let Pattern = [(!cast<SDNode>("X86rao_" # m) addr:$src1, GR32:$src2)] in 30*0fca6ea1SDimitry Andric def 32mr#suffix : BinOpMR_M<0xfc, "a" # m, Xi32>; 31*0fca6ea1SDimitry Andric let Pattern = [(!cast<SDNode>("X86rao_" # m) addr:$src1, GR64:$src2)] in 32*0fca6ea1SDimitry Andric def 64mr#suffix : BinOpMR_M<0xfc, "a" # m, Xi64>; 33bdd1243dSDimitry Andric} 34bdd1243dSDimitry Andric 35*0fca6ea1SDimitry Andriclet Predicates = [HasRAOINT, NoEGPR] in { 36*0fca6ea1SDimitry Andric defm AADD : RaoInt<"add">, T8; 37*0fca6ea1SDimitry Andric defm AAND : RaoInt<"and">, T8, PD; 38*0fca6ea1SDimitry Andric defm AOR : RaoInt<"or" >, T8, XD; 39*0fca6ea1SDimitry Andric defm AXOR : RaoInt<"xor">, T8, XS; 40*0fca6ea1SDimitry Andric} 41*0fca6ea1SDimitry Andric 42*0fca6ea1SDimitry Andriclet Predicates = [HasRAOINT, HasEGPR, In64BitMode] in { 43*0fca6ea1SDimitry Andric defm AADD : RaoInt<"add", "_EVEX">, EVEX, T_MAP4; 44*0fca6ea1SDimitry Andric defm AAND : RaoInt<"and", "_EVEX">, EVEX, T_MAP4, PD; 45*0fca6ea1SDimitry Andric defm AOR : RaoInt<"or", "_EVEX">, EVEX, T_MAP4, XD; 46*0fca6ea1SDimitry Andric defm AXOR : RaoInt<"xor", "_EVEX">, EVEX, T_MAP4, XS; 47*0fca6ea1SDimitry Andric} 48