xref: /freebsd-src/contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp (revision 349cc55c9796c4596a5b9904cd3281af295f878f)
10b57cec5SDimitry Andric //===-- WebAssemblyLowerBrUnless.cpp - Lower br_unless --------------------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric ///
90b57cec5SDimitry Andric /// \file
100b57cec5SDimitry Andric /// This file lowers br_unless into br_if with an inverted condition.
110b57cec5SDimitry Andric ///
120b57cec5SDimitry Andric /// br_unless is not currently in the spec, but it's very convenient for LLVM
130b57cec5SDimitry Andric /// to use. This pass allows LLVM to use it, for now.
140b57cec5SDimitry Andric ///
150b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
160b57cec5SDimitry Andric 
170b57cec5SDimitry Andric #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
180b57cec5SDimitry Andric #include "WebAssembly.h"
190b57cec5SDimitry Andric #include "WebAssemblyMachineFunctionInfo.h"
200b57cec5SDimitry Andric #include "WebAssemblySubtarget.h"
210b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunctionPass.h"
220b57cec5SDimitry Andric #include "llvm/CodeGen/MachineInstrBuilder.h"
230b57cec5SDimitry Andric #include "llvm/Support/Debug.h"
240b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h"
250b57cec5SDimitry Andric using namespace llvm;
260b57cec5SDimitry Andric 
270b57cec5SDimitry Andric #define DEBUG_TYPE "wasm-lower-br_unless"
280b57cec5SDimitry Andric 
290b57cec5SDimitry Andric namespace {
300b57cec5SDimitry Andric class WebAssemblyLowerBrUnless final : public MachineFunctionPass {
getPassName() const310b57cec5SDimitry Andric   StringRef getPassName() const override {
320b57cec5SDimitry Andric     return "WebAssembly Lower br_unless";
330b57cec5SDimitry Andric   }
340b57cec5SDimitry Andric 
getAnalysisUsage(AnalysisUsage & AU) const350b57cec5SDimitry Andric   void getAnalysisUsage(AnalysisUsage &AU) const override {
360b57cec5SDimitry Andric     AU.setPreservesCFG();
370b57cec5SDimitry Andric     MachineFunctionPass::getAnalysisUsage(AU);
380b57cec5SDimitry Andric   }
390b57cec5SDimitry Andric 
400b57cec5SDimitry Andric   bool runOnMachineFunction(MachineFunction &MF) override;
410b57cec5SDimitry Andric 
420b57cec5SDimitry Andric public:
430b57cec5SDimitry Andric   static char ID; // Pass identification, replacement for typeid
WebAssemblyLowerBrUnless()440b57cec5SDimitry Andric   WebAssemblyLowerBrUnless() : MachineFunctionPass(ID) {}
450b57cec5SDimitry Andric };
460b57cec5SDimitry Andric } // end anonymous namespace
470b57cec5SDimitry Andric 
480b57cec5SDimitry Andric char WebAssemblyLowerBrUnless::ID = 0;
490b57cec5SDimitry Andric INITIALIZE_PASS(WebAssemblyLowerBrUnless, DEBUG_TYPE,
500b57cec5SDimitry Andric                 "Lowers br_unless into inverted br_if", false, false)
510b57cec5SDimitry Andric 
createWebAssemblyLowerBrUnless()520b57cec5SDimitry Andric FunctionPass *llvm::createWebAssemblyLowerBrUnless() {
530b57cec5SDimitry Andric   return new WebAssemblyLowerBrUnless();
540b57cec5SDimitry Andric }
550b57cec5SDimitry Andric 
runOnMachineFunction(MachineFunction & MF)560b57cec5SDimitry Andric bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) {
570b57cec5SDimitry Andric   LLVM_DEBUG(dbgs() << "********** Lowering br_unless **********\n"
580b57cec5SDimitry Andric                        "********** Function: "
590b57cec5SDimitry Andric                     << MF.getName() << '\n');
600b57cec5SDimitry Andric 
610b57cec5SDimitry Andric   auto &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
620b57cec5SDimitry Andric   const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
630b57cec5SDimitry Andric   auto &MRI = MF.getRegInfo();
640b57cec5SDimitry Andric 
650b57cec5SDimitry Andric   for (auto &MBB : MF) {
66*349cc55cSDimitry Andric     for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
67*349cc55cSDimitry Andric       if (MI.getOpcode() != WebAssembly::BR_UNLESS)
680b57cec5SDimitry Andric         continue;
690b57cec5SDimitry Andric 
70*349cc55cSDimitry Andric       Register Cond = MI.getOperand(1).getReg();
710b57cec5SDimitry Andric       bool Inverted = false;
720b57cec5SDimitry Andric 
730b57cec5SDimitry Andric       // Attempt to invert the condition in place.
740b57cec5SDimitry Andric       if (MFI.isVRegStackified(Cond)) {
750b57cec5SDimitry Andric         assert(MRI.hasOneDef(Cond));
760b57cec5SDimitry Andric         MachineInstr *Def = MRI.getVRegDef(Cond);
770b57cec5SDimitry Andric         switch (Def->getOpcode()) {
780b57cec5SDimitry Andric           using namespace WebAssembly;
790b57cec5SDimitry Andric         case EQ_I32:
800b57cec5SDimitry Andric           Def->setDesc(TII.get(NE_I32));
810b57cec5SDimitry Andric           Inverted = true;
820b57cec5SDimitry Andric           break;
830b57cec5SDimitry Andric         case NE_I32:
840b57cec5SDimitry Andric           Def->setDesc(TII.get(EQ_I32));
850b57cec5SDimitry Andric           Inverted = true;
860b57cec5SDimitry Andric           break;
870b57cec5SDimitry Andric         case GT_S_I32:
880b57cec5SDimitry Andric           Def->setDesc(TII.get(LE_S_I32));
890b57cec5SDimitry Andric           Inverted = true;
900b57cec5SDimitry Andric           break;
910b57cec5SDimitry Andric         case GE_S_I32:
920b57cec5SDimitry Andric           Def->setDesc(TII.get(LT_S_I32));
930b57cec5SDimitry Andric           Inverted = true;
940b57cec5SDimitry Andric           break;
950b57cec5SDimitry Andric         case LT_S_I32:
960b57cec5SDimitry Andric           Def->setDesc(TII.get(GE_S_I32));
970b57cec5SDimitry Andric           Inverted = true;
980b57cec5SDimitry Andric           break;
990b57cec5SDimitry Andric         case LE_S_I32:
1000b57cec5SDimitry Andric           Def->setDesc(TII.get(GT_S_I32));
1010b57cec5SDimitry Andric           Inverted = true;
1020b57cec5SDimitry Andric           break;
1030b57cec5SDimitry Andric         case GT_U_I32:
1040b57cec5SDimitry Andric           Def->setDesc(TII.get(LE_U_I32));
1050b57cec5SDimitry Andric           Inverted = true;
1060b57cec5SDimitry Andric           break;
1070b57cec5SDimitry Andric         case GE_U_I32:
1080b57cec5SDimitry Andric           Def->setDesc(TII.get(LT_U_I32));
1090b57cec5SDimitry Andric           Inverted = true;
1100b57cec5SDimitry Andric           break;
1110b57cec5SDimitry Andric         case LT_U_I32:
1120b57cec5SDimitry Andric           Def->setDesc(TII.get(GE_U_I32));
1130b57cec5SDimitry Andric           Inverted = true;
1140b57cec5SDimitry Andric           break;
1150b57cec5SDimitry Andric         case LE_U_I32:
1160b57cec5SDimitry Andric           Def->setDesc(TII.get(GT_U_I32));
1170b57cec5SDimitry Andric           Inverted = true;
1180b57cec5SDimitry Andric           break;
1190b57cec5SDimitry Andric         case EQ_I64:
1200b57cec5SDimitry Andric           Def->setDesc(TII.get(NE_I64));
1210b57cec5SDimitry Andric           Inverted = true;
1220b57cec5SDimitry Andric           break;
1230b57cec5SDimitry Andric         case NE_I64:
1240b57cec5SDimitry Andric           Def->setDesc(TII.get(EQ_I64));
1250b57cec5SDimitry Andric           Inverted = true;
1260b57cec5SDimitry Andric           break;
1270b57cec5SDimitry Andric         case GT_S_I64:
1280b57cec5SDimitry Andric           Def->setDesc(TII.get(LE_S_I64));
1290b57cec5SDimitry Andric           Inverted = true;
1300b57cec5SDimitry Andric           break;
1310b57cec5SDimitry Andric         case GE_S_I64:
1320b57cec5SDimitry Andric           Def->setDesc(TII.get(LT_S_I64));
1330b57cec5SDimitry Andric           Inverted = true;
1340b57cec5SDimitry Andric           break;
1350b57cec5SDimitry Andric         case LT_S_I64:
1360b57cec5SDimitry Andric           Def->setDesc(TII.get(GE_S_I64));
1370b57cec5SDimitry Andric           Inverted = true;
1380b57cec5SDimitry Andric           break;
1390b57cec5SDimitry Andric         case LE_S_I64:
1400b57cec5SDimitry Andric           Def->setDesc(TII.get(GT_S_I64));
1410b57cec5SDimitry Andric           Inverted = true;
1420b57cec5SDimitry Andric           break;
1430b57cec5SDimitry Andric         case GT_U_I64:
1440b57cec5SDimitry Andric           Def->setDesc(TII.get(LE_U_I64));
1450b57cec5SDimitry Andric           Inverted = true;
1460b57cec5SDimitry Andric           break;
1470b57cec5SDimitry Andric         case GE_U_I64:
1480b57cec5SDimitry Andric           Def->setDesc(TII.get(LT_U_I64));
1490b57cec5SDimitry Andric           Inverted = true;
1500b57cec5SDimitry Andric           break;
1510b57cec5SDimitry Andric         case LT_U_I64:
1520b57cec5SDimitry Andric           Def->setDesc(TII.get(GE_U_I64));
1530b57cec5SDimitry Andric           Inverted = true;
1540b57cec5SDimitry Andric           break;
1550b57cec5SDimitry Andric         case LE_U_I64:
1560b57cec5SDimitry Andric           Def->setDesc(TII.get(GT_U_I64));
1570b57cec5SDimitry Andric           Inverted = true;
1580b57cec5SDimitry Andric           break;
1590b57cec5SDimitry Andric         case EQ_F32:
1600b57cec5SDimitry Andric           Def->setDesc(TII.get(NE_F32));
1610b57cec5SDimitry Andric           Inverted = true;
1620b57cec5SDimitry Andric           break;
1630b57cec5SDimitry Andric         case NE_F32:
1640b57cec5SDimitry Andric           Def->setDesc(TII.get(EQ_F32));
1650b57cec5SDimitry Andric           Inverted = true;
1660b57cec5SDimitry Andric           break;
1670b57cec5SDimitry Andric         case EQ_F64:
1680b57cec5SDimitry Andric           Def->setDesc(TII.get(NE_F64));
1690b57cec5SDimitry Andric           Inverted = true;
1700b57cec5SDimitry Andric           break;
1710b57cec5SDimitry Andric         case NE_F64:
1720b57cec5SDimitry Andric           Def->setDesc(TII.get(EQ_F64));
1730b57cec5SDimitry Andric           Inverted = true;
1740b57cec5SDimitry Andric           break;
1750b57cec5SDimitry Andric         case EQZ_I32: {
1760b57cec5SDimitry Andric           // Invert an eqz by replacing it with its operand.
1770b57cec5SDimitry Andric           Cond = Def->getOperand(1).getReg();
1780b57cec5SDimitry Andric           Def->eraseFromParent();
1790b57cec5SDimitry Andric           Inverted = true;
1800b57cec5SDimitry Andric           break;
1810b57cec5SDimitry Andric         }
1820b57cec5SDimitry Andric         default:
1830b57cec5SDimitry Andric           break;
1840b57cec5SDimitry Andric         }
1850b57cec5SDimitry Andric       }
1860b57cec5SDimitry Andric 
1870b57cec5SDimitry Andric       // If we weren't able to invert the condition in place. Insert an
1880b57cec5SDimitry Andric       // instruction to invert it.
1890b57cec5SDimitry Andric       if (!Inverted) {
1908bcb0991SDimitry Andric         Register Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
191*349cc55cSDimitry Andric         BuildMI(MBB, &MI, MI.getDebugLoc(), TII.get(WebAssembly::EQZ_I32), Tmp)
1920b57cec5SDimitry Andric             .addReg(Cond);
1935ffd83dbSDimitry Andric         MFI.stackifyVReg(MRI, Tmp);
1940b57cec5SDimitry Andric         Cond = Tmp;
1950b57cec5SDimitry Andric         Inverted = true;
1960b57cec5SDimitry Andric       }
1970b57cec5SDimitry Andric 
1980b57cec5SDimitry Andric       // The br_unless condition has now been inverted. Insert a br_if and
1990b57cec5SDimitry Andric       // delete the br_unless.
2000b57cec5SDimitry Andric       assert(Inverted);
201*349cc55cSDimitry Andric       BuildMI(MBB, &MI, MI.getDebugLoc(), TII.get(WebAssembly::BR_IF))
202*349cc55cSDimitry Andric           .add(MI.getOperand(0))
2030b57cec5SDimitry Andric           .addReg(Cond);
204*349cc55cSDimitry Andric       MBB.erase(&MI);
2050b57cec5SDimitry Andric     }
2060b57cec5SDimitry Andric   }
2070b57cec5SDimitry Andric 
2080b57cec5SDimitry Andric   return true;
2090b57cec5SDimitry Andric }
210