1*0fca6ea1SDimitry Andric//===-- RISCVInstrInfoSFB.td - Pseudos for SFB -------------*- tablegen -*-===// 2*0fca6ea1SDimitry Andric// 3*0fca6ea1SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0fca6ea1SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0fca6ea1SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0fca6ea1SDimitry Andric// 7*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 8*0fca6ea1SDimitry Andric// 9*0fca6ea1SDimitry Andric// This file describes the pseudos for SFB (Short Forward Branch). 10*0fca6ea1SDimitry Andric// 11*0fca6ea1SDimitry Andric//===----------------------------------------------------------------------===// 12*0fca6ea1SDimitry Andric 13*0fca6ea1SDimitry Andriclet Predicates = [HasShortForwardBranchOpt], isSelect = 1, 14*0fca6ea1SDimitry Andric Constraints = "$dst = $falsev", isCommutable = 1, Size = 8 in { 15*0fca6ea1SDimitry Andric// This instruction moves $truev to $dst when the condition is true. It will 16*0fca6ea1SDimitry Andric// be expanded to control flow in RISCVExpandPseudoInsts. 17*0fca6ea1SDimitry Andricdef PseudoCCMOVGPR : Pseudo<(outs GPR:$dst), 18*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 19*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$truev), 20*0fca6ea1SDimitry Andric [(set GPR:$dst, 21*0fca6ea1SDimitry Andric (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), 22*0fca6ea1SDimitry Andric GPR:$rhs, cond, 23*0fca6ea1SDimitry Andric (XLenVT GPR:$truev), 24*0fca6ea1SDimitry Andric GPR:$falsev))]>, 25*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, 26*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU]>; 27*0fca6ea1SDimitry Andric} 28*0fca6ea1SDimitry Andric 29*0fca6ea1SDimitry Andric// This should always expand to a branch+c.mv so the size is 6 or 4 if the 30*0fca6ea1SDimitry Andric// branch is compressible. 31*0fca6ea1SDimitry Andriclet Predicates = [HasConditionalMoveFusion, NoShortForwardBranchOpt], 32*0fca6ea1SDimitry Andric Constraints = "$dst = $falsev", isCommutable = 1, Size = 6 in { 33*0fca6ea1SDimitry Andric// This instruction moves $truev to $dst when the condition is true. It will 34*0fca6ea1SDimitry Andric// be expanded to control flow in RISCVExpandPseudoInsts. 35*0fca6ea1SDimitry Andric// We use GPRNoX0 because c.mv cannot encode X0. 36*0fca6ea1SDimitry Andricdef PseudoCCMOVGPRNoX0 : Pseudo<(outs GPRNoX0:$dst), 37*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 38*0fca6ea1SDimitry Andric GPRNoX0:$falsev, GPRNoX0:$truev), 39*0fca6ea1SDimitry Andric [(set GPRNoX0:$dst, 40*0fca6ea1SDimitry Andric (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), 41*0fca6ea1SDimitry Andric (XLenVT GPR:$rhs), 42*0fca6ea1SDimitry Andric cond, (XLenVT GPRNoX0:$truev), 43*0fca6ea1SDimitry Andric (XLenVT GPRNoX0:$falsev)))]>, 44*0fca6ea1SDimitry Andric Sched<[]>; 45*0fca6ea1SDimitry Andric} 46*0fca6ea1SDimitry Andric 47*0fca6ea1SDimitry Andric// Conditional binops, that updates update $dst to (op rs1, rs2) when condition 48*0fca6ea1SDimitry Andric// is true. Returns $falsev otherwise. Selected by optimizeSelect. 49*0fca6ea1SDimitry Andric// TODO: Can we use DefaultOperands on the regular binop to accomplish this more 50*0fca6ea1SDimitry Andric// like how ARM does predication? 51*0fca6ea1SDimitry Andriclet Predicates = [HasShortForwardBranchOpt], hasSideEffects = 0, 52*0fca6ea1SDimitry Andric mayLoad = 0, mayStore = 0, Size = 8, Constraints = "$dst = $falsev" in { 53*0fca6ea1SDimitry Andricdef PseudoCCADD : Pseudo<(outs GPR:$dst), 54*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 55*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 56*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, 57*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU, ReadSFBALU]>; 58*0fca6ea1SDimitry Andricdef PseudoCCSUB : Pseudo<(outs GPR:$dst), 59*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 60*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 61*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, 62*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU, ReadSFBALU]>; 63*0fca6ea1SDimitry Andricdef PseudoCCSLL : Pseudo<(outs GPR:$dst), 64*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 65*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 66*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 67*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU]>; 68*0fca6ea1SDimitry Andricdef PseudoCCSRL : Pseudo<(outs GPR:$dst), 69*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 70*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 71*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 72*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU]>; 73*0fca6ea1SDimitry Andricdef PseudoCCSRA : Pseudo<(outs GPR:$dst), 74*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 75*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 76*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 77*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU]>; 78*0fca6ea1SDimitry Andricdef PseudoCCAND : Pseudo<(outs GPR:$dst), 79*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 80*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 81*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, 82*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU, ReadSFBALU]>; 83*0fca6ea1SDimitry Andricdef PseudoCCOR : Pseudo<(outs GPR:$dst), 84*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 85*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 86*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, 87*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU, ReadSFBALU]>; 88*0fca6ea1SDimitry Andricdef PseudoCCXOR : Pseudo<(outs GPR:$dst), 89*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 90*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 91*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, 92*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU, ReadSFBALU]>; 93*0fca6ea1SDimitry Andric 94*0fca6ea1SDimitry Andricdef PseudoCCADDI : Pseudo<(outs GPR:$dst), 95*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 96*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, 97*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 98*0fca6ea1SDimitry Andric ReadSFBALU]>; 99*0fca6ea1SDimitry Andricdef PseudoCCSLLI : Pseudo<(outs GPR:$dst), 100*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 101*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, 102*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 103*0fca6ea1SDimitry Andric ReadSFBALU]>; 104*0fca6ea1SDimitry Andricdef PseudoCCSRLI : Pseudo<(outs GPR:$dst), 105*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 106*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, 107*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 108*0fca6ea1SDimitry Andric ReadSFBALU]>; 109*0fca6ea1SDimitry Andricdef PseudoCCSRAI : Pseudo<(outs GPR:$dst), 110*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 111*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, 112*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 113*0fca6ea1SDimitry Andric ReadSFBALU]>; 114*0fca6ea1SDimitry Andricdef PseudoCCANDI : Pseudo<(outs GPR:$dst), 115*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 116*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, 117*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 118*0fca6ea1SDimitry Andric ReadSFBALU]>; 119*0fca6ea1SDimitry Andricdef PseudoCCORI : Pseudo<(outs GPR:$dst), 120*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 121*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, 122*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 123*0fca6ea1SDimitry Andric ReadSFBALU]>; 124*0fca6ea1SDimitry Andricdef PseudoCCXORI : Pseudo<(outs GPR:$dst), 125*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 126*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, 127*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 128*0fca6ea1SDimitry Andric ReadSFBALU]>; 129*0fca6ea1SDimitry Andric 130*0fca6ea1SDimitry Andric// RV64I instructions 131*0fca6ea1SDimitry Andricdef PseudoCCADDW : Pseudo<(outs GPR:$dst), 132*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 133*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 134*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, 135*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU, ReadSFBALU]>; 136*0fca6ea1SDimitry Andricdef PseudoCCSUBW : Pseudo<(outs GPR:$dst), 137*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 138*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 139*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, 140*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU, ReadSFBALU]>; 141*0fca6ea1SDimitry Andricdef PseudoCCSLLW : Pseudo<(outs GPR:$dst), 142*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 143*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 144*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 145*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU]>; 146*0fca6ea1SDimitry Andricdef PseudoCCSRLW : Pseudo<(outs GPR:$dst), 147*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 148*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 149*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 150*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU]>; 151*0fca6ea1SDimitry Andricdef PseudoCCSRAW : Pseudo<(outs GPR:$dst), 152*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 153*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 154*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 155*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU]>; 156*0fca6ea1SDimitry Andric 157*0fca6ea1SDimitry Andricdef PseudoCCADDIW : Pseudo<(outs GPR:$dst), 158*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 159*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, 160*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 161*0fca6ea1SDimitry Andric ReadSFBALU]>; 162*0fca6ea1SDimitry Andricdef PseudoCCSLLIW : Pseudo<(outs GPR:$dst), 163*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 164*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, 165*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 166*0fca6ea1SDimitry Andric ReadSFBALU]>; 167*0fca6ea1SDimitry Andricdef PseudoCCSRLIW : Pseudo<(outs GPR:$dst), 168*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 169*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, 170*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 171*0fca6ea1SDimitry Andric ReadSFBALU]>; 172*0fca6ea1SDimitry Andricdef PseudoCCSRAIW : Pseudo<(outs GPR:$dst), 173*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 174*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, 175*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, 176*0fca6ea1SDimitry Andric ReadSFBALU]>; 177*0fca6ea1SDimitry Andric 178*0fca6ea1SDimitry Andric// Zbb/Zbkb instructions 179*0fca6ea1SDimitry Andricdef PseudoCCANDN : Pseudo<(outs GPR:$dst), 180*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 181*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 182*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, 183*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU, ReadSFBALU]>; 184*0fca6ea1SDimitry Andricdef PseudoCCORN : Pseudo<(outs GPR:$dst), 185*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 186*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 187*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, 188*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU, ReadSFBALU]>; 189*0fca6ea1SDimitry Andricdef PseudoCCXNOR : Pseudo<(outs GPR:$dst), 190*0fca6ea1SDimitry Andric (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, 191*0fca6ea1SDimitry Andric GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, 192*0fca6ea1SDimitry Andric Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, 193*0fca6ea1SDimitry Andric ReadSFBALU, ReadSFBALU, ReadSFBALU]>; 194*0fca6ea1SDimitry Andric} 195*0fca6ea1SDimitry Andric 196*0fca6ea1SDimitry Andriclet Predicates = [HasShortForwardBranchOpt] in 197*0fca6ea1SDimitry Andricdef : Pat<(XLenVT (abs GPR:$rs1)), 198*0fca6ea1SDimitry Andric (PseudoCCSUB (XLenVT GPR:$rs1), (XLenVT X0), /* COND_LT */ 2, 199*0fca6ea1SDimitry Andric (XLenVT GPR:$rs1), (XLenVT X0), (XLenVT GPR:$rs1))>; 200*0fca6ea1SDimitry Andriclet Predicates = [HasShortForwardBranchOpt, IsRV64] in 201*0fca6ea1SDimitry Andricdef : Pat<(sext_inreg (abs 33signbits_node:$rs1), i32), 202*0fca6ea1SDimitry Andric (PseudoCCSUBW (i64 GPR:$rs1), (i64 X0), /* COND_LT */ 2, 203*0fca6ea1SDimitry Andric (i64 GPR:$rs1), (i64 X0), (i64 GPR:$rs1))>; 204