1bdd1243dSDimitry Andric //===-- RISCVRegisterBankInfo.h ---------------------------------*- C++ -*-===// 2bdd1243dSDimitry Andric // 3bdd1243dSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4bdd1243dSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5bdd1243dSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6bdd1243dSDimitry Andric // 7bdd1243dSDimitry Andric //===----------------------------------------------------------------------===// 8bdd1243dSDimitry Andric /// \file 906c3fb27SDimitry Andric /// This file declares the targeting of the RegisterBankInfo class for RISC-V. 10bdd1243dSDimitry Andric /// \todo This should be generated by TableGen. 11bdd1243dSDimitry Andric //===----------------------------------------------------------------------===// 12bdd1243dSDimitry Andric 13bdd1243dSDimitry Andric #ifndef LLVM_LIB_TARGET_RISCV_RISCVREGISTERBANKINFO_H 14bdd1243dSDimitry Andric #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERBANKINFO_H 15bdd1243dSDimitry Andric 16bdd1243dSDimitry Andric #include "llvm/CodeGen/RegisterBankInfo.h" 17bdd1243dSDimitry Andric 18bdd1243dSDimitry Andric #define GET_REGBANK_DECLARATIONS 19bdd1243dSDimitry Andric #include "RISCVGenRegisterBank.inc" 20bdd1243dSDimitry Andric 21bdd1243dSDimitry Andric namespace llvm { 22bdd1243dSDimitry Andric 23bdd1243dSDimitry Andric class TargetRegisterInfo; 24bdd1243dSDimitry Andric 25bdd1243dSDimitry Andric class RISCVGenRegisterBankInfo : public RegisterBankInfo { 26bdd1243dSDimitry Andric protected: 27bdd1243dSDimitry Andric #define GET_TARGET_REGBANK_CLASS 28bdd1243dSDimitry Andric #include "RISCVGenRegisterBank.inc" 29bdd1243dSDimitry Andric }; 30bdd1243dSDimitry Andric 31bdd1243dSDimitry Andric /// This class provides the information for the target register banks. 32bdd1243dSDimitry Andric class RISCVRegisterBankInfo final : public RISCVGenRegisterBankInfo { 33bdd1243dSDimitry Andric public: 3406c3fb27SDimitry Andric RISCVRegisterBankInfo(unsigned HwMode); 35*5f757f3fSDimitry Andric 36*5f757f3fSDimitry Andric const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 37*5f757f3fSDimitry Andric LLT Ty) const override; 38*5f757f3fSDimitry Andric 39*5f757f3fSDimitry Andric const InstructionMapping & 40*5f757f3fSDimitry Andric getInstrMapping(const MachineInstr &MI) const override; 41*5f757f3fSDimitry Andric 42*5f757f3fSDimitry Andric private: 43*5f757f3fSDimitry Andric /// \returns true if \p MI only uses and defines FPRs. 44*5f757f3fSDimitry Andric bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI, 45*5f757f3fSDimitry Andric const TargetRegisterInfo &TRI) const; 46*5f757f3fSDimitry Andric 47*5f757f3fSDimitry Andric /// \returns true if \p MI only uses FPRs. 48*5f757f3fSDimitry Andric bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 49*5f757f3fSDimitry Andric const TargetRegisterInfo &TRI) const; 50*5f757f3fSDimitry Andric 51*5f757f3fSDimitry Andric /// \returns true if any use of \p Def only user FPRs. 52*5f757f3fSDimitry Andric bool anyUseOnlyUseFP(Register Def, const MachineRegisterInfo &MRI, 53*5f757f3fSDimitry Andric const TargetRegisterInfo &TRI) const; 54*5f757f3fSDimitry Andric 55*5f757f3fSDimitry Andric /// \returns true if \p MI only defines FPRs. 56*5f757f3fSDimitry Andric bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 57*5f757f3fSDimitry Andric const TargetRegisterInfo &TRI) const; 58bdd1243dSDimitry Andric }; 59bdd1243dSDimitry Andric } // end namespace llvm 60bdd1243dSDimitry Andric #endif 61