1*0b57cec5SDimitry Andric//===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric// 9*0b57cec5SDimitry Andric// This file defines the itinerary class data for the G4+ (7450) processor. 10*0b57cec5SDimitry Andric// 11*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andricdef G4P_BPU : FuncUnit; // Branch unit 14*0b57cec5SDimitry Andricdef G4P_SLU : FuncUnit; // Store/load unit 15*0b57cec5SDimitry Andricdef G4P_SRU : FuncUnit; // special register unit 16*0b57cec5SDimitry Andricdef G4P_IU1 : FuncUnit; // integer unit 1 (simple) 17*0b57cec5SDimitry Andricdef G4P_IU2 : FuncUnit; // integer unit 2 (complex) 18*0b57cec5SDimitry Andricdef G4P_IU3 : FuncUnit; // integer unit 3 (simple) 19*0b57cec5SDimitry Andricdef G4P_IU4 : FuncUnit; // integer unit 4 (simple) 20*0b57cec5SDimitry Andricdef G4P_FPU1 : FuncUnit; // floating point unit 1 21*0b57cec5SDimitry Andricdef G4P_VPU : FuncUnit; // vector permutation unit 22*0b57cec5SDimitry Andricdef G4P_VIU1 : FuncUnit; // vector integer unit 1 (simple) 23*0b57cec5SDimitry Andricdef G4P_VIU2 : FuncUnit; // vector integer unit 2 (complex) 24*0b57cec5SDimitry Andricdef G4P_VFPU : FuncUnit; // vector floating point unit 25*0b57cec5SDimitry Andric 26*0b57cec5SDimitry Andricdef G4PlusItineraries : ProcessorItineraries< 27*0b57cec5SDimitry Andric [G4P_IU1, G4P_IU2, G4P_IU3, G4P_IU4, G4P_BPU, G4P_SLU, G4P_FPU1, 28*0b57cec5SDimitry Andric G4P_VFPU, G4P_VIU1, G4P_VIU2, G4P_VPU], [], [ 29*0b57cec5SDimitry Andric InstrItinData<IIC_IntSimple , [InstrStage<1, [G4P_IU1, G4P_IU2, 30*0b57cec5SDimitry Andric G4P_IU3, G4P_IU4]>]>, 31*0b57cec5SDimitry Andric InstrItinData<IIC_IntGeneral , [InstrStage<1, [G4P_IU1, G4P_IU2, 32*0b57cec5SDimitry Andric G4P_IU3, G4P_IU4]>]>, 33*0b57cec5SDimitry Andric InstrItinData<IIC_IntCompare , [InstrStage<1, [G4P_IU1, G4P_IU2, 34*0b57cec5SDimitry Andric G4P_IU3, G4P_IU4]>]>, 35*0b57cec5SDimitry Andric InstrItinData<IIC_IntDivW , [InstrStage<23, [G4P_IU2]>]>, 36*0b57cec5SDimitry Andric InstrItinData<IIC_IntMFFS , [InstrStage<5, [G4P_FPU1]>]>, 37*0b57cec5SDimitry Andric InstrItinData<IIC_IntMFVSCR , [InstrStage<2, [G4P_VFPU]>]>, 38*0b57cec5SDimitry Andric InstrItinData<IIC_IntMTFSB0 , [InstrStage<5, [G4P_FPU1]>]>, 39*0b57cec5SDimitry Andric InstrItinData<IIC_IntMulHW , [InstrStage<4, [G4P_IU2]>]>, 40*0b57cec5SDimitry Andric InstrItinData<IIC_IntMulHWU , [InstrStage<4, [G4P_IU2]>]>, 41*0b57cec5SDimitry Andric InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4P_IU2]>]>, 42*0b57cec5SDimitry Andric InstrItinData<IIC_IntRotate , [InstrStage<1, [G4P_IU1, G4P_IU2, 43*0b57cec5SDimitry Andric G4P_IU3, G4P_IU4]>]>, 44*0b57cec5SDimitry Andric InstrItinData<IIC_IntShift , [InstrStage<2, [G4P_IU1, G4P_IU2, 45*0b57cec5SDimitry Andric G4P_IU3, G4P_IU4]>]>, 46*0b57cec5SDimitry Andric InstrItinData<IIC_IntTrapW , [InstrStage<2, [G4P_IU1, G4P_IU2, 47*0b57cec5SDimitry Andric G4P_IU3, G4P_IU4]>]>, 48*0b57cec5SDimitry Andric InstrItinData<IIC_BrB , [InstrStage<1, [G4P_BPU]>]>, 49*0b57cec5SDimitry Andric InstrItinData<IIC_BrCR , [InstrStage<2, [G4P_IU2]>]>, 50*0b57cec5SDimitry Andric InstrItinData<IIC_BrMCR , [InstrStage<2, [G4P_IU2]>]>, 51*0b57cec5SDimitry Andric InstrItinData<IIC_BrMCRX , [InstrStage<2, [G4P_IU2]>]>, 52*0b57cec5SDimitry Andric InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G4P_SLU]>]>, 53*0b57cec5SDimitry Andric InstrItinData<IIC_LdStDCBI , [InstrStage<3, [G4P_SLU]>]>, 54*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLoad , [InstrStage<3, [G4P_SLU]>]>, 55*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G4P_SLU]>]>, 56*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G4P_SLU]>]>, 57*0b57cec5SDimitry Andric InstrItinData<IIC_LdStStore , [InstrStage<3, [G4P_SLU]>]>, 58*0b57cec5SDimitry Andric InstrItinData<IIC_LdStDSS , [InstrStage<3, [G4P_SLU]>]>, 59*0b57cec5SDimitry Andric InstrItinData<IIC_LdStICBI , [InstrStage<3, [G4P_IU2]>]>, 60*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTFD , [InstrStage<3, [G4P_SLU]>]>, 61*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTFDU , [InstrStage<3, [G4P_SLU]>]>, 62*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLFD , [InstrStage<4, [G4P_SLU]>]>, 63*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLFDU , [InstrStage<4, [G4P_SLU]>]>, 64*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLFDUX , [InstrStage<4, [G4P_SLU]>]>, 65*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLHA , [InstrStage<3, [G4P_SLU]>]>, 66*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLHAU , [InstrStage<3, [G4P_SLU]>]>, 67*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLHAUX , [InstrStage<3, [G4P_SLU]>]>, 68*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLMW , [InstrStage<37, [G4P_SLU]>]>, 69*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLVecX , [InstrStage<3, [G4P_SLU]>]>, 70*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLWA , [InstrStage<3, [G4P_SLU]>]>, 71*0b57cec5SDimitry Andric InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G4P_SLU]>]>, 72*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTD , [InstrStage<3, [G4P_SLU]>]>, 73*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTDCX , [InstrStage<3, [G4P_SLU]>]>, 74*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTU , [InstrStage<3, [G4P_SLU]>]>, 75*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTUX , [InstrStage<3, [G4P_SLU]>]>, 76*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTVEBX , [InstrStage<3, [G4P_SLU]>]>, 77*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSTWCX , [InstrStage<3, [G4P_SLU]>]>, 78*0b57cec5SDimitry Andric InstrItinData<IIC_LdStSync , [InstrStage<35, [G4P_SLU]>]>, 79*0b57cec5SDimitry Andric InstrItinData<IIC_SprISYNC , [InstrStage<0, [G4P_IU1, G4P_IU2, 80*0b57cec5SDimitry Andric G4P_IU3, G4P_IU4]>]>, 81*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFSR , [InstrStage<4, [G4P_IU2]>]>, 82*0b57cec5SDimitry Andric InstrItinData<IIC_SprMTMSR , [InstrStage<2, [G4P_IU2]>]>, 83*0b57cec5SDimitry Andric InstrItinData<IIC_SprMTSR , [InstrStage<2, [G4P_IU2]>]>, 84*0b57cec5SDimitry Andric InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G4P_SLU]>]>, 85*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFCR , [InstrStage<2, [G4P_IU2]>]>, 86*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFMSR , [InstrStage<3, [G4P_IU2]>]>, 87*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFSPR , [InstrStage<4, [G4P_IU2]>]>, 88*0b57cec5SDimitry Andric InstrItinData<IIC_SprMFTB , [InstrStage<5, [G4P_IU2]>]>, 89*0b57cec5SDimitry Andric InstrItinData<IIC_SprMTSPR , [InstrStage<2, [G4P_IU2]>]>, 90*0b57cec5SDimitry Andric InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [G4P_IU2]>]>, 91*0b57cec5SDimitry Andric InstrItinData<IIC_SprRFI , [InstrStage<1, [G4P_IU1, G4P_IU2, 92*0b57cec5SDimitry Andric G4P_IU3, G4P_IU4]>]>, 93*0b57cec5SDimitry Andric InstrItinData<IIC_SprSC , [InstrStage<0, [G4P_IU1, G4P_IU2, 94*0b57cec5SDimitry Andric G4P_IU3, G4P_IU4]>]>, 95*0b57cec5SDimitry Andric InstrItinData<IIC_FPGeneral , [InstrStage<5, [G4P_FPU1]>]>, 96*0b57cec5SDimitry Andric InstrItinData<IIC_FPAddSub , [InstrStage<5, [G4P_FPU1]>]>, 97*0b57cec5SDimitry Andric InstrItinData<IIC_FPCompare , [InstrStage<5, [G4P_FPU1]>]>, 98*0b57cec5SDimitry Andric InstrItinData<IIC_FPDivD , [InstrStage<35, [G4P_FPU1]>]>, 99*0b57cec5SDimitry Andric InstrItinData<IIC_FPDivS , [InstrStage<21, [G4P_FPU1]>]>, 100*0b57cec5SDimitry Andric InstrItinData<IIC_FPFused , [InstrStage<5, [G4P_FPU1]>]>, 101*0b57cec5SDimitry Andric InstrItinData<IIC_FPRes , [InstrStage<14, [G4P_FPU1]>]>, 102*0b57cec5SDimitry Andric InstrItinData<IIC_VecGeneral , [InstrStage<1, [G4P_VIU1]>]>, 103*0b57cec5SDimitry Andric InstrItinData<IIC_VecFP , [InstrStage<4, [G4P_VFPU]>]>, 104*0b57cec5SDimitry Andric InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G4P_VFPU]>]>, 105*0b57cec5SDimitry Andric InstrItinData<IIC_VecComplex , [InstrStage<4, [G4P_VIU2]>]>, 106*0b57cec5SDimitry Andric InstrItinData<IIC_VecPerm , [InstrStage<2, [G4P_VPU]>]>, 107*0b57cec5SDimitry Andric InstrItinData<IIC_VecFPRound , [InstrStage<4, [G4P_VIU1]>]>, 108*0b57cec5SDimitry Andric InstrItinData<IIC_VecVSL , [InstrStage<2, [G4P_VPU]>]>, 109*0b57cec5SDimitry Andric InstrItinData<IIC_VecVSR , [InstrStage<2, [G4P_VPU]>]> 110*0b57cec5SDimitry Andric]>; 111