xref: /freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp (revision 0fca6ea1d4eea4c934cfff25ac9ee8ad6fe95583)
10b57cec5SDimitry Andric //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric //
90b57cec5SDimitry Andric // This file contains the PowerPC implementation of the TargetRegisterInfo
100b57cec5SDimitry Andric // class.
110b57cec5SDimitry Andric //
120b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
130b57cec5SDimitry Andric 
140b57cec5SDimitry Andric #include "PPCRegisterInfo.h"
150b57cec5SDimitry Andric #include "PPCFrameLowering.h"
160b57cec5SDimitry Andric #include "PPCInstrBuilder.h"
170b57cec5SDimitry Andric #include "PPCMachineFunctionInfo.h"
180b57cec5SDimitry Andric #include "PPCSubtarget.h"
190b57cec5SDimitry Andric #include "PPCTargetMachine.h"
200b57cec5SDimitry Andric #include "llvm/ADT/BitVector.h"
210b57cec5SDimitry Andric #include "llvm/ADT/STLExtras.h"
220b57cec5SDimitry Andric #include "llvm/ADT/Statistic.h"
230b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFrameInfo.h"
240b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunction.h"
250b57cec5SDimitry Andric #include "llvm/CodeGen/MachineInstrBuilder.h"
260b57cec5SDimitry Andric #include "llvm/CodeGen/MachineModuleInfo.h"
270b57cec5SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h"
280b57cec5SDimitry Andric #include "llvm/CodeGen/RegisterScavenging.h"
290b57cec5SDimitry Andric #include "llvm/CodeGen/TargetFrameLowering.h"
300b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h"
3181ad6265SDimitry Andric #include "llvm/CodeGen/VirtRegMap.h"
320b57cec5SDimitry Andric #include "llvm/IR/CallingConv.h"
330b57cec5SDimitry Andric #include "llvm/IR/Constants.h"
340b57cec5SDimitry Andric #include "llvm/IR/Function.h"
350b57cec5SDimitry Andric #include "llvm/IR/Type.h"
360b57cec5SDimitry Andric #include "llvm/Support/CommandLine.h"
370b57cec5SDimitry Andric #include "llvm/Support/Debug.h"
380b57cec5SDimitry Andric #include "llvm/Support/ErrorHandling.h"
390b57cec5SDimitry Andric #include "llvm/Support/MathExtras.h"
400b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h"
410b57cec5SDimitry Andric #include "llvm/Target/TargetMachine.h"
420b57cec5SDimitry Andric #include "llvm/Target/TargetOptions.h"
430b57cec5SDimitry Andric #include <cstdlib>
440b57cec5SDimitry Andric 
450b57cec5SDimitry Andric using namespace llvm;
460b57cec5SDimitry Andric 
470b57cec5SDimitry Andric #define DEBUG_TYPE "reginfo"
480b57cec5SDimitry Andric 
490b57cec5SDimitry Andric #define GET_REGINFO_TARGET_DESC
500b57cec5SDimitry Andric #include "PPCGenRegisterInfo.inc"
510b57cec5SDimitry Andric 
520b57cec5SDimitry Andric STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
530b57cec5SDimitry Andric STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
540b57cec5SDimitry Andric 
550b57cec5SDimitry Andric static cl::opt<bool>
560b57cec5SDimitry Andric EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
570b57cec5SDimitry Andric          cl::desc("Enable use of a base pointer for complex stack frames"));
580b57cec5SDimitry Andric 
590b57cec5SDimitry Andric static cl::opt<bool>
600b57cec5SDimitry Andric AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
610b57cec5SDimitry Andric          cl::desc("Force the use of a base pointer in every function"));
620b57cec5SDimitry Andric 
630b57cec5SDimitry Andric static cl::opt<bool>
640b57cec5SDimitry Andric EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(false),
650b57cec5SDimitry Andric          cl::desc("Enable spills from gpr to vsr rather than stack"));
660b57cec5SDimitry Andric 
670b57cec5SDimitry Andric static cl::opt<bool>
680b57cec5SDimitry Andric StackPtrConst("ppc-stack-ptr-caller-preserved",
690b57cec5SDimitry Andric                 cl::desc("Consider R1 caller preserved so stack saves of "
700b57cec5SDimitry Andric                          "caller preserved registers can be LICM candidates"),
710b57cec5SDimitry Andric                 cl::init(true), cl::Hidden);
720b57cec5SDimitry Andric 
730b57cec5SDimitry Andric static cl::opt<unsigned>
740b57cec5SDimitry Andric MaxCRBitSpillDist("ppc-max-crbit-spill-dist",
750b57cec5SDimitry Andric                   cl::desc("Maximum search distance for definition of CR bit "
760b57cec5SDimitry Andric                            "spill on ppc"),
770b57cec5SDimitry Andric                   cl::Hidden, cl::init(100));
780b57cec5SDimitry Andric 
79e8d8bef9SDimitry Andric // Copies/moves of physical accumulators are expensive operations
80e8d8bef9SDimitry Andric // that should be avoided whenever possible. MMA instructions are
81e8d8bef9SDimitry Andric // meant to be used in performance-sensitive computational kernels.
82e8d8bef9SDimitry Andric // This option is provided, at least for the time being, to give the
83e8d8bef9SDimitry Andric // user a tool to detect this expensive operation and either rework
84e8d8bef9SDimitry Andric // their code or report a compiler bug if that turns out to be the
85e8d8bef9SDimitry Andric // cause.
86e8d8bef9SDimitry Andric #ifndef NDEBUG
87e8d8bef9SDimitry Andric static cl::opt<bool>
88e8d8bef9SDimitry Andric ReportAccMoves("ppc-report-acc-moves",
89e8d8bef9SDimitry Andric                cl::desc("Emit information about accumulator register spills "
90e8d8bef9SDimitry Andric                         "and copies"),
91e8d8bef9SDimitry Andric                cl::Hidden, cl::init(false));
92e8d8bef9SDimitry Andric #endif
93e8d8bef9SDimitry Andric 
9481ad6265SDimitry Andric extern cl::opt<bool> DisableAutoPairedVecSt;
9581ad6265SDimitry Andric 
960b57cec5SDimitry Andric static unsigned offsetMinAlignForOpcode(unsigned OpC);
970b57cec5SDimitry Andric 
980b57cec5SDimitry Andric PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
990b57cec5SDimitry Andric   : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
1000b57cec5SDimitry Andric                        TM.isPPC64() ? 0 : 1,
1010b57cec5SDimitry Andric                        TM.isPPC64() ? 0 : 1),
1020b57cec5SDimitry Andric     TM(TM) {
1030b57cec5SDimitry Andric   ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
1040b57cec5SDimitry Andric   ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
1050b57cec5SDimitry Andric   ImmToIdxMap[PPC::LHZ]  = PPC::LHZX;   ImmToIdxMap[PPC::LHA]  = PPC::LHAX;
1060b57cec5SDimitry Andric   ImmToIdxMap[PPC::LWZ]  = PPC::LWZX;   ImmToIdxMap[PPC::LWA]  = PPC::LWAX;
1070b57cec5SDimitry Andric   ImmToIdxMap[PPC::LFS]  = PPC::LFSX;   ImmToIdxMap[PPC::LFD]  = PPC::LFDX;
1080b57cec5SDimitry Andric   ImmToIdxMap[PPC::STH]  = PPC::STHX;   ImmToIdxMap[PPC::STW]  = PPC::STWX;
1090b57cec5SDimitry Andric   ImmToIdxMap[PPC::STFS] = PPC::STFSX;  ImmToIdxMap[PPC::STFD] = PPC::STFDX;
1100b57cec5SDimitry Andric   ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
1110b57cec5SDimitry Andric   ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
1120b57cec5SDimitry Andric 
1130b57cec5SDimitry Andric   // 64-bit
1140b57cec5SDimitry Andric   ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
1150b57cec5SDimitry Andric   ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
1160b57cec5SDimitry Andric   ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
1170b57cec5SDimitry Andric   ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
1180b57cec5SDimitry Andric   ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
11981ad6265SDimitry Andric   ImmToIdxMap[PPC::LQ] = PPC::LQX_PSEUDO;
12081ad6265SDimitry Andric   ImmToIdxMap[PPC::STQ] = PPC::STQX_PSEUDO;
1210b57cec5SDimitry Andric 
1220b57cec5SDimitry Andric   // VSX
1230b57cec5SDimitry Andric   ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
1240b57cec5SDimitry Andric   ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
1250b57cec5SDimitry Andric   ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
1260b57cec5SDimitry Andric   ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
1270b57cec5SDimitry Andric   ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
1280b57cec5SDimitry Andric   ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
1290b57cec5SDimitry Andric   ImmToIdxMap[PPC::LXV] = PPC::LXVX;
1300b57cec5SDimitry Andric   ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
1310b57cec5SDimitry Andric   ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
1320b57cec5SDimitry Andric   ImmToIdxMap[PPC::STXV] = PPC::STXVX;
1330b57cec5SDimitry Andric   ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
1340b57cec5SDimitry Andric   ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
1350b57cec5SDimitry Andric 
1360b57cec5SDimitry Andric   // SPE
1370b57cec5SDimitry Andric   ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
1380b57cec5SDimitry Andric   ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
1390b57cec5SDimitry Andric   ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
1400b57cec5SDimitry Andric   ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
141fe6060f1SDimitry Andric 
142fe6060f1SDimitry Andric   // Power10
143349cc55cSDimitry Andric   ImmToIdxMap[PPC::PLBZ]   = PPC::LBZX; ImmToIdxMap[PPC::PLBZ8]   = PPC::LBZX8;
144349cc55cSDimitry Andric   ImmToIdxMap[PPC::PLHZ]   = PPC::LHZX; ImmToIdxMap[PPC::PLHZ8]   = PPC::LHZX8;
145349cc55cSDimitry Andric   ImmToIdxMap[PPC::PLHA]   = PPC::LHAX; ImmToIdxMap[PPC::PLHA8]   = PPC::LHAX8;
146349cc55cSDimitry Andric   ImmToIdxMap[PPC::PLWZ]   = PPC::LWZX; ImmToIdxMap[PPC::PLWZ8]   = PPC::LWZX8;
147349cc55cSDimitry Andric   ImmToIdxMap[PPC::PLWA]   = PPC::LWAX; ImmToIdxMap[PPC::PLWA8]   = PPC::LWAX;
148349cc55cSDimitry Andric   ImmToIdxMap[PPC::PLD]    = PPC::LDX;  ImmToIdxMap[PPC::PSTD]   = PPC::STDX;
149349cc55cSDimitry Andric 
150349cc55cSDimitry Andric   ImmToIdxMap[PPC::PSTB]   = PPC::STBX; ImmToIdxMap[PPC::PSTB8]   = PPC::STBX8;
151349cc55cSDimitry Andric   ImmToIdxMap[PPC::PSTH]   = PPC::STHX; ImmToIdxMap[PPC::PSTH8]   = PPC::STHX8;
152349cc55cSDimitry Andric   ImmToIdxMap[PPC::PSTW]   = PPC::STWX; ImmToIdxMap[PPC::PSTW8]   = PPC::STWX8;
153349cc55cSDimitry Andric 
154349cc55cSDimitry Andric   ImmToIdxMap[PPC::PLFS]   = PPC::LFSX; ImmToIdxMap[PPC::PSTFS]   = PPC::STFSX;
155349cc55cSDimitry Andric   ImmToIdxMap[PPC::PLFD]   = PPC::LFDX; ImmToIdxMap[PPC::PSTFD]   = PPC::STFDX;
156349cc55cSDimitry Andric   ImmToIdxMap[PPC::PLXSSP] = PPC::LXSSPX; ImmToIdxMap[PPC::PSTXSSP] = PPC::STXSSPX;
157349cc55cSDimitry Andric   ImmToIdxMap[PPC::PLXSD]  = PPC::LXSDX; ImmToIdxMap[PPC::PSTXSD]  = PPC::STXSDX;
158349cc55cSDimitry Andric   ImmToIdxMap[PPC::PLXV]   = PPC::LXVX; ImmToIdxMap[PPC::PSTXV]  = PPC::STXVX;
159349cc55cSDimitry Andric 
160fe6060f1SDimitry Andric   ImmToIdxMap[PPC::LXVP]   = PPC::LXVPX;
161fe6060f1SDimitry Andric   ImmToIdxMap[PPC::STXVP]  = PPC::STXVPX;
162fe6060f1SDimitry Andric   ImmToIdxMap[PPC::PLXVP]  = PPC::LXVPX;
163fe6060f1SDimitry Andric   ImmToIdxMap[PPC::PSTXVP] = PPC::STXVPX;
1640b57cec5SDimitry Andric }
1650b57cec5SDimitry Andric 
1660b57cec5SDimitry Andric /// getPointerRegClass - Return the register class to use to hold pointers.
1670b57cec5SDimitry Andric /// This is used for addressing modes.
1680b57cec5SDimitry Andric const TargetRegisterClass *
1690b57cec5SDimitry Andric PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
1700b57cec5SDimitry Andric                                                                        const {
171*0fca6ea1SDimitry Andric   // Note that PPCInstrInfo::foldImmediate also directly uses this Kind value
1720b57cec5SDimitry Andric   // when it checks for ZERO folding.
1730b57cec5SDimitry Andric   if (Kind == 1) {
1740b57cec5SDimitry Andric     if (TM.isPPC64())
1750b57cec5SDimitry Andric       return &PPC::G8RC_NOX0RegClass;
1760b57cec5SDimitry Andric     return &PPC::GPRC_NOR0RegClass;
1770b57cec5SDimitry Andric   }
1780b57cec5SDimitry Andric 
1790b57cec5SDimitry Andric   if (TM.isPPC64())
1800b57cec5SDimitry Andric     return &PPC::G8RCRegClass;
1810b57cec5SDimitry Andric   return &PPC::GPRCRegClass;
1820b57cec5SDimitry Andric }
1830b57cec5SDimitry Andric 
1840b57cec5SDimitry Andric const MCPhysReg*
1850b57cec5SDimitry Andric PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
1860b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
1870b57cec5SDimitry Andric   if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) {
1885ffd83dbSDimitry Andric     if (!TM.isPPC64() && Subtarget.isAIXABI())
1895ffd83dbSDimitry Andric       report_fatal_error("AnyReg unimplemented on 32-bit AIX.");
190fe6060f1SDimitry Andric     if (Subtarget.hasVSX()) {
19181ad6265SDimitry Andric       if (Subtarget.pairedVectorMemops())
19281ad6265SDimitry Andric         return CSR_64_AllRegs_VSRP_SaveList;
193fe6060f1SDimitry Andric       if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
194fe6060f1SDimitry Andric         return CSR_64_AllRegs_AIX_Dflt_VSX_SaveList;
1950b57cec5SDimitry Andric       return CSR_64_AllRegs_VSX_SaveList;
196fe6060f1SDimitry Andric     }
197fe6060f1SDimitry Andric     if (Subtarget.hasAltivec()) {
198fe6060f1SDimitry Andric       if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
199fe6060f1SDimitry Andric         return CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList;
2000b57cec5SDimitry Andric       return CSR_64_AllRegs_Altivec_SaveList;
201fe6060f1SDimitry Andric     }
2020b57cec5SDimitry Andric     return CSR_64_AllRegs_SaveList;
2030b57cec5SDimitry Andric   }
2040b57cec5SDimitry Andric 
2050b57cec5SDimitry Andric   // On PPC64, we might need to save r2 (but only if it is not reserved).
2065ffd83dbSDimitry Andric   // We do not need to treat R2 as callee-saved when using PC-Relative calls
2075ffd83dbSDimitry Andric   // because any direct uses of R2 will cause it to be reserved. If the function
2085ffd83dbSDimitry Andric   // is a leaf or the only uses of R2 are implicit uses for calls, the calls
2095ffd83dbSDimitry Andric   // will use the @notoc relocation which will cause this function to set the
2105ffd83dbSDimitry Andric   // st_other bit to 1, thereby communicating to its caller that it arbitrarily
2115ffd83dbSDimitry Andric   // clobbers the TOC.
2125ffd83dbSDimitry Andric   bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2) &&
2135ffd83dbSDimitry Andric                 !Subtarget.isUsingPCRelativeCalls();
2140b57cec5SDimitry Andric 
2150b57cec5SDimitry Andric   // Cold calling convention CSRs.
2160b57cec5SDimitry Andric   if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
2175ffd83dbSDimitry Andric     if (Subtarget.isAIXABI())
2185ffd83dbSDimitry Andric       report_fatal_error("Cold calling unimplemented on AIX.");
2190b57cec5SDimitry Andric     if (TM.isPPC64()) {
22081ad6265SDimitry Andric       if (Subtarget.pairedVectorMemops())
22181ad6265SDimitry Andric         return SaveR2 ? CSR_SVR64_ColdCC_R2_VSRP_SaveList
22281ad6265SDimitry Andric                       : CSR_SVR64_ColdCC_VSRP_SaveList;
2230b57cec5SDimitry Andric       if (Subtarget.hasAltivec())
2240b57cec5SDimitry Andric         return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
2250b57cec5SDimitry Andric                       : CSR_SVR64_ColdCC_Altivec_SaveList;
2260b57cec5SDimitry Andric       return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
2270b57cec5SDimitry Andric                     : CSR_SVR64_ColdCC_SaveList;
2280b57cec5SDimitry Andric     }
2290b57cec5SDimitry Andric     // 32-bit targets.
23081ad6265SDimitry Andric     if (Subtarget.pairedVectorMemops())
23181ad6265SDimitry Andric       return CSR_SVR32_ColdCC_VSRP_SaveList;
23281ad6265SDimitry Andric     else if (Subtarget.hasAltivec())
2330b57cec5SDimitry Andric       return CSR_SVR32_ColdCC_Altivec_SaveList;
2340b57cec5SDimitry Andric     else if (Subtarget.hasSPE())
2350b57cec5SDimitry Andric       return CSR_SVR32_ColdCC_SPE_SaveList;
2360b57cec5SDimitry Andric     return CSR_SVR32_ColdCC_SaveList;
2370b57cec5SDimitry Andric   }
2380b57cec5SDimitry Andric   // Standard calling convention CSRs.
2390b57cec5SDimitry Andric   if (TM.isPPC64()) {
240bdd1243dSDimitry Andric     if (Subtarget.pairedVectorMemops()) {
241bdd1243dSDimitry Andric       if (Subtarget.isAIXABI()) {
242bdd1243dSDimitry Andric         if (!TM.getAIXExtendedAltivecABI())
243bdd1243dSDimitry Andric           return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
244bdd1243dSDimitry Andric         return SaveR2 ? CSR_AIX64_R2_VSRP_SaveList : CSR_AIX64_VSRP_SaveList;
245bdd1243dSDimitry Andric       }
24681ad6265SDimitry Andric       return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList;
247bdd1243dSDimitry Andric     }
248fe6060f1SDimitry Andric     if (Subtarget.hasAltivec() &&
249fe6060f1SDimitry Andric         (!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) {
2505ffd83dbSDimitry Andric       return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
2515ffd83dbSDimitry Andric                     : CSR_PPC64_Altivec_SaveList;
252fe6060f1SDimitry Andric     }
2535ffd83dbSDimitry Andric     return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
2540b57cec5SDimitry Andric   }
2550b57cec5SDimitry Andric   // 32-bit targets.
256e8d8bef9SDimitry Andric   if (Subtarget.isAIXABI()) {
257bdd1243dSDimitry Andric     if (Subtarget.pairedVectorMemops())
258bdd1243dSDimitry Andric       return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_VSRP_SaveList
259bdd1243dSDimitry Andric                                            : CSR_AIX32_SaveList;
260e8d8bef9SDimitry Andric     if (Subtarget.hasAltivec())
261fe6060f1SDimitry Andric       return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
262fe6060f1SDimitry Andric                                            : CSR_AIX32_SaveList;
2635ffd83dbSDimitry Andric     return CSR_AIX32_SaveList;
264e8d8bef9SDimitry Andric   }
26581ad6265SDimitry Andric   if (Subtarget.pairedVectorMemops())
26681ad6265SDimitry Andric     return CSR_SVR432_VSRP_SaveList;
2670b57cec5SDimitry Andric   if (Subtarget.hasAltivec())
2680b57cec5SDimitry Andric     return CSR_SVR432_Altivec_SaveList;
269bdd1243dSDimitry Andric   else if (Subtarget.hasSPE()) {
270bdd1243dSDimitry Andric     if (TM.isPositionIndependent() && !TM.isPPC64())
271bdd1243dSDimitry Andric       return CSR_SVR432_SPE_NO_S30_31_SaveList;
2720b57cec5SDimitry Andric     return CSR_SVR432_SPE_SaveList;
273bdd1243dSDimitry Andric    }
2740b57cec5SDimitry Andric   return CSR_SVR432_SaveList;
2750b57cec5SDimitry Andric }
2760b57cec5SDimitry Andric 
2770b57cec5SDimitry Andric const uint32_t *
2780b57cec5SDimitry Andric PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
2790b57cec5SDimitry Andric                                       CallingConv::ID CC) const {
2800b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
2810b57cec5SDimitry Andric   if (CC == CallingConv::AnyReg) {
282fe6060f1SDimitry Andric     if (Subtarget.hasVSX()) {
28381ad6265SDimitry Andric       if (Subtarget.pairedVectorMemops())
28481ad6265SDimitry Andric         return CSR_64_AllRegs_VSRP_RegMask;
285fe6060f1SDimitry Andric       if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
286fe6060f1SDimitry Andric         return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask;
2870b57cec5SDimitry Andric       return CSR_64_AllRegs_VSX_RegMask;
288fe6060f1SDimitry Andric     }
289fe6060f1SDimitry Andric     if (Subtarget.hasAltivec()) {
290fe6060f1SDimitry Andric       if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
291fe6060f1SDimitry Andric         return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask;
2920b57cec5SDimitry Andric       return CSR_64_AllRegs_Altivec_RegMask;
293fe6060f1SDimitry Andric     }
2940b57cec5SDimitry Andric     return CSR_64_AllRegs_RegMask;
2950b57cec5SDimitry Andric   }
2960b57cec5SDimitry Andric 
2970b57cec5SDimitry Andric   if (Subtarget.isAIXABI()) {
298bdd1243dSDimitry Andric     if (Subtarget.pairedVectorMemops()) {
299bdd1243dSDimitry Andric       if (!TM.getAIXExtendedAltivecABI())
300bdd1243dSDimitry Andric         return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask;
301bdd1243dSDimitry Andric       return TM.isPPC64() ? CSR_AIX64_VSRP_RegMask : CSR_AIX32_VSRP_RegMask;
302bdd1243dSDimitry Andric     }
303fe6060f1SDimitry Andric     return TM.isPPC64()
304fe6060f1SDimitry Andric                ? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
305fe6060f1SDimitry Andric                       ? CSR_PPC64_Altivec_RegMask
306e8d8bef9SDimitry Andric                       : CSR_PPC64_RegMask)
307fe6060f1SDimitry Andric                : ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
308fe6060f1SDimitry Andric                       ? CSR_AIX32_Altivec_RegMask
309e8d8bef9SDimitry Andric                       : CSR_AIX32_RegMask);
3100b57cec5SDimitry Andric   }
3110b57cec5SDimitry Andric 
3120b57cec5SDimitry Andric   if (CC == CallingConv::Cold) {
31381ad6265SDimitry Andric     if (TM.isPPC64())
31481ad6265SDimitry Andric       return Subtarget.pairedVectorMemops()
31581ad6265SDimitry Andric                  ? CSR_SVR64_ColdCC_VSRP_RegMask
31681ad6265SDimitry Andric                  : (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
31781ad6265SDimitry Andric                                            : CSR_SVR64_ColdCC_RegMask);
31881ad6265SDimitry Andric     else
31981ad6265SDimitry Andric       return Subtarget.pairedVectorMemops()
32081ad6265SDimitry Andric                  ? CSR_SVR32_ColdCC_VSRP_RegMask
32181ad6265SDimitry Andric                  : (Subtarget.hasAltivec()
32281ad6265SDimitry Andric                         ? CSR_SVR32_ColdCC_Altivec_RegMask
32381ad6265SDimitry Andric                         : (Subtarget.hasSPE() ? CSR_SVR32_ColdCC_SPE_RegMask
3240b57cec5SDimitry Andric                                               : CSR_SVR32_ColdCC_RegMask));
3250b57cec5SDimitry Andric   }
3260b57cec5SDimitry Andric 
32781ad6265SDimitry Andric   if (TM.isPPC64())
32881ad6265SDimitry Andric     return Subtarget.pairedVectorMemops()
32981ad6265SDimitry Andric                ? CSR_SVR464_VSRP_RegMask
33081ad6265SDimitry Andric                : (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask
33181ad6265SDimitry Andric                                          : CSR_PPC64_RegMask);
33281ad6265SDimitry Andric   else
33381ad6265SDimitry Andric     return Subtarget.pairedVectorMemops()
33481ad6265SDimitry Andric                ? CSR_SVR432_VSRP_RegMask
3355ffd83dbSDimitry Andric                : (Subtarget.hasAltivec()
3365ffd83dbSDimitry Andric                       ? CSR_SVR432_Altivec_RegMask
337bdd1243dSDimitry Andric                       : (Subtarget.hasSPE()
338bdd1243dSDimitry Andric                              ? (TM.isPositionIndependent()
339bdd1243dSDimitry Andric                                      ? CSR_SVR432_SPE_NO_S30_31_RegMask
340bdd1243dSDimitry Andric                                      : CSR_SVR432_SPE_RegMask)
3410b57cec5SDimitry Andric                              : CSR_SVR432_RegMask));
3420b57cec5SDimitry Andric }
3430b57cec5SDimitry Andric 
3440b57cec5SDimitry Andric const uint32_t*
3450b57cec5SDimitry Andric PPCRegisterInfo::getNoPreservedMask() const {
3460b57cec5SDimitry Andric   return CSR_NoRegs_RegMask;
3470b57cec5SDimitry Andric }
3480b57cec5SDimitry Andric 
3490b57cec5SDimitry Andric void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
3500b57cec5SDimitry Andric   for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
3510b57cec5SDimitry Andric     Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
3520b57cec5SDimitry Andric }
3530b57cec5SDimitry Andric 
3540b57cec5SDimitry Andric BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
3550b57cec5SDimitry Andric   BitVector Reserved(getNumRegs());
3560b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
3570b57cec5SDimitry Andric   const PPCFrameLowering *TFI = getFrameLowering(MF);
3580b57cec5SDimitry Andric 
3590b57cec5SDimitry Andric   // The ZERO register is not really a register, but the representation of r0
3600b57cec5SDimitry Andric   // when used in instructions that treat r0 as the constant 0.
3610b57cec5SDimitry Andric   markSuperRegs(Reserved, PPC::ZERO);
3620b57cec5SDimitry Andric 
3630b57cec5SDimitry Andric   // The FP register is also not really a register, but is the representation
3640b57cec5SDimitry Andric   // of the frame pointer register used by ISD::FRAMEADDR.
3650b57cec5SDimitry Andric   markSuperRegs(Reserved, PPC::FP);
3660b57cec5SDimitry Andric 
3670b57cec5SDimitry Andric   // The BP register is also not really a register, but is the representation
3680b57cec5SDimitry Andric   // of the base pointer register used by setjmp.
3690b57cec5SDimitry Andric   markSuperRegs(Reserved, PPC::BP);
3700b57cec5SDimitry Andric 
3710b57cec5SDimitry Andric   // The counter registers must be reserved so that counter-based loops can
3720b57cec5SDimitry Andric   // be correctly formed (and the mtctr instructions are not DCE'd).
3730b57cec5SDimitry Andric   markSuperRegs(Reserved, PPC::CTR);
3740b57cec5SDimitry Andric   markSuperRegs(Reserved, PPC::CTR8);
3750b57cec5SDimitry Andric 
3760b57cec5SDimitry Andric   markSuperRegs(Reserved, PPC::R1);
3770b57cec5SDimitry Andric   markSuperRegs(Reserved, PPC::LR);
3780b57cec5SDimitry Andric   markSuperRegs(Reserved, PPC::LR8);
3790b57cec5SDimitry Andric   markSuperRegs(Reserved, PPC::RM);
3800b57cec5SDimitry Andric 
3810b57cec5SDimitry Andric   markSuperRegs(Reserved, PPC::VRSAVE);
3820b57cec5SDimitry Andric 
3830b57cec5SDimitry Andric   // The SVR4 ABI reserves r2 and r13
3840b57cec5SDimitry Andric   if (Subtarget.isSVR4ABI()) {
3850b57cec5SDimitry Andric     // We only reserve r2 if we need to use the TOC pointer. If we have no
3860b57cec5SDimitry Andric     // explicit uses of the TOC pointer (meaning we're a leaf function with
3870b57cec5SDimitry Andric     // no constant-pool loads, etc.) and we have no potential uses inside an
3880b57cec5SDimitry Andric     // inline asm block, then we can treat r2 has an ordinary callee-saved
3890b57cec5SDimitry Andric     // register.
3900b57cec5SDimitry Andric     const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3910b57cec5SDimitry Andric     if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
3920b57cec5SDimitry Andric       markSuperRegs(Reserved, PPC::R2);  // System-reserved register
3930b57cec5SDimitry Andric     markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
3940b57cec5SDimitry Andric   }
3950b57cec5SDimitry Andric 
3960b57cec5SDimitry Andric   // Always reserve r2 on AIX for now.
3970b57cec5SDimitry Andric   // TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions.
3980b57cec5SDimitry Andric   if (Subtarget.isAIXABI())
3990b57cec5SDimitry Andric     markSuperRegs(Reserved, PPC::R2);  // System-reserved register
4000b57cec5SDimitry Andric 
4010b57cec5SDimitry Andric   // On PPC64, r13 is the thread pointer. Never allocate this register.
4020b57cec5SDimitry Andric   if (TM.isPPC64())
4030b57cec5SDimitry Andric     markSuperRegs(Reserved, PPC::R13);
4040b57cec5SDimitry Andric 
4050b57cec5SDimitry Andric   if (TFI->needsFP(MF))
4060b57cec5SDimitry Andric     markSuperRegs(Reserved, PPC::R31);
4070b57cec5SDimitry Andric 
4080b57cec5SDimitry Andric   bool IsPositionIndependent = TM.isPositionIndependent();
4090b57cec5SDimitry Andric   if (hasBasePointer(MF)) {
4108bcb0991SDimitry Andric     if (Subtarget.is32BitELFABI() && IsPositionIndependent)
4110b57cec5SDimitry Andric       markSuperRegs(Reserved, PPC::R29);
4120b57cec5SDimitry Andric     else
4130b57cec5SDimitry Andric       markSuperRegs(Reserved, PPC::R30);
4140b57cec5SDimitry Andric   }
4150b57cec5SDimitry Andric 
4168bcb0991SDimitry Andric   if (Subtarget.is32BitELFABI() && IsPositionIndependent)
4170b57cec5SDimitry Andric     markSuperRegs(Reserved, PPC::R30);
4180b57cec5SDimitry Andric 
4190b57cec5SDimitry Andric   // Reserve Altivec registers when Altivec is unavailable.
4200b57cec5SDimitry Andric   if (!Subtarget.hasAltivec())
421bdd1243dSDimitry Andric     for (MCRegister Reg : PPC::VRRCRegClass)
422bdd1243dSDimitry Andric       markSuperRegs(Reserved, Reg);
4230b57cec5SDimitry Andric 
424fe6060f1SDimitry Andric   if (Subtarget.isAIXABI() && Subtarget.hasAltivec() &&
425fe6060f1SDimitry Andric       !TM.getAIXExtendedAltivecABI()) {
426fe6060f1SDimitry Andric     //  In the AIX default Altivec ABI, vector registers VR20-VR31 are reserved
427fe6060f1SDimitry Andric     //  and cannot be used.
428fe6060f1SDimitry Andric     for (auto Reg : CSR_Altivec_SaveList) {
429fe6060f1SDimitry Andric       if (Reg == 0)
430fe6060f1SDimitry Andric         break;
431fe6060f1SDimitry Andric       markSuperRegs(Reserved, Reg);
432fe6060f1SDimitry Andric       for (MCRegAliasIterator AS(Reg, this, true); AS.isValid(); ++AS) {
433fe6060f1SDimitry Andric         Reserved.set(*AS);
434fe6060f1SDimitry Andric       }
435fe6060f1SDimitry Andric     }
436fe6060f1SDimitry Andric   }
437fe6060f1SDimitry Andric 
4380b57cec5SDimitry Andric   assert(checkAllSuperRegsMarked(Reserved));
4390b57cec5SDimitry Andric   return Reserved;
4400b57cec5SDimitry Andric }
4410b57cec5SDimitry Andric 
44204eeddc0SDimitry Andric bool PPCRegisterInfo::isAsmClobberable(const MachineFunction &MF,
44304eeddc0SDimitry Andric                                        MCRegister PhysReg) const {
44404eeddc0SDimitry Andric   // We cannot use getReservedRegs() to find the registers that are not asm
44504eeddc0SDimitry Andric   // clobberable because there are some reserved registers which can be
44604eeddc0SDimitry Andric   // clobbered by inline asm. For example, when LR is clobbered, the register is
44704eeddc0SDimitry Andric   // saved and restored. We will hardcode the registers that are not asm
44804eeddc0SDimitry Andric   // cloberable in this function.
44904eeddc0SDimitry Andric 
45004eeddc0SDimitry Andric   // The stack pointer (R1/X1) is not clobberable by inline asm
45104eeddc0SDimitry Andric   return PhysReg != PPC::R1 && PhysReg != PPC::X1;
45204eeddc0SDimitry Andric }
45304eeddc0SDimitry Andric 
4540b57cec5SDimitry Andric bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
4550b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
4560b57cec5SDimitry Andric   const PPCInstrInfo *InstrInfo =  Subtarget.getInstrInfo();
4570b57cec5SDimitry Andric   const MachineFrameInfo &MFI = MF.getFrameInfo();
4580b57cec5SDimitry Andric   const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo();
4590b57cec5SDimitry Andric 
460fe6060f1SDimitry Andric   LLVM_DEBUG(dbgs() << "requiresFrameIndexScavenging for " << MF.getName()
461fe6060f1SDimitry Andric                     << ".\n");
4620b57cec5SDimitry Andric   // If the callee saved info is invalid we have to default to true for safety.
463fe6060f1SDimitry Andric   if (!MFI.isCalleeSavedInfoValid()) {
464fe6060f1SDimitry Andric     LLVM_DEBUG(dbgs() << "TRUE - Invalid callee saved info.\n");
4650b57cec5SDimitry Andric     return true;
466fe6060f1SDimitry Andric   }
4670b57cec5SDimitry Andric 
4680b57cec5SDimitry Andric   // We will require the use of X-Forms because the frame is larger than what
4690b57cec5SDimitry Andric   // can be represented in signed 16 bits that fit in the immediate of a D-Form.
4700b57cec5SDimitry Andric   // If we need an X-Form then we need a register to store the address offset.
4710b57cec5SDimitry Andric   unsigned FrameSize = MFI.getStackSize();
4720b57cec5SDimitry Andric   // Signed 16 bits means that the FrameSize cannot be more than 15 bits.
473fe6060f1SDimitry Andric   if (FrameSize & ~0x7FFF) {
474fe6060f1SDimitry Andric     LLVM_DEBUG(dbgs() << "TRUE - Frame size is too large for D-Form.\n");
4750b57cec5SDimitry Andric     return true;
476fe6060f1SDimitry Andric   }
4770b57cec5SDimitry Andric 
4780b57cec5SDimitry Andric   // The callee saved info is valid so it can be traversed.
4790b57cec5SDimitry Andric   // Checking for registers that need saving that do not have load or store
4800b57cec5SDimitry Andric   // forms where the address offset is an immediate.
481bdd1243dSDimitry Andric   for (const CalleeSavedInfo &CSI : Info) {
482fe6060f1SDimitry Andric     // If the spill is to a register no scavenging is required.
483bdd1243dSDimitry Andric     if (CSI.isSpilledToReg())
484fe6060f1SDimitry Andric       continue;
485fe6060f1SDimitry Andric 
486bdd1243dSDimitry Andric     int FrIdx = CSI.getFrameIdx();
487bdd1243dSDimitry Andric     Register Reg = CSI.getReg();
4880b57cec5SDimitry Andric 
4895ffd83dbSDimitry Andric     const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
4905ffd83dbSDimitry Andric     unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(RC);
4910b57cec5SDimitry Andric     if (!MFI.isFixedObjectIndex(FrIdx)) {
4920b57cec5SDimitry Andric       // This is not a fixed object. If it requires alignment then we may still
4930b57cec5SDimitry Andric       // need to use the XForm.
494fe6060f1SDimitry Andric       if (offsetMinAlignForOpcode(Opcode) > 1) {
495fe6060f1SDimitry Andric         LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
496fe6060f1SDimitry Andric                           << " for register " << printReg(Reg, this) << ".\n");
497fe6060f1SDimitry Andric         LLVM_DEBUG(dbgs() << "TRUE - Not fixed frame object that requires "
498fe6060f1SDimitry Andric                           << "alignment.\n");
4990b57cec5SDimitry Andric         return true;
5000b57cec5SDimitry Andric       }
501fe6060f1SDimitry Andric     }
5020b57cec5SDimitry Andric 
5030b57cec5SDimitry Andric     // This is eiher:
5040b57cec5SDimitry Andric     // 1) A fixed frame index object which we know are aligned so
5050b57cec5SDimitry Andric     // as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't
506480093f4SDimitry Andric     // need to consider the alignment here.
5070b57cec5SDimitry Andric     // 2) A not fixed object but in that case we now know that the min required
5080b57cec5SDimitry Andric     // alignment is no more than 1 based on the previous check.
509fe6060f1SDimitry Andric     if (InstrInfo->isXFormMemOp(Opcode)) {
510fe6060f1SDimitry Andric       LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
511fe6060f1SDimitry Andric                         << " for register " << printReg(Reg, this) << ".\n");
512fe6060f1SDimitry Andric       LLVM_DEBUG(dbgs() << "TRUE - Memory operand is X-Form.\n");
5130b57cec5SDimitry Andric       return true;
5140b57cec5SDimitry Andric     }
51581ad6265SDimitry Andric 
51681ad6265SDimitry Andric     // This is a spill/restore of a quadword.
51781ad6265SDimitry Andric     if ((Opcode == PPC::RESTORE_QUADWORD) || (Opcode == PPC::SPILL_QUADWORD)) {
51881ad6265SDimitry Andric       LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
51981ad6265SDimitry Andric                         << " for register " << printReg(Reg, this) << ".\n");
52081ad6265SDimitry Andric       LLVM_DEBUG(dbgs() << "TRUE - Memory operand is a quadword.\n");
52181ad6265SDimitry Andric       return true;
52281ad6265SDimitry Andric     }
523fe6060f1SDimitry Andric   }
524fe6060f1SDimitry Andric   LLVM_DEBUG(dbgs() << "FALSE - Scavenging is not required.\n");
5250b57cec5SDimitry Andric   return false;
5260b57cec5SDimitry Andric }
5270b57cec5SDimitry Andric 
528fe6060f1SDimitry Andric bool PPCRegisterInfo::requiresVirtualBaseRegisters(
529fe6060f1SDimitry Andric     const MachineFunction &MF) const {
530fe6060f1SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
531fe6060f1SDimitry Andric   // Do not use virtual base registers when ROP protection is turned on.
532fe6060f1SDimitry Andric   // Virtual base registers break the layout of the local variable space and may
533fe6060f1SDimitry Andric   // push the ROP Hash location past the 512 byte range of the ROP store
534fe6060f1SDimitry Andric   // instruction.
535fe6060f1SDimitry Andric   return !Subtarget.hasROPProtect();
536fe6060f1SDimitry Andric }
537fe6060f1SDimitry Andric 
5385ffd83dbSDimitry Andric bool PPCRegisterInfo::isCallerPreservedPhysReg(MCRegister PhysReg,
5390b57cec5SDimitry Andric                                                const MachineFunction &MF) const {
5408bcb0991SDimitry Andric   assert(Register::isPhysicalRegister(PhysReg));
5410b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
5420b57cec5SDimitry Andric   const MachineFrameInfo &MFI = MF.getFrameInfo();
5430b57cec5SDimitry Andric 
544fe6060f1SDimitry Andric   if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI())
5450b57cec5SDimitry Andric     return false;
546fe6060f1SDimitry Andric   if (PhysReg == Subtarget.getTOCPointerRegister())
547fe6060f1SDimitry Andric     // X2/R2 is guaranteed to be preserved within a function if it is reserved.
5480b57cec5SDimitry Andric     // The reason it's reserved is that it's the TOC pointer (and the function
5490b57cec5SDimitry Andric     // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
5500b57cec5SDimitry Andric     // with no TOC access), we can't claim that it is preserved.
551fe6060f1SDimitry Andric     return (getReservedRegs(MF).test(PhysReg));
552fe6060f1SDimitry Andric   if (StackPtrConst && PhysReg == Subtarget.getStackPointerRegister() &&
553fe6060f1SDimitry Andric       !MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
5540b57cec5SDimitry Andric     // The value of the stack pointer does not change within a function after
5550b57cec5SDimitry Andric     // the prologue and before the epilogue if there are no dynamic allocations
556fe6060f1SDimitry Andric     // and no inline asm which clobbers X1/R1.
5570b57cec5SDimitry Andric     return true;
5580b57cec5SDimitry Andric   return false;
5590b57cec5SDimitry Andric }
5600b57cec5SDimitry Andric 
561fe6060f1SDimitry Andric bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
562fe6060f1SDimitry Andric                                             ArrayRef<MCPhysReg> Order,
563fe6060f1SDimitry Andric                                             SmallVectorImpl<MCPhysReg> &Hints,
564fe6060f1SDimitry Andric                                             const MachineFunction &MF,
565fe6060f1SDimitry Andric                                             const VirtRegMap *VRM,
566fe6060f1SDimitry Andric                                             const LiveRegMatrix *Matrix) const {
567fe6060f1SDimitry Andric   const MachineRegisterInfo *MRI = &MF.getRegInfo();
568fe6060f1SDimitry Andric 
569fe6060f1SDimitry Andric   // Call the base implementation first to set any hints based on the usual
570fe6060f1SDimitry Andric   // heuristics and decide what the return value should be. We want to return
571fe6060f1SDimitry Andric   // the same value returned by the base implementation. If the base
572fe6060f1SDimitry Andric   // implementation decides to return true and force the allocation then we
573fe6060f1SDimitry Andric   // will leave it as such. On the other hand if the base implementation
574fe6060f1SDimitry Andric   // decides to return false the following code will not force the allocation
575fe6060f1SDimitry Andric   // as we are just looking to provide a hint.
576fe6060f1SDimitry Andric   bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
577fe6060f1SDimitry Andric       VirtReg, Order, Hints, MF, VRM, Matrix);
578bdd1243dSDimitry Andric 
579bdd1243dSDimitry Andric   // Don't use the allocation hints for ISAFuture.
580bdd1243dSDimitry Andric   // The WACC registers used in ISAFuture are unlike the ACC registers on
581bdd1243dSDimitry Andric   // Power 10 and so this logic to register allocation hints does not apply.
582bdd1243dSDimitry Andric   if (MF.getSubtarget<PPCSubtarget>().isISAFuture())
583bdd1243dSDimitry Andric     return BaseImplRetVal;
584bdd1243dSDimitry Andric 
585fe6060f1SDimitry Andric   // We are interested in instructions that copy values to ACC/UACC.
586fe6060f1SDimitry Andric   // The copy into UACC will be simply a COPY to a subreg so we
587fe6060f1SDimitry Andric   // want to allocate the corresponding physical subreg for the source.
588fe6060f1SDimitry Andric   // The copy into ACC will be a BUILD_UACC so we want to allocate
589fe6060f1SDimitry Andric   // the same number UACC for the source.
590bdd1243dSDimitry Andric   const TargetRegisterClass *RegClass = MRI->getRegClass(VirtReg);
591fe6060f1SDimitry Andric   for (MachineInstr &Use : MRI->reg_nodbg_instructions(VirtReg)) {
592fe6060f1SDimitry Andric     const MachineOperand *ResultOp = nullptr;
593fe6060f1SDimitry Andric     Register ResultReg;
594fe6060f1SDimitry Andric     switch (Use.getOpcode()) {
595fe6060f1SDimitry Andric     case TargetOpcode::COPY: {
596fe6060f1SDimitry Andric       ResultOp = &Use.getOperand(0);
597fe6060f1SDimitry Andric       ResultReg = ResultOp->getReg();
598bdd1243dSDimitry Andric       if (ResultReg.isVirtual() &&
599fe6060f1SDimitry Andric           MRI->getRegClass(ResultReg)->contains(PPC::UACC0) &&
600fe6060f1SDimitry Andric           VRM->hasPhys(ResultReg)) {
601fe6060f1SDimitry Andric         Register UACCPhys = VRM->getPhys(ResultReg);
602bdd1243dSDimitry Andric         Register HintReg;
603bdd1243dSDimitry Andric         if (RegClass->contains(PPC::VSRp0)) {
604bdd1243dSDimitry Andric           HintReg = getSubReg(UACCPhys, ResultOp->getSubReg());
605349cc55cSDimitry Andric           // Ensure that the hint is a VSRp register.
606349cc55cSDimitry Andric           if (HintReg >= PPC::VSRp0 && HintReg <= PPC::VSRp31)
607fe6060f1SDimitry Andric             Hints.push_back(HintReg);
608bdd1243dSDimitry Andric         } else if (RegClass->contains(PPC::ACC0)) {
609bdd1243dSDimitry Andric           HintReg = PPC::ACC0 + (UACCPhys - PPC::UACC0);
610bdd1243dSDimitry Andric           if (HintReg >= PPC::ACC0 && HintReg <= PPC::ACC7)
611bdd1243dSDimitry Andric             Hints.push_back(HintReg);
612bdd1243dSDimitry Andric         }
613fe6060f1SDimitry Andric       }
614fe6060f1SDimitry Andric       break;
615fe6060f1SDimitry Andric     }
616fe6060f1SDimitry Andric     case PPC::BUILD_UACC: {
617fe6060f1SDimitry Andric       ResultOp = &Use.getOperand(0);
618fe6060f1SDimitry Andric       ResultReg = ResultOp->getReg();
619fe6060f1SDimitry Andric       if (MRI->getRegClass(ResultReg)->contains(PPC::ACC0) &&
620fe6060f1SDimitry Andric           VRM->hasPhys(ResultReg)) {
621fe6060f1SDimitry Andric         Register ACCPhys = VRM->getPhys(ResultReg);
622fe6060f1SDimitry Andric         assert((ACCPhys >= PPC::ACC0 && ACCPhys <= PPC::ACC7) &&
623fe6060f1SDimitry Andric                "Expecting an ACC register for BUILD_UACC.");
624fe6060f1SDimitry Andric         Register HintReg = PPC::UACC0 + (ACCPhys - PPC::ACC0);
625fe6060f1SDimitry Andric         Hints.push_back(HintReg);
626fe6060f1SDimitry Andric       }
627fe6060f1SDimitry Andric       break;
628fe6060f1SDimitry Andric     }
629fe6060f1SDimitry Andric     }
630fe6060f1SDimitry Andric   }
631fe6060f1SDimitry Andric   return BaseImplRetVal;
632fe6060f1SDimitry Andric }
633fe6060f1SDimitry Andric 
6340b57cec5SDimitry Andric unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
6350b57cec5SDimitry Andric                                               MachineFunction &MF) const {
6360b57cec5SDimitry Andric   const PPCFrameLowering *TFI = getFrameLowering(MF);
6370b57cec5SDimitry Andric   const unsigned DefaultSafety = 1;
6380b57cec5SDimitry Andric 
6390b57cec5SDimitry Andric   switch (RC->getID()) {
6400b57cec5SDimitry Andric   default:
6410b57cec5SDimitry Andric     return 0;
6420b57cec5SDimitry Andric   case PPC::G8RC_NOX0RegClassID:
6430b57cec5SDimitry Andric   case PPC::GPRC_NOR0RegClassID:
6440b57cec5SDimitry Andric   case PPC::SPERCRegClassID:
6450b57cec5SDimitry Andric   case PPC::G8RCRegClassID:
6460b57cec5SDimitry Andric   case PPC::GPRCRegClassID: {
6470b57cec5SDimitry Andric     unsigned FP = TFI->hasFP(MF) ? 1 : 0;
6480b57cec5SDimitry Andric     return 32 - FP - DefaultSafety;
6490b57cec5SDimitry Andric   }
6500b57cec5SDimitry Andric   case PPC::F4RCRegClassID:
651fe6060f1SDimitry Andric   case PPC::F8RCRegClassID:
6520b57cec5SDimitry Andric   case PPC::VSLRCRegClassID:
6530b57cec5SDimitry Andric     return 32 - DefaultSafety;
654fe6060f1SDimitry Andric   case PPC::VFRCRegClassID:
655fe6060f1SDimitry Andric   case PPC::VRRCRegClassID: {
656fe6060f1SDimitry Andric     const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
657fe6060f1SDimitry Andric     // Vector registers VR20-VR31 are reserved and cannot be used in the default
658fe6060f1SDimitry Andric     // Altivec ABI on AIX.
659fe6060f1SDimitry Andric     if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI())
660fe6060f1SDimitry Andric       return 20 - DefaultSafety;
661fe6060f1SDimitry Andric   }
662fe6060f1SDimitry Andric     return 32 - DefaultSafety;
6630b57cec5SDimitry Andric   case PPC::VSFRCRegClassID:
6640b57cec5SDimitry Andric   case PPC::VSSRCRegClassID:
665fe6060f1SDimitry Andric   case PPC::VSRCRegClassID: {
666fe6060f1SDimitry Andric     const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
667fe6060f1SDimitry Andric     if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI())
668fe6060f1SDimitry Andric       // Vector registers VR20-VR31 are reserved and cannot be used in the
669fe6060f1SDimitry Andric       // default Altivec ABI on AIX.
670fe6060f1SDimitry Andric       return 52 - DefaultSafety;
671fe6060f1SDimitry Andric   }
6720b57cec5SDimitry Andric     return 64 - DefaultSafety;
6730b57cec5SDimitry Andric   case PPC::CRRCRegClassID:
6740b57cec5SDimitry Andric     return 8 - DefaultSafety;
6750b57cec5SDimitry Andric   }
6760b57cec5SDimitry Andric }
6770b57cec5SDimitry Andric 
6780b57cec5SDimitry Andric const TargetRegisterClass *
6790b57cec5SDimitry Andric PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
6800b57cec5SDimitry Andric                                            const MachineFunction &MF) const {
6810b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
682fe6060f1SDimitry Andric   const auto *DefaultSuperclass =
683fe6060f1SDimitry Andric       TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
6840b57cec5SDimitry Andric   if (Subtarget.hasVSX()) {
6850b57cec5SDimitry Andric     // With VSX, we can inflate various sub-register classes to the full VSX
6860b57cec5SDimitry Andric     // register set.
6870b57cec5SDimitry Andric 
6880b57cec5SDimitry Andric     // For Power9 we allow the user to enable GPR to vector spills.
6890b57cec5SDimitry Andric     // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
6900b57cec5SDimitry Andric     // support to spill GPRC.
691fe6060f1SDimitry Andric     if (TM.isELFv2ABI() || Subtarget.isAIXABI()) {
6920b57cec5SDimitry Andric       if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
6930b57cec5SDimitry Andric           RC == &PPC::G8RCRegClass) {
6940b57cec5SDimitry Andric         InflateGP8RC++;
6950b57cec5SDimitry Andric         return &PPC::SPILLTOVSRRCRegClass;
6960b57cec5SDimitry Andric       }
6970b57cec5SDimitry Andric       if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
6980b57cec5SDimitry Andric         InflateGPRC++;
6990b57cec5SDimitry Andric     }
700fe6060f1SDimitry Andric 
701fe6060f1SDimitry Andric     for (const auto *I = RC->getSuperClasses(); *I; ++I) {
702fe6060f1SDimitry Andric       if (getRegSizeInBits(**I) != getRegSizeInBits(*RC))
703fe6060f1SDimitry Andric         continue;
704fe6060f1SDimitry Andric 
705fe6060f1SDimitry Andric       switch ((*I)->getID()) {
706fe6060f1SDimitry Andric       case PPC::VSSRCRegClassID:
707fe6060f1SDimitry Andric         return Subtarget.hasP8Vector() ? *I : DefaultSuperclass;
708fe6060f1SDimitry Andric       case PPC::VSFRCRegClassID:
709fe6060f1SDimitry Andric       case PPC::VSRCRegClassID:
710fe6060f1SDimitry Andric         return *I;
711fe6060f1SDimitry Andric       case PPC::VSRpRCRegClassID:
712fe6060f1SDimitry Andric         return Subtarget.pairedVectorMemops() ? *I : DefaultSuperclass;
713fe6060f1SDimitry Andric       case PPC::ACCRCRegClassID:
714fe6060f1SDimitry Andric       case PPC::UACCRCRegClassID:
715fe6060f1SDimitry Andric         return Subtarget.hasMMA() ? *I : DefaultSuperclass;
716fe6060f1SDimitry Andric       }
717fe6060f1SDimitry Andric     }
7180b57cec5SDimitry Andric   }
7190b57cec5SDimitry Andric 
720fe6060f1SDimitry Andric   return DefaultSuperclass;
7210b57cec5SDimitry Andric }
7220b57cec5SDimitry Andric 
7230b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
7240b57cec5SDimitry Andric // Stack Frame Processing methods
7250b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
7260b57cec5SDimitry Andric 
7270b57cec5SDimitry Andric /// lowerDynamicAlloc - Generate the code for allocating an object in the
7280b57cec5SDimitry Andric /// current frame.  The sequence of code will be in the general form
7290b57cec5SDimitry Andric ///
7300b57cec5SDimitry Andric ///   addi   R0, SP, \#frameSize ; get the address of the previous frame
7310b57cec5SDimitry Andric ///   stwxu  R0, SP, Rnegsize   ; add and update the SP with the negated size
7320b57cec5SDimitry Andric ///   addi   Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
7330b57cec5SDimitry Andric ///
7340b57cec5SDimitry Andric void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
7350b57cec5SDimitry Andric   // Get the instruction.
7360b57cec5SDimitry Andric   MachineInstr &MI = *II;
7370b57cec5SDimitry Andric   // Get the instruction's basic block.
7380b57cec5SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
7390b57cec5SDimitry Andric   // Get the basic block's function.
7400b57cec5SDimitry Andric   MachineFunction &MF = *MBB.getParent();
7410b57cec5SDimitry Andric   // Get the frame info.
7420b57cec5SDimitry Andric   MachineFrameInfo &MFI = MF.getFrameInfo();
7430b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
7440b57cec5SDimitry Andric   // Get the instruction info.
7450b57cec5SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
7460b57cec5SDimitry Andric   // Determine whether 64-bit pointers are used.
7470b57cec5SDimitry Andric   bool LP64 = TM.isPPC64();
7480b57cec5SDimitry Andric   DebugLoc dl = MI.getDebugLoc();
7490b57cec5SDimitry Andric 
7500b57cec5SDimitry Andric   // Get the maximum call stack size.
7510b57cec5SDimitry Andric   unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
7525ffd83dbSDimitry Andric   Align MaxAlign = MFI.getMaxAlign();
7535ffd83dbSDimitry Andric   assert(isAligned(MaxAlign, maxCallFrameSize) &&
7540b57cec5SDimitry Andric          "Maximum call-frame size not sufficiently aligned");
7555ffd83dbSDimitry Andric   (void)MaxAlign;
7560b57cec5SDimitry Andric 
7570b57cec5SDimitry Andric   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
7580b57cec5SDimitry Andric   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
7598bcb0991SDimitry Andric   Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
7600b57cec5SDimitry Andric   bool KillNegSizeReg = MI.getOperand(1).isKill();
7618bcb0991SDimitry Andric   Register NegSizeReg = MI.getOperand(1).getReg();
7620b57cec5SDimitry Andric 
7635ffd83dbSDimitry Andric   prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, Reg);
7640b57cec5SDimitry Andric   // Grow the stack and update the stack pointer link, then determine the
7650b57cec5SDimitry Andric   // address of new allocated space.
7660b57cec5SDimitry Andric   if (LP64) {
7670b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
7680b57cec5SDimitry Andric         .addReg(Reg, RegState::Kill)
7690b57cec5SDimitry Andric         .addReg(PPC::X1)
7700b57cec5SDimitry Andric         .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
7710b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
7720b57cec5SDimitry Andric         .addReg(PPC::X1)
7730b57cec5SDimitry Andric         .addImm(maxCallFrameSize);
7740b57cec5SDimitry Andric   } else {
7750b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
7760b57cec5SDimitry Andric         .addReg(Reg, RegState::Kill)
7770b57cec5SDimitry Andric         .addReg(PPC::R1)
7780b57cec5SDimitry Andric         .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
7790b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
7800b57cec5SDimitry Andric         .addReg(PPC::R1)
7810b57cec5SDimitry Andric         .addImm(maxCallFrameSize);
7820b57cec5SDimitry Andric   }
7830b57cec5SDimitry Andric 
7840b57cec5SDimitry Andric   // Discard the DYNALLOC instruction.
7850b57cec5SDimitry Andric   MBB.erase(II);
7860b57cec5SDimitry Andric }
7870b57cec5SDimitry Andric 
7885ffd83dbSDimitry Andric /// To accomplish dynamic stack allocation, we have to calculate exact size
7895ffd83dbSDimitry Andric /// subtracted from the stack pointer according alignment information and get
7905ffd83dbSDimitry Andric /// previous frame pointer.
7915ffd83dbSDimitry Andric void PPCRegisterInfo::prepareDynamicAlloca(MachineBasicBlock::iterator II,
7925ffd83dbSDimitry Andric                                            Register &NegSizeReg,
7935ffd83dbSDimitry Andric                                            bool &KillNegSizeReg,
7945ffd83dbSDimitry Andric                                            Register &FramePointer) const {
7955ffd83dbSDimitry Andric   // Get the instruction.
7965ffd83dbSDimitry Andric   MachineInstr &MI = *II;
7975ffd83dbSDimitry Andric   // Get the instruction's basic block.
7985ffd83dbSDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
7995ffd83dbSDimitry Andric   // Get the basic block's function.
8005ffd83dbSDimitry Andric   MachineFunction &MF = *MBB.getParent();
8015ffd83dbSDimitry Andric   // Get the frame info.
8025ffd83dbSDimitry Andric   MachineFrameInfo &MFI = MF.getFrameInfo();
8035ffd83dbSDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
8045ffd83dbSDimitry Andric   // Get the instruction info.
8055ffd83dbSDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
8065ffd83dbSDimitry Andric   // Determine whether 64-bit pointers are used.
8075ffd83dbSDimitry Andric   bool LP64 = TM.isPPC64();
8085ffd83dbSDimitry Andric   DebugLoc dl = MI.getDebugLoc();
8095ffd83dbSDimitry Andric   // Get the total frame size.
8105ffd83dbSDimitry Andric   unsigned FrameSize = MFI.getStackSize();
8115ffd83dbSDimitry Andric 
8125ffd83dbSDimitry Andric   // Get stack alignments.
8135ffd83dbSDimitry Andric   const PPCFrameLowering *TFI = getFrameLowering(MF);
8145ffd83dbSDimitry Andric   Align TargetAlign = TFI->getStackAlign();
8155ffd83dbSDimitry Andric   Align MaxAlign = MFI.getMaxAlign();
8165ffd83dbSDimitry Andric 
8175ffd83dbSDimitry Andric   // Determine the previous frame's address.  If FrameSize can't be
8185ffd83dbSDimitry Andric   // represented as 16 bits or we need special alignment, then we load the
8195ffd83dbSDimitry Andric   // previous frame's address from 0(SP).  Why not do an addis of the hi?
8205ffd83dbSDimitry Andric   // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
8215ffd83dbSDimitry Andric   // Constructing the constant and adding would take 3 instructions.
8225ffd83dbSDimitry Andric   // Fortunately, a frame greater than 32K is rare.
8235ffd83dbSDimitry Andric   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
8245ffd83dbSDimitry Andric   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
8255ffd83dbSDimitry Andric 
8265ffd83dbSDimitry Andric   if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
8275ffd83dbSDimitry Andric     if (LP64)
8285ffd83dbSDimitry Andric       BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), FramePointer)
8295ffd83dbSDimitry Andric           .addReg(PPC::X31)
8305ffd83dbSDimitry Andric           .addImm(FrameSize);
8315ffd83dbSDimitry Andric     else
8325ffd83dbSDimitry Andric       BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer)
8335ffd83dbSDimitry Andric           .addReg(PPC::R31)
8345ffd83dbSDimitry Andric           .addImm(FrameSize);
8355ffd83dbSDimitry Andric   } else if (LP64) {
8365ffd83dbSDimitry Andric     BuildMI(MBB, II, dl, TII.get(PPC::LD), FramePointer)
8375ffd83dbSDimitry Andric         .addImm(0)
8385ffd83dbSDimitry Andric         .addReg(PPC::X1);
8395ffd83dbSDimitry Andric   } else {
8405ffd83dbSDimitry Andric     BuildMI(MBB, II, dl, TII.get(PPC::LWZ), FramePointer)
8415ffd83dbSDimitry Andric         .addImm(0)
8425ffd83dbSDimitry Andric         .addReg(PPC::R1);
8435ffd83dbSDimitry Andric   }
8445ffd83dbSDimitry Andric   // Determine the actual NegSizeReg according to alignment info.
8455ffd83dbSDimitry Andric   if (LP64) {
8465ffd83dbSDimitry Andric     if (MaxAlign > TargetAlign) {
8475ffd83dbSDimitry Andric       unsigned UnalNegSizeReg = NegSizeReg;
8485ffd83dbSDimitry Andric       NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
8495ffd83dbSDimitry Andric 
8505ffd83dbSDimitry Andric       // Unfortunately, there is no andi, only andi., and we can't insert that
8515ffd83dbSDimitry Andric       // here because we might clobber cr0 while it is live.
8525ffd83dbSDimitry Andric       BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
8535ffd83dbSDimitry Andric           .addImm(~(MaxAlign.value() - 1));
8545ffd83dbSDimitry Andric 
8555ffd83dbSDimitry Andric       unsigned NegSizeReg1 = NegSizeReg;
8565ffd83dbSDimitry Andric       NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
8575ffd83dbSDimitry Andric       BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
8585ffd83dbSDimitry Andric           .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
8595ffd83dbSDimitry Andric           .addReg(NegSizeReg1, RegState::Kill);
8605ffd83dbSDimitry Andric       KillNegSizeReg = true;
8615ffd83dbSDimitry Andric     }
8625ffd83dbSDimitry Andric   } else {
8635ffd83dbSDimitry Andric     if (MaxAlign > TargetAlign) {
8645ffd83dbSDimitry Andric       unsigned UnalNegSizeReg = NegSizeReg;
8655ffd83dbSDimitry Andric       NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
8665ffd83dbSDimitry Andric 
8675ffd83dbSDimitry Andric       // Unfortunately, there is no andi, only andi., and we can't insert that
8685ffd83dbSDimitry Andric       // here because we might clobber cr0 while it is live.
8695ffd83dbSDimitry Andric       BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
8705ffd83dbSDimitry Andric           .addImm(~(MaxAlign.value() - 1));
8715ffd83dbSDimitry Andric 
8725ffd83dbSDimitry Andric       unsigned NegSizeReg1 = NegSizeReg;
8735ffd83dbSDimitry Andric       NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
8745ffd83dbSDimitry Andric       BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
8755ffd83dbSDimitry Andric           .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
8765ffd83dbSDimitry Andric           .addReg(NegSizeReg1, RegState::Kill);
8775ffd83dbSDimitry Andric       KillNegSizeReg = true;
8785ffd83dbSDimitry Andric     }
8795ffd83dbSDimitry Andric   }
8805ffd83dbSDimitry Andric }
8815ffd83dbSDimitry Andric 
8825ffd83dbSDimitry Andric void PPCRegisterInfo::lowerPrepareProbedAlloca(
8835ffd83dbSDimitry Andric     MachineBasicBlock::iterator II) const {
8845ffd83dbSDimitry Andric   MachineInstr &MI = *II;
8855ffd83dbSDimitry Andric   // Get the instruction's basic block.
8865ffd83dbSDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
8875ffd83dbSDimitry Andric   // Get the basic block's function.
8885ffd83dbSDimitry Andric   MachineFunction &MF = *MBB.getParent();
8895ffd83dbSDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
8905ffd83dbSDimitry Andric   // Get the instruction info.
8915ffd83dbSDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
8925ffd83dbSDimitry Andric   // Determine whether 64-bit pointers are used.
8935ffd83dbSDimitry Andric   bool LP64 = TM.isPPC64();
8945ffd83dbSDimitry Andric   DebugLoc dl = MI.getDebugLoc();
8955ffd83dbSDimitry Andric   Register FramePointer = MI.getOperand(0).getReg();
896590d96feSDimitry Andric   const Register ActualNegSizeReg = MI.getOperand(1).getReg();
8975ffd83dbSDimitry Andric   bool KillNegSizeReg = MI.getOperand(2).isKill();
8985ffd83dbSDimitry Andric   Register NegSizeReg = MI.getOperand(2).getReg();
899590d96feSDimitry Andric   const MCInstrDesc &CopyInst = TII.get(LP64 ? PPC::OR8 : PPC::OR);
900590d96feSDimitry Andric   // RegAllocator might allocate FramePointer and NegSizeReg in the same phyreg.
901590d96feSDimitry Andric   if (FramePointer == NegSizeReg) {
902590d96feSDimitry Andric     assert(KillNegSizeReg && "FramePointer is a def and NegSizeReg is an use, "
903590d96feSDimitry Andric                              "NegSizeReg should be killed");
904590d96feSDimitry Andric     // FramePointer is clobbered earlier than the use of NegSizeReg in
905590d96feSDimitry Andric     // prepareDynamicAlloca, save NegSizeReg in ActualNegSizeReg to avoid
906590d96feSDimitry Andric     // misuse.
907590d96feSDimitry Andric     BuildMI(MBB, II, dl, CopyInst, ActualNegSizeReg)
908590d96feSDimitry Andric         .addReg(NegSizeReg)
909590d96feSDimitry Andric         .addReg(NegSizeReg);
910590d96feSDimitry Andric     NegSizeReg = ActualNegSizeReg;
911590d96feSDimitry Andric     KillNegSizeReg = false;
9125ffd83dbSDimitry Andric   }
913590d96feSDimitry Andric   prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer);
914590d96feSDimitry Andric   // NegSizeReg might be updated in prepareDynamicAlloca if MaxAlign >
915590d96feSDimitry Andric   // TargetAlign.
916590d96feSDimitry Andric   if (NegSizeReg != ActualNegSizeReg)
917590d96feSDimitry Andric     BuildMI(MBB, II, dl, CopyInst, ActualNegSizeReg)
918590d96feSDimitry Andric         .addReg(NegSizeReg)
919590d96feSDimitry Andric         .addReg(NegSizeReg);
9205ffd83dbSDimitry Andric   MBB.erase(II);
9215ffd83dbSDimitry Andric }
9225ffd83dbSDimitry Andric 
9230b57cec5SDimitry Andric void PPCRegisterInfo::lowerDynamicAreaOffset(
9240b57cec5SDimitry Andric     MachineBasicBlock::iterator II) const {
9250b57cec5SDimitry Andric   // Get the instruction.
9260b57cec5SDimitry Andric   MachineInstr &MI = *II;
9270b57cec5SDimitry Andric   // Get the instruction's basic block.
9280b57cec5SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
9290b57cec5SDimitry Andric   // Get the basic block's function.
9300b57cec5SDimitry Andric   MachineFunction &MF = *MBB.getParent();
9310b57cec5SDimitry Andric   // Get the frame info.
9320b57cec5SDimitry Andric   MachineFrameInfo &MFI = MF.getFrameInfo();
9330b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
9340b57cec5SDimitry Andric   // Get the instruction info.
9350b57cec5SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
9360b57cec5SDimitry Andric 
9370b57cec5SDimitry Andric   unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
9380b57cec5SDimitry Andric   bool is64Bit = TM.isPPC64();
9390b57cec5SDimitry Andric   DebugLoc dl = MI.getDebugLoc();
9400b57cec5SDimitry Andric   BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI),
9410b57cec5SDimitry Andric           MI.getOperand(0).getReg())
9420b57cec5SDimitry Andric       .addImm(maxCallFrameSize);
9430b57cec5SDimitry Andric   MBB.erase(II);
9440b57cec5SDimitry Andric }
9450b57cec5SDimitry Andric 
9460b57cec5SDimitry Andric /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
9470b57cec5SDimitry Andric /// reserving a whole register (R0), we scrounge for one here. This generates
9480b57cec5SDimitry Andric /// code like this:
9490b57cec5SDimitry Andric ///
9500b57cec5SDimitry Andric ///   mfcr rA                  ; Move the conditional register into GPR rA.
9510b57cec5SDimitry Andric ///   rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
9520b57cec5SDimitry Andric ///   stw rA, FI               ; Store rA to the frame.
9530b57cec5SDimitry Andric ///
9540b57cec5SDimitry Andric void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
9550b57cec5SDimitry Andric                                       unsigned FrameIndex) const {
9560b57cec5SDimitry Andric   // Get the instruction.
9570b57cec5SDimitry Andric   MachineInstr &MI = *II;       // ; SPILL_CR <SrcReg>, <offset>
9580b57cec5SDimitry Andric   // Get the instruction's basic block.
9590b57cec5SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
9600b57cec5SDimitry Andric   MachineFunction &MF = *MBB.getParent();
9610b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
9620b57cec5SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
9630b57cec5SDimitry Andric   DebugLoc dl = MI.getDebugLoc();
9640b57cec5SDimitry Andric 
9650b57cec5SDimitry Andric   bool LP64 = TM.isPPC64();
9660b57cec5SDimitry Andric   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
9670b57cec5SDimitry Andric   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
9680b57cec5SDimitry Andric 
9698bcb0991SDimitry Andric   Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
9708bcb0991SDimitry Andric   Register SrcReg = MI.getOperand(0).getReg();
9710b57cec5SDimitry Andric 
9720b57cec5SDimitry Andric   // We need to store the CR in the low 4-bits of the saved value. First, issue
9730b57cec5SDimitry Andric   // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
9740b57cec5SDimitry Andric   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
9750b57cec5SDimitry Andric       .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
9760b57cec5SDimitry Andric 
9770b57cec5SDimitry Andric   // If the saved register wasn't CR0, shift the bits left so that they are in
9780b57cec5SDimitry Andric   // CR0's slot.
9790b57cec5SDimitry Andric   if (SrcReg != PPC::CR0) {
9805ffd83dbSDimitry Andric     Register Reg1 = Reg;
9810b57cec5SDimitry Andric     Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
9820b57cec5SDimitry Andric 
9830b57cec5SDimitry Andric     // rlwinm rA, rA, ShiftBits, 0, 31.
9840b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
9850b57cec5SDimitry Andric       .addReg(Reg1, RegState::Kill)
9860b57cec5SDimitry Andric       .addImm(getEncodingValue(SrcReg) * 4)
9870b57cec5SDimitry Andric       .addImm(0)
9880b57cec5SDimitry Andric       .addImm(31);
9890b57cec5SDimitry Andric   }
9900b57cec5SDimitry Andric 
9910b57cec5SDimitry Andric   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
9920b57cec5SDimitry Andric                     .addReg(Reg, RegState::Kill),
9930b57cec5SDimitry Andric                     FrameIndex);
9940b57cec5SDimitry Andric 
9950b57cec5SDimitry Andric   // Discard the pseudo instruction.
9960b57cec5SDimitry Andric   MBB.erase(II);
9970b57cec5SDimitry Andric }
9980b57cec5SDimitry Andric 
9990b57cec5SDimitry Andric void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
10000b57cec5SDimitry Andric                                       unsigned FrameIndex) const {
10010b57cec5SDimitry Andric   // Get the instruction.
10020b57cec5SDimitry Andric   MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CR <offset>
10030b57cec5SDimitry Andric   // Get the instruction's basic block.
10040b57cec5SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
10050b57cec5SDimitry Andric   MachineFunction &MF = *MBB.getParent();
10060b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
10070b57cec5SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
10080b57cec5SDimitry Andric   DebugLoc dl = MI.getDebugLoc();
10090b57cec5SDimitry Andric 
10100b57cec5SDimitry Andric   bool LP64 = TM.isPPC64();
10110b57cec5SDimitry Andric   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
10120b57cec5SDimitry Andric   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
10130b57cec5SDimitry Andric 
10148bcb0991SDimitry Andric   Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
10158bcb0991SDimitry Andric   Register DestReg = MI.getOperand(0).getReg();
1016*0fca6ea1SDimitry Andric   assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) &&
10170b57cec5SDimitry Andric          "RESTORE_CR does not define its destination");
10180b57cec5SDimitry Andric 
10190b57cec5SDimitry Andric   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
10200b57cec5SDimitry Andric                               Reg), FrameIndex);
10210b57cec5SDimitry Andric 
10220b57cec5SDimitry Andric   // If the reloaded register isn't CR0, shift the bits right so that they are
10230b57cec5SDimitry Andric   // in the right CR's slot.
10240b57cec5SDimitry Andric   if (DestReg != PPC::CR0) {
10255ffd83dbSDimitry Andric     Register Reg1 = Reg;
10260b57cec5SDimitry Andric     Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
10270b57cec5SDimitry Andric 
10280b57cec5SDimitry Andric     unsigned ShiftBits = getEncodingValue(DestReg)*4;
10290b57cec5SDimitry Andric     // rlwinm r11, r11, 32-ShiftBits, 0, 31.
10300b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
10310b57cec5SDimitry Andric              .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
10320b57cec5SDimitry Andric              .addImm(31);
10330b57cec5SDimitry Andric   }
10340b57cec5SDimitry Andric 
10350b57cec5SDimitry Andric   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
10360b57cec5SDimitry Andric              .addReg(Reg, RegState::Kill);
10370b57cec5SDimitry Andric 
10380b57cec5SDimitry Andric   // Discard the pseudo instruction.
10390b57cec5SDimitry Andric   MBB.erase(II);
10400b57cec5SDimitry Andric }
10410b57cec5SDimitry Andric 
10420b57cec5SDimitry Andric void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
10430b57cec5SDimitry Andric                                          unsigned FrameIndex) const {
10440b57cec5SDimitry Andric   // Get the instruction.
10450b57cec5SDimitry Andric   MachineInstr &MI = *II;       // ; SPILL_CRBIT <SrcReg>, <offset>
10460b57cec5SDimitry Andric   // Get the instruction's basic block.
10470b57cec5SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
10480b57cec5SDimitry Andric   MachineFunction &MF = *MBB.getParent();
10490b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
10500b57cec5SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
10510b57cec5SDimitry Andric   const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo();
10520b57cec5SDimitry Andric   DebugLoc dl = MI.getDebugLoc();
10530b57cec5SDimitry Andric 
10540b57cec5SDimitry Andric   bool LP64 = TM.isPPC64();
10550b57cec5SDimitry Andric   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
10560b57cec5SDimitry Andric   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
10570b57cec5SDimitry Andric 
10588bcb0991SDimitry Andric   Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
10598bcb0991SDimitry Andric   Register SrcReg = MI.getOperand(0).getReg();
10600b57cec5SDimitry Andric 
10610b57cec5SDimitry Andric   // Search up the BB to find the definition of the CR bit.
1062480093f4SDimitry Andric   MachineBasicBlock::reverse_iterator Ins = MI;
1063480093f4SDimitry Andric   MachineBasicBlock::reverse_iterator Rend = MBB.rend();
1064480093f4SDimitry Andric   ++Ins;
10650b57cec5SDimitry Andric   unsigned CRBitSpillDistance = 0;
1066480093f4SDimitry Andric   bool SeenUse = false;
1067480093f4SDimitry Andric   for (; Ins != Rend; ++Ins) {
10680b57cec5SDimitry Andric     // Definition found.
10690b57cec5SDimitry Andric     if (Ins->modifiesRegister(SrcReg, TRI))
10700b57cec5SDimitry Andric       break;
1071480093f4SDimitry Andric     // Use found.
1072480093f4SDimitry Andric     if (Ins->readsRegister(SrcReg, TRI))
1073480093f4SDimitry Andric       SeenUse = true;
10740b57cec5SDimitry Andric     // Unable to find CR bit definition within maximum search distance.
10750b57cec5SDimitry Andric     if (CRBitSpillDistance == MaxCRBitSpillDist) {
10760b57cec5SDimitry Andric       Ins = MI;
10770b57cec5SDimitry Andric       break;
10780b57cec5SDimitry Andric     }
10790b57cec5SDimitry Andric     // Skip debug instructions when counting CR bit spill distance.
10800b57cec5SDimitry Andric     if (!Ins->isDebugInstr())
10810b57cec5SDimitry Andric       CRBitSpillDistance++;
10820b57cec5SDimitry Andric   }
10830b57cec5SDimitry Andric 
10840b57cec5SDimitry Andric   // Unable to find the definition of the CR bit in the MBB.
10850b57cec5SDimitry Andric   if (Ins == MBB.rend())
10860b57cec5SDimitry Andric     Ins = MI;
10870b57cec5SDimitry Andric 
1088480093f4SDimitry Andric   bool SpillsKnownBit = false;
10890b57cec5SDimitry Andric   // There is no need to extract the CR bit if its value is already known.
10900b57cec5SDimitry Andric   switch (Ins->getOpcode()) {
10910b57cec5SDimitry Andric   case PPC::CRUNSET:
10920b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg)
10930b57cec5SDimitry Andric       .addImm(0);
1094480093f4SDimitry Andric     SpillsKnownBit = true;
10950b57cec5SDimitry Andric     break;
10960b57cec5SDimitry Andric   case PPC::CRSET:
10970b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg)
10980b57cec5SDimitry Andric       .addImm(-32768);
1099480093f4SDimitry Andric     SpillsKnownBit = true;
11000b57cec5SDimitry Andric     break;
11010b57cec5SDimitry Andric   default:
1102e8d8bef9SDimitry Andric     // On Power10, we can use SETNBC to spill all CR bits. SETNBC will set all
1103e8d8bef9SDimitry Andric     // bits (specifically, it produces a -1 if the CR bit is set). Ultimately,
1104e8d8bef9SDimitry Andric     // the bit that is of importance to us is bit 32 (bit 0 of a 32-bit
1105e8d8bef9SDimitry Andric     // register), and SETNBC will set this.
1106e8d8bef9SDimitry Andric     if (Subtarget.isISA3_1()) {
1107e8d8bef9SDimitry Andric       BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETNBC8 : PPC::SETNBC), Reg)
1108e8d8bef9SDimitry Andric           .addReg(SrcReg, RegState::Undef);
1109e8d8bef9SDimitry Andric       break;
1110e8d8bef9SDimitry Andric     }
1111e8d8bef9SDimitry Andric 
1112480093f4SDimitry Andric     // On Power9, we can use SETB to extract the LT bit. This only works for
1113480093f4SDimitry Andric     // the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value
1114480093f4SDimitry Andric     // of the bit we care about (32-bit sign bit) will be set to the value of
1115480093f4SDimitry Andric     // the LT bit (regardless of the other bits in the CR field).
1116480093f4SDimitry Andric     if (Subtarget.isISA3_0()) {
1117480093f4SDimitry Andric       if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT ||
1118480093f4SDimitry Andric           SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT ||
1119480093f4SDimitry Andric           SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT ||
1120480093f4SDimitry Andric           SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) {
1121480093f4SDimitry Andric         BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg)
1122480093f4SDimitry Andric           .addReg(getCRFromCRBit(SrcReg), RegState::Undef);
1123480093f4SDimitry Andric         break;
1124480093f4SDimitry Andric       }
1125480093f4SDimitry Andric     }
1126480093f4SDimitry Andric 
11270b57cec5SDimitry Andric     // We need to move the CR field that contains the CR bit we are spilling.
11280b57cec5SDimitry Andric     // The super register may not be explicitly defined (i.e. it can be defined
11290b57cec5SDimitry Andric     // by a CR-logical that only defines the subreg) so we state that the CR
11300b57cec5SDimitry Andric     // field is undef. Also, in order to preserve the kill flag on the CR bit,
11310b57cec5SDimitry Andric     // we add it as an implicit use.
11320b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
11330b57cec5SDimitry Andric       .addReg(getCRFromCRBit(SrcReg), RegState::Undef)
11340b57cec5SDimitry Andric       .addReg(SrcReg,
11350b57cec5SDimitry Andric               RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
11360b57cec5SDimitry Andric 
11370b57cec5SDimitry Andric     // If the saved register wasn't CR0LT, shift the bits left so that the bit
11380b57cec5SDimitry Andric     // to store is the first one. Mask all but that bit.
11395ffd83dbSDimitry Andric     Register Reg1 = Reg;
11400b57cec5SDimitry Andric     Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
11410b57cec5SDimitry Andric 
11420b57cec5SDimitry Andric     // rlwinm rA, rA, ShiftBits, 0, 0.
11430b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
11440b57cec5SDimitry Andric       .addReg(Reg1, RegState::Kill)
11450b57cec5SDimitry Andric       .addImm(getEncodingValue(SrcReg))
11460b57cec5SDimitry Andric       .addImm(0).addImm(0);
11470b57cec5SDimitry Andric   }
11480b57cec5SDimitry Andric   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
11490b57cec5SDimitry Andric                     .addReg(Reg, RegState::Kill),
11500b57cec5SDimitry Andric                     FrameIndex);
11510b57cec5SDimitry Andric 
1152480093f4SDimitry Andric   bool KillsCRBit = MI.killsRegister(SrcReg, TRI);
11530b57cec5SDimitry Andric   // Discard the pseudo instruction.
11540b57cec5SDimitry Andric   MBB.erase(II);
1155480093f4SDimitry Andric   if (SpillsKnownBit && KillsCRBit && !SeenUse) {
1156480093f4SDimitry Andric     Ins->setDesc(TII.get(PPC::UNENCODED_NOP));
115781ad6265SDimitry Andric     Ins->removeOperand(0);
1158480093f4SDimitry Andric   }
11590b57cec5SDimitry Andric }
11600b57cec5SDimitry Andric 
11610b57cec5SDimitry Andric void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
11620b57cec5SDimitry Andric                                       unsigned FrameIndex) const {
11630b57cec5SDimitry Andric   // Get the instruction.
11640b57cec5SDimitry Andric   MachineInstr &MI = *II;       // ; <DestReg> = RESTORE_CRBIT <offset>
11650b57cec5SDimitry Andric   // Get the instruction's basic block.
11660b57cec5SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
11670b57cec5SDimitry Andric   MachineFunction &MF = *MBB.getParent();
11680b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
11690b57cec5SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
11700b57cec5SDimitry Andric   DebugLoc dl = MI.getDebugLoc();
11710b57cec5SDimitry Andric 
11720b57cec5SDimitry Andric   bool LP64 = TM.isPPC64();
11730b57cec5SDimitry Andric   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
11740b57cec5SDimitry Andric   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
11750b57cec5SDimitry Andric 
11768bcb0991SDimitry Andric   Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
11778bcb0991SDimitry Andric   Register DestReg = MI.getOperand(0).getReg();
1178*0fca6ea1SDimitry Andric   assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) &&
11790b57cec5SDimitry Andric          "RESTORE_CRBIT does not define its destination");
11800b57cec5SDimitry Andric 
11810b57cec5SDimitry Andric   addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
11820b57cec5SDimitry Andric                               Reg), FrameIndex);
11830b57cec5SDimitry Andric 
11840b57cec5SDimitry Andric   BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
11850b57cec5SDimitry Andric 
11868bcb0991SDimitry Andric   Register RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
11870b57cec5SDimitry Andric   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
11880b57cec5SDimitry Andric           .addReg(getCRFromCRBit(DestReg));
11890b57cec5SDimitry Andric 
11900b57cec5SDimitry Andric   unsigned ShiftBits = getEncodingValue(DestReg);
11910b57cec5SDimitry Andric   // rlwimi r11, r10, 32-ShiftBits, ..., ...
11920b57cec5SDimitry Andric   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
11930b57cec5SDimitry Andric       .addReg(RegO, RegState::Kill)
11940b57cec5SDimitry Andric       .addReg(Reg, RegState::Kill)
11950b57cec5SDimitry Andric       .addImm(ShiftBits ? 32 - ShiftBits : 0)
11960b57cec5SDimitry Andric       .addImm(ShiftBits)
11970b57cec5SDimitry Andric       .addImm(ShiftBits);
11980b57cec5SDimitry Andric 
11990b57cec5SDimitry Andric   BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
12000b57cec5SDimitry Andric           getCRFromCRBit(DestReg))
12010b57cec5SDimitry Andric       .addReg(RegO, RegState::Kill)
12020b57cec5SDimitry Andric       // Make sure we have a use dependency all the way through this
12030b57cec5SDimitry Andric       // sequence of instructions. We can't have the other bits in the CR
12040b57cec5SDimitry Andric       // modified in between the mfocrf and the mtocrf.
12050b57cec5SDimitry Andric       .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
12060b57cec5SDimitry Andric 
12070b57cec5SDimitry Andric   // Discard the pseudo instruction.
12080b57cec5SDimitry Andric   MBB.erase(II);
12090b57cec5SDimitry Andric }
12100b57cec5SDimitry Andric 
1211e8d8bef9SDimitry Andric void PPCRegisterInfo::emitAccCopyInfo(MachineBasicBlock &MBB,
1212e8d8bef9SDimitry Andric                                       MCRegister DestReg, MCRegister SrcReg) {
1213e8d8bef9SDimitry Andric #ifdef NDEBUG
1214e8d8bef9SDimitry Andric   return;
1215e8d8bef9SDimitry Andric #else
1216e8d8bef9SDimitry Andric   if (ReportAccMoves) {
1217e8d8bef9SDimitry Andric     std::string Dest = PPC::ACCRCRegClass.contains(DestReg) ? "acc" : "uacc";
1218e8d8bef9SDimitry Andric     std::string Src = PPC::ACCRCRegClass.contains(SrcReg) ? "acc" : "uacc";
1219e8d8bef9SDimitry Andric     dbgs() << "Emitting copy from " << Src << " to " << Dest << ":\n";
1220e8d8bef9SDimitry Andric     MBB.dump();
1221e8d8bef9SDimitry Andric   }
1222e8d8bef9SDimitry Andric #endif
1223e8d8bef9SDimitry Andric }
1224e8d8bef9SDimitry Andric 
1225e8d8bef9SDimitry Andric static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed,
1226e8d8bef9SDimitry Andric                                     bool IsRestore) {
1227e8d8bef9SDimitry Andric #ifdef NDEBUG
1228e8d8bef9SDimitry Andric   return;
1229e8d8bef9SDimitry Andric #else
1230e8d8bef9SDimitry Andric   if (ReportAccMoves) {
1231e8d8bef9SDimitry Andric     dbgs() << "Emitting " << (IsPrimed ? "acc" : "uacc") << " register "
1232e8d8bef9SDimitry Andric            << (IsRestore ? "restore" : "spill") << ":\n";
1233e8d8bef9SDimitry Andric     MBB.dump();
1234e8d8bef9SDimitry Andric   }
1235e8d8bef9SDimitry Andric #endif
1236e8d8bef9SDimitry Andric }
1237e8d8bef9SDimitry Andric 
123881ad6265SDimitry Andric static void spillRegPairs(MachineBasicBlock &MBB,
123981ad6265SDimitry Andric                           MachineBasicBlock::iterator II, DebugLoc DL,
124081ad6265SDimitry Andric                           const TargetInstrInfo &TII, Register SrcReg,
124181ad6265SDimitry Andric                           unsigned FrameIndex, bool IsLittleEndian,
124281ad6265SDimitry Andric                           bool IsKilled, bool TwoPairs) {
124381ad6265SDimitry Andric   unsigned Offset = 0;
1244bdd1243dSDimitry Andric   // The register arithmetic in this function does not support virtual
1245bdd1243dSDimitry Andric   // registers.
1246bdd1243dSDimitry Andric   assert(!SrcReg.isVirtual() &&
1247bdd1243dSDimitry Andric          "Spilling register pairs does not support virtual registers.");
1248bdd1243dSDimitry Andric 
124981ad6265SDimitry Andric   if (TwoPairs)
125081ad6265SDimitry Andric     Offset = IsLittleEndian ? 48 : 0;
125181ad6265SDimitry Andric   else
125281ad6265SDimitry Andric     Offset = IsLittleEndian ? 16 : 0;
125381ad6265SDimitry Andric   Register Reg = (SrcReg > PPC::VSRp15) ? PPC::V0 + (SrcReg - PPC::VSRp16) * 2
125481ad6265SDimitry Andric                                         : PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2;
125581ad6265SDimitry Andric   addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
125681ad6265SDimitry Andric                         .addReg(Reg, getKillRegState(IsKilled)),
125781ad6265SDimitry Andric                     FrameIndex, Offset);
125881ad6265SDimitry Andric   Offset += IsLittleEndian ? -16 : 16;
125981ad6265SDimitry Andric   addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
126081ad6265SDimitry Andric                         .addReg(Reg + 1, getKillRegState(IsKilled)),
126181ad6265SDimitry Andric                     FrameIndex, Offset);
126281ad6265SDimitry Andric   if (TwoPairs) {
126381ad6265SDimitry Andric     Offset += IsLittleEndian ? -16 : 16;
126481ad6265SDimitry Andric     addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
126581ad6265SDimitry Andric                           .addReg(Reg + 2, getKillRegState(IsKilled)),
126681ad6265SDimitry Andric                       FrameIndex, Offset);
126781ad6265SDimitry Andric     Offset += IsLittleEndian ? -16 : 16;
126881ad6265SDimitry Andric     addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXV))
126981ad6265SDimitry Andric                           .addReg(Reg + 3, getKillRegState(IsKilled)),
127081ad6265SDimitry Andric                       FrameIndex, Offset);
127181ad6265SDimitry Andric   }
127281ad6265SDimitry Andric }
127381ad6265SDimitry Andric 
127481ad6265SDimitry Andric /// Remove any STXVP[X] instructions and split them out into a pair of
127581ad6265SDimitry Andric /// STXV[X] instructions if --disable-auto-paired-vec-st is specified on
127681ad6265SDimitry Andric /// the command line.
127781ad6265SDimitry Andric void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II,
127881ad6265SDimitry Andric                                            unsigned FrameIndex) const {
127981ad6265SDimitry Andric   assert(DisableAutoPairedVecSt &&
128081ad6265SDimitry Andric          "Expecting to do this only if paired vector stores are disabled.");
128181ad6265SDimitry Andric   MachineInstr &MI = *II; // STXVP <SrcReg>, <offset>
128281ad6265SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
128381ad6265SDimitry Andric   MachineFunction &MF = *MBB.getParent();
128481ad6265SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
128581ad6265SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
128681ad6265SDimitry Andric   DebugLoc DL = MI.getDebugLoc();
128781ad6265SDimitry Andric   Register SrcReg = MI.getOperand(0).getReg();
128881ad6265SDimitry Andric   bool IsLittleEndian = Subtarget.isLittleEndian();
128981ad6265SDimitry Andric   bool IsKilled = MI.getOperand(0).isKill();
129081ad6265SDimitry Andric   spillRegPairs(MBB, II, DL, TII, SrcReg, FrameIndex, IsLittleEndian, IsKilled,
129181ad6265SDimitry Andric                 /* TwoPairs */ false);
129281ad6265SDimitry Andric   // Discard the original instruction.
129381ad6265SDimitry Andric   MBB.erase(II);
129481ad6265SDimitry Andric }
129581ad6265SDimitry Andric 
1296bdd1243dSDimitry Andric static void emitWAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsRestore) {
1297bdd1243dSDimitry Andric #ifdef NDEBUG
1298bdd1243dSDimitry Andric   return;
1299bdd1243dSDimitry Andric #else
1300bdd1243dSDimitry Andric   if (ReportAccMoves) {
1301bdd1243dSDimitry Andric     dbgs() << "Emitting wacc register " << (IsRestore ? "restore" : "spill")
1302bdd1243dSDimitry Andric            << ":\n";
1303bdd1243dSDimitry Andric     MBB.dump();
1304bdd1243dSDimitry Andric   }
1305bdd1243dSDimitry Andric #endif
1306bdd1243dSDimitry Andric }
1307bdd1243dSDimitry Andric 
1308e8d8bef9SDimitry Andric /// lowerACCSpilling - Generate the code for spilling the accumulator register.
1309e8d8bef9SDimitry Andric /// Similarly to other spills/reloads that use pseudo-ops, we do not actually
1310e8d8bef9SDimitry Andric /// eliminate the FrameIndex here nor compute the stack offset. We simply
1311e8d8bef9SDimitry Andric /// create a real instruction with an FI and rely on eliminateFrameIndex to
1312e8d8bef9SDimitry Andric /// handle the FI elimination.
1313e8d8bef9SDimitry Andric void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
13140b57cec5SDimitry Andric                                        unsigned FrameIndex) const {
1315e8d8bef9SDimitry Andric   MachineInstr &MI = *II; // SPILL_ACC <SrcReg>, <offset>
13160b57cec5SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
13170b57cec5SDimitry Andric   MachineFunction &MF = *MBB.getParent();
13180b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
13190b57cec5SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1320e8d8bef9SDimitry Andric   DebugLoc DL = MI.getDebugLoc();
13218bcb0991SDimitry Andric   Register SrcReg = MI.getOperand(0).getReg();
1322e8d8bef9SDimitry Andric   bool IsKilled = MI.getOperand(0).isKill();
13230b57cec5SDimitry Andric 
1324e8d8bef9SDimitry Andric   bool IsPrimed = PPC::ACCRCRegClass.contains(SrcReg);
1325e8d8bef9SDimitry Andric   Register Reg =
1326e8d8bef9SDimitry Andric       PPC::VSRp0 + (SrcReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
1327e8d8bef9SDimitry Andric   bool IsLittleEndian = Subtarget.isLittleEndian();
13280b57cec5SDimitry Andric 
1329e8d8bef9SDimitry Andric   emitAccSpillRestoreInfo(MBB, IsPrimed, false);
1330e8d8bef9SDimitry Andric 
1331e8d8bef9SDimitry Andric   // De-prime the register being spilled, create two stores for the pair
1332e8d8bef9SDimitry Andric   // subregisters accounting for endianness and then re-prime the register if
1333e8d8bef9SDimitry Andric   // it isn't killed.  This uses the Offset parameter to addFrameReference() to
1334e8d8bef9SDimitry Andric   // adjust the offset of the store that is within the 64-byte stack slot.
1335e8d8bef9SDimitry Andric   if (IsPrimed)
1336e8d8bef9SDimitry Andric     BuildMI(MBB, II, DL, TII.get(PPC::XXMFACC), SrcReg).addReg(SrcReg);
133781ad6265SDimitry Andric   if (DisableAutoPairedVecSt)
133881ad6265SDimitry Andric     spillRegPairs(MBB, II, DL, TII, Reg, FrameIndex, IsLittleEndian, IsKilled,
133981ad6265SDimitry Andric                   /* TwoPairs */ true);
134081ad6265SDimitry Andric   else {
1341e8d8bef9SDimitry Andric     addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1342e8d8bef9SDimitry Andric                           .addReg(Reg, getKillRegState(IsKilled)),
1343e8d8bef9SDimitry Andric                       FrameIndex, IsLittleEndian ? 32 : 0);
1344e8d8bef9SDimitry Andric     addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1345e8d8bef9SDimitry Andric                           .addReg(Reg + 1, getKillRegState(IsKilled)),
1346e8d8bef9SDimitry Andric                       FrameIndex, IsLittleEndian ? 0 : 32);
134781ad6265SDimitry Andric   }
1348e8d8bef9SDimitry Andric   if (IsPrimed && !IsKilled)
1349e8d8bef9SDimitry Andric     BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), SrcReg).addReg(SrcReg);
13500b57cec5SDimitry Andric 
13510b57cec5SDimitry Andric   // Discard the pseudo instruction.
13520b57cec5SDimitry Andric   MBB.erase(II);
13530b57cec5SDimitry Andric }
13540b57cec5SDimitry Andric 
1355e8d8bef9SDimitry Andric /// lowerACCRestore - Generate the code to restore the accumulator register.
1356e8d8bef9SDimitry Andric void PPCRegisterInfo::lowerACCRestore(MachineBasicBlock::iterator II,
13570b57cec5SDimitry Andric                                       unsigned FrameIndex) const {
1358e8d8bef9SDimitry Andric   MachineInstr &MI = *II; // <DestReg> = RESTORE_ACC <offset>
13590b57cec5SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
13600b57cec5SDimitry Andric   MachineFunction &MF = *MBB.getParent();
13610b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
13620b57cec5SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1363e8d8bef9SDimitry Andric   DebugLoc DL = MI.getDebugLoc();
13640b57cec5SDimitry Andric 
13658bcb0991SDimitry Andric   Register DestReg = MI.getOperand(0).getReg();
1366*0fca6ea1SDimitry Andric   assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) &&
1367e8d8bef9SDimitry Andric          "RESTORE_ACC does not define its destination");
13680b57cec5SDimitry Andric 
1369e8d8bef9SDimitry Andric   bool IsPrimed = PPC::ACCRCRegClass.contains(DestReg);
1370e8d8bef9SDimitry Andric   Register Reg =
1371e8d8bef9SDimitry Andric       PPC::VSRp0 + (DestReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
1372e8d8bef9SDimitry Andric   bool IsLittleEndian = Subtarget.isLittleEndian();
13730b57cec5SDimitry Andric 
1374e8d8bef9SDimitry Andric   emitAccSpillRestoreInfo(MBB, IsPrimed, true);
1375e8d8bef9SDimitry Andric 
1376e8d8bef9SDimitry Andric   // Create two loads for the pair subregisters accounting for endianness and
1377e8d8bef9SDimitry Andric   // then prime the accumulator register being restored.
1378e8d8bef9SDimitry Andric   addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg),
1379e8d8bef9SDimitry Andric                     FrameIndex, IsLittleEndian ? 32 : 0);
1380e8d8bef9SDimitry Andric   addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), Reg + 1),
1381e8d8bef9SDimitry Andric                     FrameIndex, IsLittleEndian ? 0 : 32);
1382e8d8bef9SDimitry Andric   if (IsPrimed)
1383e8d8bef9SDimitry Andric     BuildMI(MBB, II, DL, TII.get(PPC::XXMTACC), DestReg).addReg(DestReg);
13840b57cec5SDimitry Andric 
13850b57cec5SDimitry Andric   // Discard the pseudo instruction.
13860b57cec5SDimitry Andric   MBB.erase(II);
13870b57cec5SDimitry Andric }
13880b57cec5SDimitry Andric 
1389bdd1243dSDimitry Andric /// lowerWACCSpilling - Generate the code for spilling the wide accumulator
1390bdd1243dSDimitry Andric /// register.
1391bdd1243dSDimitry Andric void PPCRegisterInfo::lowerWACCSpilling(MachineBasicBlock::iterator II,
1392bdd1243dSDimitry Andric                                         unsigned FrameIndex) const {
1393bdd1243dSDimitry Andric   MachineInstr &MI = *II; // SPILL_WACC <SrcReg>, <offset>
1394bdd1243dSDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
1395bdd1243dSDimitry Andric   MachineFunction &MF = *MBB.getParent();
1396bdd1243dSDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1397bdd1243dSDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1398bdd1243dSDimitry Andric   DebugLoc DL = MI.getDebugLoc();
1399bdd1243dSDimitry Andric   bool IsLittleEndian = Subtarget.isLittleEndian();
1400bdd1243dSDimitry Andric 
1401bdd1243dSDimitry Andric   emitWAccSpillRestoreInfo(MBB, false);
1402bdd1243dSDimitry Andric 
1403bdd1243dSDimitry Andric   const TargetRegisterClass *RC = &PPC::VSRpRCRegClass;
1404bdd1243dSDimitry Andric   Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RC);
1405bdd1243dSDimitry Andric   Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RC);
1406bdd1243dSDimitry Andric   Register SrcReg = MI.getOperand(0).getReg();
1407bdd1243dSDimitry Andric 
1408bdd1243dSDimitry Andric   BuildMI(MBB, II, DL, TII.get(PPC::DMXXEXTFDMR512), VSRpReg0)
1409bdd1243dSDimitry Andric       .addDef(VSRpReg1)
1410bdd1243dSDimitry Andric       .addReg(SrcReg);
1411bdd1243dSDimitry Andric 
1412bdd1243dSDimitry Andric   addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1413bdd1243dSDimitry Andric                         .addReg(VSRpReg0, RegState::Kill),
1414bdd1243dSDimitry Andric                     FrameIndex, IsLittleEndian ? 32 : 0);
1415bdd1243dSDimitry Andric   addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STXVP))
1416bdd1243dSDimitry Andric                         .addReg(VSRpReg1, RegState::Kill),
1417bdd1243dSDimitry Andric                     FrameIndex, IsLittleEndian ? 0 : 32);
1418bdd1243dSDimitry Andric 
1419bdd1243dSDimitry Andric   // Discard the pseudo instruction.
1420bdd1243dSDimitry Andric   MBB.erase(II);
1421bdd1243dSDimitry Andric }
1422bdd1243dSDimitry Andric 
1423bdd1243dSDimitry Andric /// lowerWACCRestore - Generate the code to restore the wide accumulator
1424bdd1243dSDimitry Andric /// register.
1425bdd1243dSDimitry Andric void PPCRegisterInfo::lowerWACCRestore(MachineBasicBlock::iterator II,
1426bdd1243dSDimitry Andric                                        unsigned FrameIndex) const {
1427bdd1243dSDimitry Andric   MachineInstr &MI = *II; // <DestReg> = RESTORE_WACC <offset>
1428bdd1243dSDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
1429bdd1243dSDimitry Andric   MachineFunction &MF = *MBB.getParent();
1430bdd1243dSDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1431bdd1243dSDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1432bdd1243dSDimitry Andric   DebugLoc DL = MI.getDebugLoc();
1433bdd1243dSDimitry Andric   bool IsLittleEndian = Subtarget.isLittleEndian();
1434bdd1243dSDimitry Andric 
1435bdd1243dSDimitry Andric   emitWAccSpillRestoreInfo(MBB, true);
1436bdd1243dSDimitry Andric 
1437bdd1243dSDimitry Andric   const TargetRegisterClass *RC = &PPC::VSRpRCRegClass;
1438bdd1243dSDimitry Andric   Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RC);
1439bdd1243dSDimitry Andric   Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RC);
1440bdd1243dSDimitry Andric   Register DestReg = MI.getOperand(0).getReg();
1441bdd1243dSDimitry Andric 
1442bdd1243dSDimitry Andric   addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), VSRpReg0),
1443bdd1243dSDimitry Andric                     FrameIndex, IsLittleEndian ? 32 : 0);
1444bdd1243dSDimitry Andric   addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LXVP), VSRpReg1),
1445bdd1243dSDimitry Andric                     FrameIndex, IsLittleEndian ? 0 : 32);
1446bdd1243dSDimitry Andric 
1447bdd1243dSDimitry Andric   // Kill VSRpReg0, VSRpReg1   (killedRegState::Killed)
1448bdd1243dSDimitry Andric   BuildMI(MBB, II, DL, TII.get(PPC::DMXXINSTFDMR512), DestReg)
1449bdd1243dSDimitry Andric       .addReg(VSRpReg0, RegState::Kill)
1450bdd1243dSDimitry Andric       .addReg(VSRpReg1, RegState::Kill);
1451bdd1243dSDimitry Andric 
1452bdd1243dSDimitry Andric   // Discard the pseudo instruction.
1453bdd1243dSDimitry Andric   MBB.erase(II);
1454bdd1243dSDimitry Andric }
1455bdd1243dSDimitry Andric 
1456fe6060f1SDimitry Andric /// lowerQuadwordSpilling - Generate code to spill paired general register.
1457fe6060f1SDimitry Andric void PPCRegisterInfo::lowerQuadwordSpilling(MachineBasicBlock::iterator II,
1458fe6060f1SDimitry Andric                                             unsigned FrameIndex) const {
1459fe6060f1SDimitry Andric   MachineInstr &MI = *II;
1460fe6060f1SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
1461fe6060f1SDimitry Andric   MachineFunction &MF = *MBB.getParent();
1462fe6060f1SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1463fe6060f1SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1464fe6060f1SDimitry Andric   DebugLoc DL = MI.getDebugLoc();
1465fe6060f1SDimitry Andric 
1466fe6060f1SDimitry Andric   Register SrcReg = MI.getOperand(0).getReg();
1467fe6060f1SDimitry Andric   bool IsKilled = MI.getOperand(0).isKill();
1468fe6060f1SDimitry Andric 
1469fe6060f1SDimitry Andric   Register Reg = PPC::X0 + (SrcReg - PPC::G8p0) * 2;
1470fe6060f1SDimitry Andric   bool IsLittleEndian = Subtarget.isLittleEndian();
1471fe6060f1SDimitry Andric 
1472fe6060f1SDimitry Andric   addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD))
1473fe6060f1SDimitry Andric                         .addReg(Reg, getKillRegState(IsKilled)),
1474fe6060f1SDimitry Andric                     FrameIndex, IsLittleEndian ? 8 : 0);
1475fe6060f1SDimitry Andric   addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::STD))
1476fe6060f1SDimitry Andric                         .addReg(Reg + 1, getKillRegState(IsKilled)),
1477fe6060f1SDimitry Andric                     FrameIndex, IsLittleEndian ? 0 : 8);
1478fe6060f1SDimitry Andric 
1479fe6060f1SDimitry Andric   // Discard the pseudo instruction.
1480fe6060f1SDimitry Andric   MBB.erase(II);
1481fe6060f1SDimitry Andric }
1482fe6060f1SDimitry Andric 
1483fe6060f1SDimitry Andric /// lowerQuadwordRestore - Generate code to restore paired general register.
1484fe6060f1SDimitry Andric void PPCRegisterInfo::lowerQuadwordRestore(MachineBasicBlock::iterator II,
1485fe6060f1SDimitry Andric                                            unsigned FrameIndex) const {
1486fe6060f1SDimitry Andric   MachineInstr &MI = *II;
1487fe6060f1SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
1488fe6060f1SDimitry Andric   MachineFunction &MF = *MBB.getParent();
1489fe6060f1SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1490fe6060f1SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1491fe6060f1SDimitry Andric   DebugLoc DL = MI.getDebugLoc();
1492fe6060f1SDimitry Andric 
1493fe6060f1SDimitry Andric   Register DestReg = MI.getOperand(0).getReg();
1494*0fca6ea1SDimitry Andric   assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) &&
1495fe6060f1SDimitry Andric          "RESTORE_QUADWORD does not define its destination");
1496fe6060f1SDimitry Andric 
1497fe6060f1SDimitry Andric   Register Reg = PPC::X0 + (DestReg - PPC::G8p0) * 2;
1498fe6060f1SDimitry Andric   bool IsLittleEndian = Subtarget.isLittleEndian();
1499fe6060f1SDimitry Andric 
1500fe6060f1SDimitry Andric   addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LD), Reg), FrameIndex,
1501fe6060f1SDimitry Andric                     IsLittleEndian ? 8 : 0);
1502fe6060f1SDimitry Andric   addFrameReference(BuildMI(MBB, II, DL, TII.get(PPC::LD), Reg + 1), FrameIndex,
1503fe6060f1SDimitry Andric                     IsLittleEndian ? 0 : 8);
1504fe6060f1SDimitry Andric 
1505fe6060f1SDimitry Andric   // Discard the pseudo instruction.
1506fe6060f1SDimitry Andric   MBB.erase(II);
1507fe6060f1SDimitry Andric }
1508fe6060f1SDimitry Andric 
15090b57cec5SDimitry Andric bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
15105ffd83dbSDimitry Andric                                            Register Reg, int &FrameIdx) const {
15115ffd83dbSDimitry Andric   // For the nonvolatile condition registers (CR2, CR3, CR4) return true to
15125ffd83dbSDimitry Andric   // prevent allocating an additional frame slot.
15135ffd83dbSDimitry Andric   // For 64-bit ELF and AIX, the CR save area is in the linkage area at SP+8,
15145ffd83dbSDimitry Andric   // for 32-bit AIX the CR save area is in the linkage area at SP+4.
15155ffd83dbSDimitry Andric   // We have created a FrameIndex to that spill slot to keep the CalleSaveInfos
15165ffd83dbSDimitry Andric   // valid.
15175ffd83dbSDimitry Andric   // For 32-bit ELF, we have previously created the stack slot if needed, so
15185ffd83dbSDimitry Andric   // return its FrameIdx.
15195ffd83dbSDimitry Andric   if (PPC::CR2 <= Reg && Reg <= PPC::CR4) {
15205ffd83dbSDimitry Andric     FrameIdx = MF.getInfo<PPCFunctionInfo>()->getCRSpillFrameIndex();
15210b57cec5SDimitry Andric     return true;
15220b57cec5SDimitry Andric   }
15230b57cec5SDimitry Andric   return false;
15240b57cec5SDimitry Andric }
15250b57cec5SDimitry Andric 
15260b57cec5SDimitry Andric // If the offset must be a multiple of some value, return what that value is.
15270b57cec5SDimitry Andric static unsigned offsetMinAlignForOpcode(unsigned OpC) {
15280b57cec5SDimitry Andric   switch (OpC) {
15290b57cec5SDimitry Andric   default:
15300b57cec5SDimitry Andric     return 1;
15310b57cec5SDimitry Andric   case PPC::LWA:
15320b57cec5SDimitry Andric   case PPC::LWA_32:
15330b57cec5SDimitry Andric   case PPC::LD:
15340b57cec5SDimitry Andric   case PPC::LDU:
15350b57cec5SDimitry Andric   case PPC::STD:
15360b57cec5SDimitry Andric   case PPC::STDU:
15370b57cec5SDimitry Andric   case PPC::DFLOADf32:
15380b57cec5SDimitry Andric   case PPC::DFLOADf64:
15390b57cec5SDimitry Andric   case PPC::DFSTOREf32:
15400b57cec5SDimitry Andric   case PPC::DFSTOREf64:
15410b57cec5SDimitry Andric   case PPC::LXSD:
15420b57cec5SDimitry Andric   case PPC::LXSSP:
15430b57cec5SDimitry Andric   case PPC::STXSD:
15440b57cec5SDimitry Andric   case PPC::STXSSP:
1545fe6060f1SDimitry Andric   case PPC::STQ:
15460b57cec5SDimitry Andric     return 4;
15470b57cec5SDimitry Andric   case PPC::EVLDD:
15480b57cec5SDimitry Andric   case PPC::EVSTDD:
15490b57cec5SDimitry Andric     return 8;
15500b57cec5SDimitry Andric   case PPC::LXV:
15510b57cec5SDimitry Andric   case PPC::STXV:
1552fe6060f1SDimitry Andric   case PPC::LQ:
1553fe6060f1SDimitry Andric   case PPC::LXVP:
1554fe6060f1SDimitry Andric   case PPC::STXVP:
15550b57cec5SDimitry Andric     return 16;
15560b57cec5SDimitry Andric   }
15570b57cec5SDimitry Andric }
15580b57cec5SDimitry Andric 
15590b57cec5SDimitry Andric // If the offset must be a multiple of some value, return what that value is.
15600b57cec5SDimitry Andric static unsigned offsetMinAlign(const MachineInstr &MI) {
15610b57cec5SDimitry Andric   unsigned OpC = MI.getOpcode();
15620b57cec5SDimitry Andric   return offsetMinAlignForOpcode(OpC);
15630b57cec5SDimitry Andric }
15640b57cec5SDimitry Andric 
15650b57cec5SDimitry Andric // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
15660b57cec5SDimitry Andric static unsigned getOffsetONFromFION(const MachineInstr &MI,
15670b57cec5SDimitry Andric                                     unsigned FIOperandNum) {
15680b57cec5SDimitry Andric   // Take into account whether it's an add or mem instruction
15690b57cec5SDimitry Andric   unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
15700b57cec5SDimitry Andric   if (MI.isInlineAsm())
15710b57cec5SDimitry Andric     OffsetOperandNo = FIOperandNum - 1;
15720b57cec5SDimitry Andric   else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
15730b57cec5SDimitry Andric            MI.getOpcode() == TargetOpcode::PATCHPOINT)
15740b57cec5SDimitry Andric     OffsetOperandNo = FIOperandNum + 1;
15750b57cec5SDimitry Andric 
15760b57cec5SDimitry Andric   return OffsetOperandNo;
15770b57cec5SDimitry Andric }
15780b57cec5SDimitry Andric 
1579bdd1243dSDimitry Andric bool
15800b57cec5SDimitry Andric PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
15810b57cec5SDimitry Andric                                      int SPAdj, unsigned FIOperandNum,
15820b57cec5SDimitry Andric                                      RegScavenger *RS) const {
15830b57cec5SDimitry Andric   assert(SPAdj == 0 && "Unexpected");
15840b57cec5SDimitry Andric 
15850b57cec5SDimitry Andric   // Get the instruction.
15860b57cec5SDimitry Andric   MachineInstr &MI = *II;
15870b57cec5SDimitry Andric   // Get the instruction's basic block.
15880b57cec5SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
15890b57cec5SDimitry Andric   // Get the basic block's function.
15900b57cec5SDimitry Andric   MachineFunction &MF = *MBB.getParent();
15910b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
15920b57cec5SDimitry Andric   // Get the instruction info.
1593349cc55cSDimitry Andric   const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
15940b57cec5SDimitry Andric   // Get the frame info.
15950b57cec5SDimitry Andric   MachineFrameInfo &MFI = MF.getFrameInfo();
15960b57cec5SDimitry Andric   DebugLoc dl = MI.getDebugLoc();
15970b57cec5SDimitry Andric 
15980b57cec5SDimitry Andric   unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
15990b57cec5SDimitry Andric 
16000b57cec5SDimitry Andric   // Get the frame index.
16010b57cec5SDimitry Andric   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
16020b57cec5SDimitry Andric 
16030b57cec5SDimitry Andric   // Get the frame pointer save index.  Users of this index are primarily
16040b57cec5SDimitry Andric   // DYNALLOC instructions.
16050b57cec5SDimitry Andric   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
16060b57cec5SDimitry Andric   int FPSI = FI->getFramePointerSaveIndex();
16070b57cec5SDimitry Andric   // Get the instruction opcode.
16080b57cec5SDimitry Andric   unsigned OpC = MI.getOpcode();
16090b57cec5SDimitry Andric 
16100b57cec5SDimitry Andric   if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
16110b57cec5SDimitry Andric     lowerDynamicAreaOffset(II);
1612bdd1243dSDimitry Andric     // lowerDynamicAreaOffset erases II
1613bdd1243dSDimitry Andric     return true;
16140b57cec5SDimitry Andric   }
16150b57cec5SDimitry Andric 
16160b57cec5SDimitry Andric   // Special case for dynamic alloca.
16170b57cec5SDimitry Andric   if (FPSI && FrameIndex == FPSI &&
16180b57cec5SDimitry Andric       (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
16190b57cec5SDimitry Andric     lowerDynamicAlloc(II);
1620bdd1243dSDimitry Andric     // lowerDynamicAlloc erases II
1621bdd1243dSDimitry Andric     return true;
16220b57cec5SDimitry Andric   }
16230b57cec5SDimitry Andric 
16245ffd83dbSDimitry Andric   if (FPSI && FrameIndex == FPSI &&
16255ffd83dbSDimitry Andric       (OpC == PPC::PREPARE_PROBED_ALLOCA_64 ||
1626590d96feSDimitry Andric        OpC == PPC::PREPARE_PROBED_ALLOCA_32 ||
1627590d96feSDimitry Andric        OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 ||
1628590d96feSDimitry Andric        OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32)) {
16295ffd83dbSDimitry Andric     lowerPrepareProbedAlloca(II);
1630bdd1243dSDimitry Andric     // lowerPrepareProbedAlloca erases II
1631bdd1243dSDimitry Andric     return true;
16325ffd83dbSDimitry Andric   }
16335ffd83dbSDimitry Andric 
16340b57cec5SDimitry Andric   // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
16350b57cec5SDimitry Andric   if (OpC == PPC::SPILL_CR) {
16360b57cec5SDimitry Andric     lowerCRSpilling(II, FrameIndex);
1637bdd1243dSDimitry Andric     return true;
16380b57cec5SDimitry Andric   } else if (OpC == PPC::RESTORE_CR) {
16390b57cec5SDimitry Andric     lowerCRRestore(II, FrameIndex);
1640bdd1243dSDimitry Andric     return true;
16410b57cec5SDimitry Andric   } else if (OpC == PPC::SPILL_CRBIT) {
16420b57cec5SDimitry Andric     lowerCRBitSpilling(II, FrameIndex);
1643bdd1243dSDimitry Andric     return true;
16440b57cec5SDimitry Andric   } else if (OpC == PPC::RESTORE_CRBIT) {
16450b57cec5SDimitry Andric     lowerCRBitRestore(II, FrameIndex);
1646bdd1243dSDimitry Andric     return true;
1647e8d8bef9SDimitry Andric   } else if (OpC == PPC::SPILL_ACC || OpC == PPC::SPILL_UACC) {
1648e8d8bef9SDimitry Andric     lowerACCSpilling(II, FrameIndex);
1649bdd1243dSDimitry Andric     return true;
1650e8d8bef9SDimitry Andric   } else if (OpC == PPC::RESTORE_ACC || OpC == PPC::RESTORE_UACC) {
1651e8d8bef9SDimitry Andric     lowerACCRestore(II, FrameIndex);
1652bdd1243dSDimitry Andric     return true;
165381ad6265SDimitry Andric   } else if (OpC == PPC::STXVP && DisableAutoPairedVecSt) {
165481ad6265SDimitry Andric     lowerOctWordSpilling(II, FrameIndex);
1655bdd1243dSDimitry Andric     return true;
1656bdd1243dSDimitry Andric   } else if (OpC == PPC::SPILL_WACC) {
1657bdd1243dSDimitry Andric     lowerWACCSpilling(II, FrameIndex);
1658bdd1243dSDimitry Andric     return true;
1659bdd1243dSDimitry Andric   } else if (OpC == PPC::RESTORE_WACC) {
1660bdd1243dSDimitry Andric     lowerWACCRestore(II, FrameIndex);
1661bdd1243dSDimitry Andric     return true;
1662fe6060f1SDimitry Andric   } else if (OpC == PPC::SPILL_QUADWORD) {
1663fe6060f1SDimitry Andric     lowerQuadwordSpilling(II, FrameIndex);
1664bdd1243dSDimitry Andric     return true;
1665fe6060f1SDimitry Andric   } else if (OpC == PPC::RESTORE_QUADWORD) {
1666fe6060f1SDimitry Andric     lowerQuadwordRestore(II, FrameIndex);
1667bdd1243dSDimitry Andric     return true;
16680b57cec5SDimitry Andric   }
16690b57cec5SDimitry Andric 
16700b57cec5SDimitry Andric   // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
16710b57cec5SDimitry Andric   MI.getOperand(FIOperandNum).ChangeToRegister(
16720b57cec5SDimitry Andric     FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
16730b57cec5SDimitry Andric 
16740b57cec5SDimitry Andric   // If the instruction is not present in ImmToIdxMap, then it has no immediate
16750b57cec5SDimitry Andric   // form (and must be r+r).
16760b57cec5SDimitry Andric   bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
16770b57cec5SDimitry Andric                    OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
16780b57cec5SDimitry Andric 
16790b57cec5SDimitry Andric   // Now add the frame object offset to the offset from r1.
168081ad6265SDimitry Andric   int64_t Offset = MFI.getObjectOffset(FrameIndex);
16810b57cec5SDimitry Andric   Offset += MI.getOperand(OffsetOperandNo).getImm();
16820b57cec5SDimitry Andric 
16830b57cec5SDimitry Andric   // If we're not using a Frame Pointer that has been set to the value of the
16840b57cec5SDimitry Andric   // SP before having the stack size subtracted from it, then add the stack size
16850b57cec5SDimitry Andric   // to Offset to get the correct offset.
16860b57cec5SDimitry Andric   // Naked functions have stack size 0, although getStackSize may not reflect
16870b57cec5SDimitry Andric   // that because we didn't call all the pieces that compute it for naked
16880b57cec5SDimitry Andric   // functions.
16890b57cec5SDimitry Andric   if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) {
16900b57cec5SDimitry Andric     if (!(hasBasePointer(MF) && FrameIndex < 0))
16910b57cec5SDimitry Andric       Offset += MFI.getStackSize();
16920b57cec5SDimitry Andric   }
16930b57cec5SDimitry Andric 
1694fe6060f1SDimitry Andric   // If we encounter an LXVP/STXVP with an offset that doesn't fit, we can
1695fe6060f1SDimitry Andric   // transform it to the prefixed version so we don't have to use the XForm.
1696fe6060f1SDimitry Andric   if ((OpC == PPC::LXVP || OpC == PPC::STXVP) &&
1697fe6060f1SDimitry Andric       (!isInt<16>(Offset) || (Offset % offsetMinAlign(MI)) != 0) &&
1698*0fca6ea1SDimitry Andric       Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) {
1699fe6060f1SDimitry Andric     unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP;
1700fe6060f1SDimitry Andric     MI.setDesc(TII.get(NewOpc));
1701fe6060f1SDimitry Andric     OpC = NewOpc;
1702fe6060f1SDimitry Andric   }
1703fe6060f1SDimitry Andric 
17040b57cec5SDimitry Andric   // If we can, encode the offset directly into the instruction.  If this is a
17050b57cec5SDimitry Andric   // normal PPC "ri" instruction, any 16-bit value can be safely encoded.  If
17060b57cec5SDimitry Andric   // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
17070b57cec5SDimitry Andric   // clear can be encoded.  This is extremely uncommon, because normally you
17080b57cec5SDimitry Andric   // only "std" to a stack slot that is at least 4-byte aligned, but it can
17090b57cec5SDimitry Andric   // happen in invalid code.
17100b57cec5SDimitry Andric   assert(OpC != PPC::DBG_VALUE &&
17110b57cec5SDimitry Andric          "This should be handled in a target-independent way");
1712fe6060f1SDimitry Andric   // FIXME: This should be factored out to a separate function as prefixed
1713fe6060f1SDimitry Andric   // instructions add a number of opcodes for which we can use 34-bit imm.
17140b57cec5SDimitry Andric   bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ?
17150b57cec5SDimitry Andric                             isUInt<8>(Offset) :
17160b57cec5SDimitry Andric                             isInt<16>(Offset);
1717349cc55cSDimitry Andric   if (TII.isPrefixed(MI.getOpcode()))
1718fe6060f1SDimitry Andric     OffsetFitsMnemonic = isInt<34>(Offset);
17190b57cec5SDimitry Andric   if (!noImmForm && ((OffsetFitsMnemonic &&
17200b57cec5SDimitry Andric                       ((Offset % offsetMinAlign(MI)) == 0)) ||
17210b57cec5SDimitry Andric                      OpC == TargetOpcode::STACKMAP ||
17220b57cec5SDimitry Andric                      OpC == TargetOpcode::PATCHPOINT)) {
17230b57cec5SDimitry Andric     MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1724bdd1243dSDimitry Andric     return false;
17250b57cec5SDimitry Andric   }
17260b57cec5SDimitry Andric 
17270b57cec5SDimitry Andric   // The offset doesn't fit into a single register, scavenge one to build the
17280b57cec5SDimitry Andric   // offset in.
17290b57cec5SDimitry Andric 
17300b57cec5SDimitry Andric   bool is64Bit = TM.isPPC64();
17310b57cec5SDimitry Andric   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
17320b57cec5SDimitry Andric   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
17330b57cec5SDimitry Andric   const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
173481ad6265SDimitry Andric   unsigned NewOpcode = 0u;
1735bdd1243dSDimitry Andric   bool ScavengingFailed = RS && RS->getRegsAvailable(RC).none() &&
1736bdd1243dSDimitry Andric                           RS->getRegsAvailable(&PPC::VSFRCRegClass).any();
1737bdd1243dSDimitry Andric   Register SRegHi, SReg, VSReg;
1738bdd1243dSDimitry Andric 
1739bdd1243dSDimitry Andric   // The register scavenger is unable to get a GPR but can get a VSR. We
1740bdd1243dSDimitry Andric   // need to stash a GPR into a VSR so that we can free one up.
1741bdd1243dSDimitry Andric   if (ScavengingFailed && Subtarget.hasDirectMove()) {
1742bdd1243dSDimitry Andric     // Pick a volatile register and if we are spilling/restoring that
1743bdd1243dSDimitry Andric     // particular one, pick the next one.
1744bdd1243dSDimitry Andric     SRegHi = SReg = is64Bit ? PPC::X4 : PPC::R4;
1745bdd1243dSDimitry Andric     if (MI.getOperand(0).getReg() == SReg)
1746bdd1243dSDimitry Andric       SRegHi = SReg = SReg + 1;
1747bdd1243dSDimitry Andric     VSReg = MF.getRegInfo().createVirtualRegister(&PPC::VSFRCRegClass);
1748bdd1243dSDimitry Andric     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::MTVSRD : PPC::MTVSRWZ), VSReg)
1749bdd1243dSDimitry Andric         .addReg(SReg);
1750bdd1243dSDimitry Andric   } else {
1751bdd1243dSDimitry Andric     SRegHi = MF.getRegInfo().createVirtualRegister(RC);
1752bdd1243dSDimitry Andric     SReg = MF.getRegInfo().createVirtualRegister(RC);
1753bdd1243dSDimitry Andric   }
17540b57cec5SDimitry Andric 
17550b57cec5SDimitry Andric   // Insert a set of rA with the full offset value before the ld, st, or add
17560b57cec5SDimitry Andric   if (isInt<16>(Offset))
17570b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
17580b57cec5SDimitry Andric         .addImm(Offset);
175981ad6265SDimitry Andric   else if (isInt<32>(Offset)) {
17600b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
17610b57cec5SDimitry Andric         .addImm(Offset >> 16);
17620b57cec5SDimitry Andric     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
17630b57cec5SDimitry Andric         .addReg(SRegHi, RegState::Kill)
17640b57cec5SDimitry Andric         .addImm(Offset);
176581ad6265SDimitry Andric   } else {
176681ad6265SDimitry Andric     assert(is64Bit && "Huge stack is only supported on PPC64");
176781ad6265SDimitry Andric     TII.materializeImmPostRA(MBB, II, dl, SReg, Offset);
17680b57cec5SDimitry Andric   }
17690b57cec5SDimitry Andric 
17700b57cec5SDimitry Andric   // Convert into indexed form of the instruction:
17710b57cec5SDimitry Andric   //
17720b57cec5SDimitry Andric   //   sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
17730b57cec5SDimitry Andric   //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
17740b57cec5SDimitry Andric   unsigned OperandBase;
17750b57cec5SDimitry Andric 
17760b57cec5SDimitry Andric   if (noImmForm)
17770b57cec5SDimitry Andric     OperandBase = 1;
17780b57cec5SDimitry Andric   else if (OpC != TargetOpcode::INLINEASM &&
17790b57cec5SDimitry Andric            OpC != TargetOpcode::INLINEASM_BR) {
17800b57cec5SDimitry Andric     assert(ImmToIdxMap.count(OpC) &&
17810b57cec5SDimitry Andric            "No indexed form of load or store available!");
178281ad6265SDimitry Andric     NewOpcode = ImmToIdxMap.find(OpC)->second;
17830b57cec5SDimitry Andric     MI.setDesc(TII.get(NewOpcode));
17840b57cec5SDimitry Andric     OperandBase = 1;
17850b57cec5SDimitry Andric   } else {
17860b57cec5SDimitry Andric     OperandBase = OffsetOperandNo;
17870b57cec5SDimitry Andric   }
17880b57cec5SDimitry Andric 
17898bcb0991SDimitry Andric   Register StackReg = MI.getOperand(FIOperandNum).getReg();
17900b57cec5SDimitry Andric   MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
17910b57cec5SDimitry Andric   MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
179281ad6265SDimitry Andric 
1793bdd1243dSDimitry Andric   // If we stashed a value from a GPR into a VSR, we need to get it back after
1794bdd1243dSDimitry Andric   // spilling the register.
1795bdd1243dSDimitry Andric   if (ScavengingFailed && Subtarget.hasDirectMove())
1796bdd1243dSDimitry Andric     BuildMI(MBB, ++II, dl, TII.get(is64Bit ? PPC::MFVSRD : PPC::MFVSRWZ), SReg)
1797bdd1243dSDimitry Andric         .addReg(VSReg);
1798bdd1243dSDimitry Andric 
179981ad6265SDimitry Andric   // Since these are not real X-Form instructions, we must
180081ad6265SDimitry Andric   // add the registers and access 0(NewReg) rather than
180181ad6265SDimitry Andric   // emitting the X-Form pseudo.
180281ad6265SDimitry Andric   if (NewOpcode == PPC::LQX_PSEUDO || NewOpcode == PPC::STQX_PSEUDO) {
180381ad6265SDimitry Andric     assert(is64Bit && "Quadword loads/stores only supported in 64-bit mode");
180481ad6265SDimitry Andric     Register NewReg = MF.getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
180581ad6265SDimitry Andric     BuildMI(MBB, II, dl, TII.get(PPC::ADD8), NewReg)
180681ad6265SDimitry Andric         .addReg(SReg, RegState::Kill)
180781ad6265SDimitry Andric         .addReg(StackReg);
180881ad6265SDimitry Andric     MI.setDesc(TII.get(NewOpcode == PPC::LQX_PSEUDO ? PPC::LQ : PPC::STQ));
180981ad6265SDimitry Andric     MI.getOperand(OperandBase + 1).ChangeToRegister(NewReg, false);
181081ad6265SDimitry Andric     MI.getOperand(OperandBase).ChangeToImmediate(0);
181181ad6265SDimitry Andric   }
1812bdd1243dSDimitry Andric   return false;
18130b57cec5SDimitry Andric }
18140b57cec5SDimitry Andric 
18150b57cec5SDimitry Andric Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
18160b57cec5SDimitry Andric   const PPCFrameLowering *TFI = getFrameLowering(MF);
18170b57cec5SDimitry Andric 
18180b57cec5SDimitry Andric   if (!TM.isPPC64())
18190b57cec5SDimitry Andric     return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
18200b57cec5SDimitry Andric   else
18210b57cec5SDimitry Andric     return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
18220b57cec5SDimitry Andric }
18230b57cec5SDimitry Andric 
18240b57cec5SDimitry Andric Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
18250b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
18260b57cec5SDimitry Andric   if (!hasBasePointer(MF))
18270b57cec5SDimitry Andric     return getFrameRegister(MF);
18280b57cec5SDimitry Andric 
18290b57cec5SDimitry Andric   if (TM.isPPC64())
18300b57cec5SDimitry Andric     return PPC::X30;
18310b57cec5SDimitry Andric 
18320b57cec5SDimitry Andric   if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
18330b57cec5SDimitry Andric     return PPC::R29;
18340b57cec5SDimitry Andric 
18350b57cec5SDimitry Andric   return PPC::R30;
18360b57cec5SDimitry Andric }
18370b57cec5SDimitry Andric 
18380b57cec5SDimitry Andric bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
18390b57cec5SDimitry Andric   if (!EnableBasePointer)
18400b57cec5SDimitry Andric     return false;
18410b57cec5SDimitry Andric   if (AlwaysBasePointer)
18420b57cec5SDimitry Andric     return true;
18430b57cec5SDimitry Andric 
18440b57cec5SDimitry Andric   // If we need to realign the stack, then the stack pointer can no longer
18450b57cec5SDimitry Andric   // serve as an offset into the caller's stack space. As a result, we need a
18460b57cec5SDimitry Andric   // base pointer.
1847fe6060f1SDimitry Andric   return hasStackRealignment(MF);
18480b57cec5SDimitry Andric }
18490b57cec5SDimitry Andric 
18500b57cec5SDimitry Andric /// Returns true if the instruction's frame index
18510b57cec5SDimitry Andric /// reference would be better served by a base register other than FP
18520b57cec5SDimitry Andric /// or SP. Used by LocalStackFrameAllocation to determine which frame index
18530b57cec5SDimitry Andric /// references it should create new base registers for.
18540b57cec5SDimitry Andric bool PPCRegisterInfo::
18550b57cec5SDimitry Andric needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
18560b57cec5SDimitry Andric   assert(Offset < 0 && "Local offset must be negative");
18570b57cec5SDimitry Andric 
18580b57cec5SDimitry Andric   // It's the load/store FI references that cause issues, as it can be difficult
18590b57cec5SDimitry Andric   // to materialize the offset if it won't fit in the literal field. Estimate
18600b57cec5SDimitry Andric   // based on the size of the local frame and some conservative assumptions
18610b57cec5SDimitry Andric   // about the rest of the stack frame (note, this is pre-regalloc, so
18620b57cec5SDimitry Andric   // we don't know everything for certain yet) whether this offset is likely
18630b57cec5SDimitry Andric   // to be out of range of the immediate. Return true if so.
18640b57cec5SDimitry Andric 
18650b57cec5SDimitry Andric   // We only generate virtual base registers for loads and stores that have
18660b57cec5SDimitry Andric   // an r+i form. Return false for everything else.
18670b57cec5SDimitry Andric   unsigned OpC = MI->getOpcode();
18680b57cec5SDimitry Andric   if (!ImmToIdxMap.count(OpC))
18690b57cec5SDimitry Andric     return false;
18700b57cec5SDimitry Andric 
18710b57cec5SDimitry Andric   // Don't generate a new virtual base register just to add zero to it.
18720b57cec5SDimitry Andric   if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
18730b57cec5SDimitry Andric       MI->getOperand(2).getImm() == 0)
18740b57cec5SDimitry Andric     return false;
18750b57cec5SDimitry Andric 
18760b57cec5SDimitry Andric   MachineBasicBlock &MBB = *MI->getParent();
18770b57cec5SDimitry Andric   MachineFunction &MF = *MBB.getParent();
18780b57cec5SDimitry Andric   const PPCFrameLowering *TFI = getFrameLowering(MF);
18790b57cec5SDimitry Andric   unsigned StackEst = TFI->determineFrameLayout(MF, true);
18800b57cec5SDimitry Andric 
18810b57cec5SDimitry Andric   // If we likely don't need a stack frame, then we probably don't need a
18820b57cec5SDimitry Andric   // virtual base register either.
18830b57cec5SDimitry Andric   if (!StackEst)
18840b57cec5SDimitry Andric     return false;
18850b57cec5SDimitry Andric 
18860b57cec5SDimitry Andric   // Estimate an offset from the stack pointer.
18870b57cec5SDimitry Andric   // The incoming offset is relating to the SP at the start of the function,
18880b57cec5SDimitry Andric   // but when we access the local it'll be relative to the SP after local
18890b57cec5SDimitry Andric   // allocation, so adjust our SP-relative offset by that allocation size.
18900b57cec5SDimitry Andric   Offset += StackEst;
18910b57cec5SDimitry Andric 
18920b57cec5SDimitry Andric   // The frame pointer will point to the end of the stack, so estimate the
18930b57cec5SDimitry Andric   // offset as the difference between the object offset and the FP location.
18940b57cec5SDimitry Andric   return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
18950b57cec5SDimitry Andric }
18960b57cec5SDimitry Andric 
18970b57cec5SDimitry Andric /// Insert defining instruction(s) for BaseReg to
18980b57cec5SDimitry Andric /// be a pointer to FrameIdx at the beginning of the basic block.
1899e8d8bef9SDimitry Andric Register PPCRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
19005ffd83dbSDimitry Andric                                                        int FrameIdx,
19010b57cec5SDimitry Andric                                                        int64_t Offset) const {
19020b57cec5SDimitry Andric   unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
19030b57cec5SDimitry Andric 
19040b57cec5SDimitry Andric   MachineBasicBlock::iterator Ins = MBB->begin();
19050b57cec5SDimitry Andric   DebugLoc DL;                  // Defaults to "unknown"
19060b57cec5SDimitry Andric   if (Ins != MBB->end())
19070b57cec5SDimitry Andric     DL = Ins->getDebugLoc();
19080b57cec5SDimitry Andric 
19090b57cec5SDimitry Andric   const MachineFunction &MF = *MBB->getParent();
19100b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
19110b57cec5SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
19120b57cec5SDimitry Andric   const MCInstrDesc &MCID = TII.get(ADDriOpc);
19130b57cec5SDimitry Andric   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1914e8d8bef9SDimitry Andric   const TargetRegisterClass *RC = getPointerRegClass(MF);
1915e8d8bef9SDimitry Andric   Register BaseReg = MRI.createVirtualRegister(RC);
19160b57cec5SDimitry Andric   MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
19170b57cec5SDimitry Andric 
19180b57cec5SDimitry Andric   BuildMI(*MBB, Ins, DL, MCID, BaseReg)
19190b57cec5SDimitry Andric     .addFrameIndex(FrameIdx).addImm(Offset);
1920e8d8bef9SDimitry Andric 
1921e8d8bef9SDimitry Andric   return BaseReg;
19220b57cec5SDimitry Andric }
19230b57cec5SDimitry Andric 
19245ffd83dbSDimitry Andric void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
19250b57cec5SDimitry Andric                                         int64_t Offset) const {
19260b57cec5SDimitry Andric   unsigned FIOperandNum = 0;
19270b57cec5SDimitry Andric   while (!MI.getOperand(FIOperandNum).isFI()) {
19280b57cec5SDimitry Andric     ++FIOperandNum;
19290b57cec5SDimitry Andric     assert(FIOperandNum < MI.getNumOperands() &&
19300b57cec5SDimitry Andric            "Instr doesn't have FrameIndex operand!");
19310b57cec5SDimitry Andric   }
19320b57cec5SDimitry Andric 
19330b57cec5SDimitry Andric   MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
19340b57cec5SDimitry Andric   unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
19350b57cec5SDimitry Andric   Offset += MI.getOperand(OffsetOperandNo).getImm();
19360b57cec5SDimitry Andric   MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
19370b57cec5SDimitry Andric 
19380b57cec5SDimitry Andric   MachineBasicBlock &MBB = *MI.getParent();
19390b57cec5SDimitry Andric   MachineFunction &MF = *MBB.getParent();
19400b57cec5SDimitry Andric   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
19410b57cec5SDimitry Andric   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
19420b57cec5SDimitry Andric   const MCInstrDesc &MCID = MI.getDesc();
19430b57cec5SDimitry Andric   MachineRegisterInfo &MRI = MF.getRegInfo();
19440b57cec5SDimitry Andric   MRI.constrainRegClass(BaseReg,
19450b57cec5SDimitry Andric                         TII.getRegClass(MCID, FIOperandNum, this, MF));
19460b57cec5SDimitry Andric }
19470b57cec5SDimitry Andric 
19480b57cec5SDimitry Andric bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
19495ffd83dbSDimitry Andric                                          Register BaseReg,
19500b57cec5SDimitry Andric                                          int64_t Offset) const {
19510b57cec5SDimitry Andric   unsigned FIOperandNum = 0;
19520b57cec5SDimitry Andric   while (!MI->getOperand(FIOperandNum).isFI()) {
19530b57cec5SDimitry Andric     ++FIOperandNum;
19540b57cec5SDimitry Andric     assert(FIOperandNum < MI->getNumOperands() &&
19550b57cec5SDimitry Andric            "Instr doesn't have FrameIndex operand!");
19560b57cec5SDimitry Andric   }
19570b57cec5SDimitry Andric 
19580b57cec5SDimitry Andric   unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
19590b57cec5SDimitry Andric   Offset += MI->getOperand(OffsetOperandNo).getImm();
19600b57cec5SDimitry Andric 
19610b57cec5SDimitry Andric   return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
19620b57cec5SDimitry Andric          MI->getOpcode() == TargetOpcode::STACKMAP ||
19630b57cec5SDimitry Andric          MI->getOpcode() == TargetOpcode::PATCHPOINT ||
19640b57cec5SDimitry Andric          (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0);
19650b57cec5SDimitry Andric }
1966