1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCTargetDesc.h" 10 #include "TargetInfo/PowerPCTargetInfo.h" 11 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 12 #include "llvm/MC/MCFixedLenDisassembler.h" 13 #include "llvm/MC/MCInst.h" 14 #include "llvm/MC/MCSubtargetInfo.h" 15 #include "llvm/Support/Endian.h" 16 #include "llvm/Support/TargetRegistry.h" 17 18 using namespace llvm; 19 20 DEFINE_PPC_REGCLASSES; 21 22 #define DEBUG_TYPE "ppc-disassembler" 23 24 typedef MCDisassembler::DecodeStatus DecodeStatus; 25 26 namespace { 27 class PPCDisassembler : public MCDisassembler { 28 bool IsLittleEndian; 29 30 public: 31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 32 bool IsLittleEndian) 33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {} 34 35 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 36 ArrayRef<uint8_t> Bytes, uint64_t Address, 37 raw_ostream &VStream, 38 raw_ostream &CStream) const override; 39 }; 40 } // end anonymous namespace 41 42 static MCDisassembler *createPPCDisassembler(const Target &T, 43 const MCSubtargetInfo &STI, 44 MCContext &Ctx) { 45 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false); 46 } 47 48 static MCDisassembler *createPPCLEDisassembler(const Target &T, 49 const MCSubtargetInfo &STI, 50 MCContext &Ctx) { 51 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); 52 } 53 54 extern "C" void LLVMInitializePowerPCDisassembler() { 55 // Register the disassembler for each target. 56 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(), 57 createPPCDisassembler); 58 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(), 59 createPPCDisassembler); 60 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(), 61 createPPCLEDisassembler); 62 } 63 64 static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm, 65 uint64_t Addr, 66 const void *Decoder) { 67 int32_t Offset = SignExtend32<24>(Imm); 68 Inst.addOperand(MCOperand::createImm(Offset)); 69 return MCDisassembler::Success; 70 } 71 72 // FIXME: These can be generated by TableGen from the existing register 73 // encoding values! 74 75 template <std::size_t N> 76 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 77 const MCPhysReg (&Regs)[N]) { 78 assert(RegNo < N && "Invalid register number"); 79 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 80 return MCDisassembler::Success; 81 } 82 83 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 84 uint64_t Address, 85 const void *Decoder) { 86 return decodeRegisterClass(Inst, RegNo, CRRegs); 87 } 88 89 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 90 uint64_t Address, 91 const void *Decoder) { 92 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 93 } 94 95 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 96 uint64_t Address, 97 const void *Decoder) { 98 return decodeRegisterClass(Inst, RegNo, FRegs); 99 } 100 101 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 102 uint64_t Address, 103 const void *Decoder) { 104 return decodeRegisterClass(Inst, RegNo, FRegs); 105 } 106 107 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 108 uint64_t Address, 109 const void *Decoder) { 110 return decodeRegisterClass(Inst, RegNo, VFRegs); 111 } 112 113 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 114 uint64_t Address, 115 const void *Decoder) { 116 return decodeRegisterClass(Inst, RegNo, VRegs); 117 } 118 119 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 120 uint64_t Address, 121 const void *Decoder) { 122 return decodeRegisterClass(Inst, RegNo, VSRegs); 123 } 124 125 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 126 uint64_t Address, 127 const void *Decoder) { 128 return decodeRegisterClass(Inst, RegNo, VSFRegs); 129 } 130 131 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 132 uint64_t Address, 133 const void *Decoder) { 134 return decodeRegisterClass(Inst, RegNo, VSSRegs); 135 } 136 137 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 138 uint64_t Address, 139 const void *Decoder) { 140 return decodeRegisterClass(Inst, RegNo, RRegs); 141 } 142 143 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, 144 uint64_t Address, 145 const void *Decoder) { 146 return decodeRegisterClass(Inst, RegNo, RRegsNoR0); 147 } 148 149 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 150 uint64_t Address, 151 const void *Decoder) { 152 return decodeRegisterClass(Inst, RegNo, XRegs); 153 } 154 155 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, 156 uint64_t Address, 157 const void *Decoder) { 158 return decodeRegisterClass(Inst, RegNo, XRegsNoX0); 159 } 160 161 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 162 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 163 164 static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 165 uint64_t Address, 166 const void *Decoder) { 167 return decodeRegisterClass(Inst, RegNo, QFRegs); 168 } 169 170 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, 171 uint64_t Address, 172 const void *Decoder) { 173 return decodeRegisterClass(Inst, RegNo, SPERegs); 174 } 175 176 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass 177 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass 178 179 template<unsigned N> 180 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 181 int64_t Address, const void *Decoder) { 182 assert(isUInt<N>(Imm) && "Invalid immediate"); 183 Inst.addOperand(MCOperand::createImm(Imm)); 184 return MCDisassembler::Success; 185 } 186 187 template<unsigned N> 188 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 189 int64_t Address, const void *Decoder) { 190 assert(isUInt<N>(Imm) && "Invalid immediate"); 191 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 192 return MCDisassembler::Success; 193 } 194 195 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 196 int64_t Address, const void *Decoder) { 197 // Decode the memri field (imm, reg), which has the low 16-bits as the 198 // displacement and the next 5 bits as the register #. 199 200 uint64_t Base = Imm >> 16; 201 uint64_t Disp = Imm & 0xFFFF; 202 203 assert(Base < 32 && "Invalid base register"); 204 205 switch (Inst.getOpcode()) { 206 default: break; 207 case PPC::LBZU: 208 case PPC::LHAU: 209 case PPC::LHZU: 210 case PPC::LWZU: 211 case PPC::LFSU: 212 case PPC::LFDU: 213 // Add the tied output operand. 214 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 215 break; 216 case PPC::STBU: 217 case PPC::STHU: 218 case PPC::STWU: 219 case PPC::STFSU: 220 case PPC::STFDU: 221 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 222 break; 223 } 224 225 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); 226 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 227 return MCDisassembler::Success; 228 } 229 230 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 231 int64_t Address, const void *Decoder) { 232 // Decode the memrix field (imm, reg), which has the low 14-bits as the 233 // displacement and the next 5 bits as the register #. 234 235 uint64_t Base = Imm >> 14; 236 uint64_t Disp = Imm & 0x3FFF; 237 238 assert(Base < 32 && "Invalid base register"); 239 240 if (Inst.getOpcode() == PPC::LDU) 241 // Add the tied output operand. 242 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 243 else if (Inst.getOpcode() == PPC::STDU) 244 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 245 246 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); 247 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 248 return MCDisassembler::Success; 249 } 250 251 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, 252 int64_t Address, const void *Decoder) { 253 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the 254 // displacement with 16-byte aligned, and the next 5 bits as the register #. 255 256 uint64_t Base = Imm >> 12; 257 uint64_t Disp = Imm & 0xFFF; 258 259 assert(Base < 32 && "Invalid base register"); 260 261 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); 262 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 263 return MCDisassembler::Success; 264 } 265 266 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, 267 int64_t Address, const void *Decoder) { 268 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the 269 // displacement with 8-byte aligned, and the next 5 bits as the register #. 270 271 uint64_t Base = Imm >> 5; 272 uint64_t Disp = Imm & 0x1F; 273 274 assert(Base < 32 && "Invalid base register"); 275 276 Inst.addOperand(MCOperand::createImm(Disp << 3)); 277 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 278 return MCDisassembler::Success; 279 } 280 281 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, 282 int64_t Address, const void *Decoder) { 283 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the 284 // displacement with 4-byte aligned, and the next 5 bits as the register #. 285 286 uint64_t Base = Imm >> 5; 287 uint64_t Disp = Imm & 0x1F; 288 289 assert(Base < 32 && "Invalid base register"); 290 291 Inst.addOperand(MCOperand::createImm(Disp << 2)); 292 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 293 return MCDisassembler::Success; 294 } 295 296 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, 297 int64_t Address, const void *Decoder) { 298 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the 299 // displacement with 2-byte aligned, and the next 5 bits as the register #. 300 301 uint64_t Base = Imm >> 5; 302 uint64_t Disp = Imm & 0x1F; 303 304 assert(Base < 32 && "Invalid base register"); 305 306 Inst.addOperand(MCOperand::createImm(Disp << 1)); 307 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 308 return MCDisassembler::Success; 309 } 310 311 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 312 int64_t Address, const void *Decoder) { 313 // The cr bit encoding is 0x80 >> cr_reg_num. 314 315 unsigned Zeros = countTrailingZeros(Imm); 316 assert(Zeros < 8 && "Invalid CR bit value"); 317 318 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); 319 return MCDisassembler::Success; 320 } 321 322 #include "PPCGenDisassemblerTables.inc" 323 324 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 325 ArrayRef<uint8_t> Bytes, 326 uint64_t Address, raw_ostream &OS, 327 raw_ostream &CS) const { 328 // Get the four bytes of the instruction. 329 Size = 4; 330 if (Bytes.size() < 4) { 331 Size = 0; 332 return MCDisassembler::Fail; 333 } 334 335 // Read the instruction in the proper endianness. 336 uint32_t Inst = IsLittleEndian ? support::endian::read32le(Bytes.data()) 337 : support::endian::read32be(Bytes.data()); 338 339 if (STI.getFeatureBits()[PPC::FeatureQPX]) { 340 DecodeStatus result = 341 decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI); 342 if (result != MCDisassembler::Fail) 343 return result; 344 } else if (STI.getFeatureBits()[PPC::FeatureSPE]) { 345 DecodeStatus result = 346 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI); 347 if (result != MCDisassembler::Fail) 348 return result; 349 } 350 351 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 352 } 353 354