10b57cec5SDimitry Andric//===- MipsEVAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file describes Mips32r6 instruction formats. 100b57cec5SDimitry Andric// 110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andricclass MipsEVAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, 140b57cec5SDimitry Andric StdArch { 150b57cec5SDimitry Andric let DecoderNamespace = "Mips"; 160b57cec5SDimitry Andric let EncodingPredicates = [HasStdEnc]; 170b57cec5SDimitry Andric} 180b57cec5SDimitry Andric 190b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 200b57cec5SDimitry Andric// 210b57cec5SDimitry Andric// Field Values 220b57cec5SDimitry Andric// 230b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric// Memory Load/Store EVA 260b57cec5SDimitry Andricdef OPCODE6_LBE : OPCODE6<0b101100>; 270b57cec5SDimitry Andricdef OPCODE6_LBuE : OPCODE6<0b101000>; 280b57cec5SDimitry Andricdef OPCODE6_LHE : OPCODE6<0b101101>; 290b57cec5SDimitry Andricdef OPCODE6_LHuE : OPCODE6<0b101001>; 300b57cec5SDimitry Andricdef OPCODE6_LWE : OPCODE6<0b101111>; 310b57cec5SDimitry Andric 320b57cec5SDimitry Andricdef OPCODE6_SBE : OPCODE6<0b011100>; 330b57cec5SDimitry Andricdef OPCODE6_SHE : OPCODE6<0b011101>; 340b57cec5SDimitry Andricdef OPCODE6_SWE : OPCODE6<0b011111>; 350b57cec5SDimitry Andric 360b57cec5SDimitry Andric// load/store left/right EVA 370b57cec5SDimitry Andricdef OPCODE6_LWLE : OPCODE6<0b011001>; 380b57cec5SDimitry Andricdef OPCODE6_LWRE : OPCODE6<0b011010>; 390b57cec5SDimitry Andricdef OPCODE6_SWLE : OPCODE6<0b100001>; 400b57cec5SDimitry Andricdef OPCODE6_SWRE : OPCODE6<0b100010>; 410b57cec5SDimitry Andric 420b57cec5SDimitry Andric// Load-linked EVA, Store-conditional EVA 430b57cec5SDimitry Andricdef OPCODE6_LLE : OPCODE6<0b101110>; 440b57cec5SDimitry Andricdef OPCODE6_SCE : OPCODE6<0b011110>; 450b57cec5SDimitry Andric 460b57cec5SDimitry Andricdef OPCODE6_TLBINV : OPCODE6<0b000011>; 470b57cec5SDimitry Andricdef OPCODE6_TLBINVF : OPCODE6<0b000100>; 480b57cec5SDimitry Andric 490b57cec5SDimitry Andricdef OPCODE6_CACHEE : OPCODE6<0b011011>; 500b57cec5SDimitry Andricdef OPCODE6_PREFE : OPCODE6<0b100011>; 510b57cec5SDimitry Andric 520b57cec5SDimitry Andricdef OPGROUP_COP0_TLB : OPGROUP<0b010000>; 530b57cec5SDimitry Andric 540b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 550b57cec5SDimitry Andric// 560b57cec5SDimitry Andric// Encoding Formats 570b57cec5SDimitry Andric// 580b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 590b57cec5SDimitry Andric 600b57cec5SDimitry Andricclass SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6 Operation> : MipsEVAInst { 610b57cec5SDimitry Andric bits<21> addr; 62*bdd1243dSDimitry Andric bits<5> rt; 630b57cec5SDimitry Andric bits<5> base = addr{20-16}; 640b57cec5SDimitry Andric bits<9> offset = addr{8-0}; 650b57cec5SDimitry Andric 660b57cec5SDimitry Andric bits<32> Inst; 670b57cec5SDimitry Andric 680b57cec5SDimitry Andric let Inst{31-26} = OPGROUP_SPECIAL3.Value; 690b57cec5SDimitry Andric let Inst{25-21} = base; 70*bdd1243dSDimitry Andric let Inst{20-16} = rt; 710b57cec5SDimitry Andric let Inst{15-7} = offset; 720b57cec5SDimitry Andric let Inst{6} = 0; 730b57cec5SDimitry Andric let Inst{5-0} = Operation.Value; 740b57cec5SDimitry Andric} 750b57cec5SDimitry Andric 760b57cec5SDimitry Andricclass TLB_FM<OPCODE6 Operation> : MipsEVAInst { 770b57cec5SDimitry Andric bits<32> Inst; 780b57cec5SDimitry Andric 790b57cec5SDimitry Andric let Inst{31-26} = OPGROUP_COP0_TLB.Value; 800b57cec5SDimitry Andric let Inst{25} = 1; // CO 810b57cec5SDimitry Andric let Inst{24-6} = 0; 820b57cec5SDimitry Andric let Inst{5-0} = Operation.Value; 830b57cec5SDimitry Andric} 84