1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the Mips Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/MipsMCTargetDesc.h" 14 #include "Mips.h" 15 #include "TargetInfo/MipsTargetInfo.h" 16 #include "llvm/ADT/ArrayRef.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "mips-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 class MipsDisassembler : public MCDisassembler { 41 bool IsMicroMips; 42 bool IsBigEndian; 43 44 public: 45 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian) 46 : MCDisassembler(STI, Ctx), 47 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]), 48 IsBigEndian(IsBigEndian) {} 49 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; } 51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; } 52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; } 53 54 bool hasMips32r6() const { 55 return STI.getFeatureBits()[Mips::FeatureMips32r6]; 56 } 57 58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } 59 60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } 61 62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; } 63 64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; } 65 66 bool hasCnMipsP() const { return STI.getFeatureBits()[Mips::FeatureCnMipsP]; } 67 68 bool hasCOP3() const { 69 // Only present in MIPS-I and MIPS-II 70 return !hasMips32() && !hasMips3(); 71 } 72 73 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 74 ArrayRef<uint8_t> Bytes, uint64_t Address, 75 raw_ostream &VStream, 76 raw_ostream &CStream) const override; 77 }; 78 79 } // end anonymous namespace 80 81 // Forward declare these because the autogenerated code will reference them. 82 // Definitions are further down. 83 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 84 unsigned RegNo, 85 uint64_t Address, 86 const void *Decoder); 87 88 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 89 unsigned RegNo, 90 uint64_t Address, 91 const void *Decoder); 92 93 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 94 unsigned RegNo, 95 uint64_t Address, 96 const void *Decoder); 97 98 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 99 unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102 103 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 104 unsigned RegNo, 105 uint64_t Address, 106 const void *Decoder); 107 108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 109 unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 114 unsigned Insn, 115 uint64_t Address, 116 const void *Decoder); 117 118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 129 unsigned RegNo, 130 uint64_t Address, 131 const void *Decoder); 132 133 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 134 unsigned RegNo, 135 uint64_t Address, 136 const void *Decoder); 137 138 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 139 unsigned RegNo, 140 uint64_t Address, 141 const void *Decoder); 142 143 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 147 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 148 unsigned Insn, 149 uint64_t Address, 150 const void *Decoder); 151 152 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 153 unsigned RegNo, 154 uint64_t Address, 155 const void *Decoder); 156 157 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 158 unsigned RegNo, 159 uint64_t Address, 160 const void *Decoder); 161 162 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 163 unsigned RegNo, 164 uint64_t Address, 165 const void *Decoder); 166 167 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 168 unsigned RegNo, 169 uint64_t Address, 170 const void *Decoder); 171 172 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 173 unsigned RegNo, 174 uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 178 unsigned RegNo, 179 uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 183 unsigned RegNo, 184 uint64_t Address, 185 const void *Decoder); 186 187 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 188 unsigned RegNo, 189 uint64_t Address, 190 const void *Decoder); 191 192 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 193 unsigned RegNo, 194 uint64_t Address, 195 const void *Decoder); 196 197 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 198 unsigned RegNo, 199 uint64_t Address, 200 const void *Decoder); 201 202 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 203 unsigned RegNo, 204 uint64_t Address, 205 const void *Decoder); 206 207 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 208 unsigned Offset, 209 uint64_t Address, 210 const void *Decoder); 211 212 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 213 unsigned Offset, 214 uint64_t Address, 215 const void *Decoder); 216 217 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 218 unsigned Insn, 219 uint64_t Address, 220 const void *Decoder); 221 222 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 223 unsigned Offset, 224 uint64_t Address, 225 const void *Decoder); 226 227 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 228 unsigned Offset, 229 uint64_t Address, 230 const void *Decoder); 231 232 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 233 unsigned Offset, 234 uint64_t Address, 235 const void *Decoder); 236 237 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is 238 // shifted left by 1 bit. 239 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 240 unsigned Offset, 241 uint64_t Address, 242 const void *Decoder); 243 244 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is 245 // shifted left by 1 bit. 246 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 247 unsigned Offset, 248 uint64_t Address, 249 const void *Decoder); 250 251 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is 252 // shifted left by 1 bit. 253 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 254 unsigned Offset, 255 uint64_t Address, 256 const void *Decoder); 257 258 // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is 259 // shifted left by 1 bit. 260 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 261 unsigned Offset, 262 uint64_t Address, 263 const void *Decoder); 264 265 // DecodeJumpTargetMM - Decode microMIPS jump target, which is 266 // shifted left by 1 bit. 267 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 268 unsigned Insn, 269 uint64_t Address, 270 const void *Decoder); 271 272 // DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target, 273 // which is shifted left by 2 bit. 274 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, 275 unsigned Insn, 276 uint64_t Address, 277 const void *Decoder); 278 279 static DecodeStatus DecodeMem(MCInst &Inst, 280 unsigned Insn, 281 uint64_t Address, 282 const void *Decoder); 283 284 static DecodeStatus DecodeMemEVA(MCInst &Inst, 285 unsigned Insn, 286 uint64_t Address, 287 const void *Decoder); 288 289 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 290 unsigned Insn, 291 uint64_t Address, 292 const void *Decoder); 293 294 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, 295 const void *Decoder); 296 297 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 298 unsigned Insn, 299 uint64_t Address, 300 const void *Decoder); 301 302 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 303 unsigned Insn, 304 uint64_t Address, 305 const void *Decoder); 306 307 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 308 unsigned Insn, 309 uint64_t Address, 310 const void *Decoder); 311 312 static DecodeStatus DecodeSyncI(MCInst &Inst, 313 unsigned Insn, 314 uint64_t Address, 315 const void *Decoder); 316 317 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, 318 unsigned Insn, 319 uint64_t Address, 320 const void *Decoder); 321 322 static DecodeStatus DecodeSynciR6(MCInst &Inst, 323 unsigned Insn, 324 uint64_t Address, 325 const void *Decoder); 326 327 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 328 uint64_t Address, const void *Decoder); 329 330 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 331 unsigned Insn, 332 uint64_t Address, 333 const void *Decoder); 334 335 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 336 unsigned Insn, 337 uint64_t Address, 338 const void *Decoder); 339 340 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 341 unsigned Insn, 342 uint64_t Address, 343 const void *Decoder); 344 345 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 346 unsigned Insn, 347 uint64_t Address, 348 const void *Decoder); 349 350 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 351 unsigned Insn, 352 uint64_t Address, 353 const void *Decoder); 354 355 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 356 unsigned Insn, 357 uint64_t Address, 358 const void *Decoder); 359 360 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 361 unsigned Insn, 362 uint64_t Address, 363 const void *Decoder); 364 365 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, 366 uint64_t Address, 367 const void *Decoder); 368 369 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 370 uint64_t Address, 371 const void *Decoder); 372 373 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, 374 const void *Decoder); 375 376 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, 377 const void *Decoder); 378 379 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 382 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 383 uint64_t Address, 384 const void *Decoder); 385 386 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 387 unsigned Insn, 388 uint64_t Address, 389 const void *Decoder); 390 391 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 392 unsigned Value, 393 uint64_t Address, 394 const void *Decoder); 395 396 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 397 unsigned Value, 398 uint64_t Address, 399 const void *Decoder); 400 401 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 402 unsigned Value, 403 uint64_t Address, 404 const void *Decoder); 405 406 template <unsigned Bits, int Offset, int Scale> 407 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 408 uint64_t Address, 409 const void *Decoder); 410 411 template <unsigned Bits, int Offset> 412 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, 413 uint64_t Address, 414 const void *Decoder) { 415 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address, 416 Decoder); 417 } 418 419 template <unsigned Bits, int Offset = 0, int ScaleBy = 1> 420 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 421 uint64_t Address, 422 const void *Decoder); 423 424 static DecodeStatus DecodeInsSize(MCInst &Inst, 425 unsigned Insn, 426 uint64_t Address, 427 const void *Decoder); 428 429 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 430 uint64_t Address, const void *Decoder); 431 432 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 433 uint64_t Address, const void *Decoder); 434 435 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 436 uint64_t Address, const void *Decoder); 437 438 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 439 uint64_t Address, const void *Decoder); 440 441 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 442 uint64_t Address, const void *Decoder); 443 444 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't 445 /// handle. 446 template <typename InsnType> 447 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 448 const void *Decoder); 449 450 template <typename InsnType> 451 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 452 const void *Decoder); 453 454 template <typename InsnType> 455 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 456 const void *Decoder); 457 458 template <typename InsnType> 459 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 460 const void *Decoder); 461 462 template <typename InsnType> 463 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 464 const void *Decoder); 465 466 template <typename InsnType> 467 static DecodeStatus 468 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 469 const void *Decoder); 470 471 template <typename InsnType> 472 static DecodeStatus 473 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 474 const void *Decoder); 475 476 template <typename InsnType> 477 static DecodeStatus 478 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 479 const void *Decoder); 480 481 template <typename InsnType> 482 static DecodeStatus 483 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 484 const void *Decoder); 485 486 template <typename InsnType> 487 static DecodeStatus 488 DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 489 const void *Decoder); 490 491 template <typename InsnType> 492 static DecodeStatus 493 DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 494 const void *Decoder); 495 496 template <typename InsnType> 497 static DecodeStatus 498 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 499 const void *Decoder); 500 501 template <typename InsnType> 502 static DecodeStatus 503 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 504 const void *Decoder); 505 506 template <typename InsnType> 507 static DecodeStatus 508 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 509 const void *Decoder); 510 511 template <typename InsnType> 512 static DecodeStatus 513 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, 514 const void *Decoder); 515 516 template <typename InsnType> 517 static DecodeStatus 518 DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 519 const void *Decoder); 520 521 template <typename InsnType> 522 static DecodeStatus 523 DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, 524 const void *Decoder); 525 526 template <typename InsnType> 527 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 528 const void *Decoder); 529 530 template <typename InsnType> 531 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 532 const void *Decoder); 533 534 template <typename InsnType> 535 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 536 const void *Decoder); 537 538 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, 539 uint64_t Address, 540 const void *Decoder); 541 542 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 543 uint64_t Address, 544 const void *Decoder); 545 546 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 547 uint64_t Address, 548 const void *Decoder); 549 550 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 551 uint64_t Address, const void *Decoder); 552 553 static MCDisassembler *createMipsDisassembler( 554 const Target &T, 555 const MCSubtargetInfo &STI, 556 MCContext &Ctx) { 557 return new MipsDisassembler(STI, Ctx, true); 558 } 559 560 static MCDisassembler *createMipselDisassembler( 561 const Target &T, 562 const MCSubtargetInfo &STI, 563 MCContext &Ctx) { 564 return new MipsDisassembler(STI, Ctx, false); 565 } 566 567 extern "C" void LLVMInitializeMipsDisassembler() { 568 // Register the disassembler. 569 TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), 570 createMipsDisassembler); 571 TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), 572 createMipselDisassembler); 573 TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), 574 createMipsDisassembler); 575 TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), 576 createMipselDisassembler); 577 } 578 579 #include "MipsGenDisassemblerTables.inc" 580 581 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 582 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D); 583 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo(); 584 return *(RegInfo->getRegClass(RC).begin() + RegNo); 585 } 586 587 template <typename InsnType> 588 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, 589 const void *Decoder) { 590 using DecodeFN = DecodeStatus (*)(MCInst &, unsigned, uint64_t, const void *); 591 592 // The size of the n field depends on the element size 593 // The register class also depends on this. 594 InsnType tmp = fieldFromInstruction(insn, 17, 5); 595 unsigned NSize = 0; 596 DecodeFN RegDecoder = nullptr; 597 if ((tmp & 0x18) == 0x00) { // INSVE_B 598 NSize = 4; 599 RegDecoder = DecodeMSA128BRegisterClass; 600 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H 601 NSize = 3; 602 RegDecoder = DecodeMSA128HRegisterClass; 603 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W 604 NSize = 2; 605 RegDecoder = DecodeMSA128WRegisterClass; 606 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D 607 NSize = 1; 608 RegDecoder = DecodeMSA128DRegisterClass; 609 } else 610 llvm_unreachable("Invalid encoding"); 611 612 assert(NSize != 0 && RegDecoder != nullptr); 613 614 // $wd 615 tmp = fieldFromInstruction(insn, 6, 5); 616 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 617 return MCDisassembler::Fail; 618 // $wd_in 619 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 620 return MCDisassembler::Fail; 621 // $n 622 tmp = fieldFromInstruction(insn, 16, NSize); 623 MI.addOperand(MCOperand::createImm(tmp)); 624 // $ws 625 tmp = fieldFromInstruction(insn, 11, 5); 626 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) 627 return MCDisassembler::Fail; 628 // $n2 629 MI.addOperand(MCOperand::createImm(0)); 630 631 return MCDisassembler::Success; 632 } 633 634 template <typename InsnType> 635 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, 636 const void *Decoder) { 637 InsnType Rs = fieldFromInstruction(insn, 16, 5); 638 InsnType Imm = fieldFromInstruction(insn, 0, 16); 639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 640 Rs))); 641 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 642 Rs))); 643 MI.addOperand(MCOperand::createImm(Imm)); 644 645 return MCDisassembler::Success; 646 } 647 648 template <typename InsnType> 649 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, 650 const void *Decoder) { 651 InsnType Rs = fieldFromInstruction(insn, 21, 5); 652 InsnType Imm = fieldFromInstruction(insn, 0, 16); 653 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 654 Rs))); 655 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, 656 Rs))); 657 MI.addOperand(MCOperand::createImm(Imm)); 658 659 return MCDisassembler::Success; 660 } 661 662 template <typename InsnType> 663 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, 664 uint64_t Address, 665 const void *Decoder) { 666 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 667 // (otherwise we would have matched the ADDI instruction from the earlier 668 // ISA's instead). 669 // 670 // We have: 671 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii 672 // BOVC if rs >= rt 673 // BEQZALC if rs == 0 && rt != 0 674 // BEQC if rs < rt && rs != 0 675 676 InsnType Rs = fieldFromInstruction(insn, 21, 5); 677 InsnType Rt = fieldFromInstruction(insn, 16, 5); 678 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 679 bool HasRs = false; 680 681 if (Rs >= Rt) { 682 MI.setOpcode(Mips::BOVC); 683 HasRs = true; 684 } else if (Rs != 0 && Rs < Rt) { 685 MI.setOpcode(Mips::BEQC); 686 HasRs = true; 687 } else 688 MI.setOpcode(Mips::BEQZALC); 689 690 if (HasRs) 691 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 692 Rs))); 693 694 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 695 Rt))); 696 MI.addOperand(MCOperand::createImm(Imm)); 697 698 return MCDisassembler::Success; 699 } 700 701 template <typename InsnType> 702 static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, 703 uint64_t Address, 704 const void *Decoder) { 705 InsnType Rt = fieldFromInstruction(insn, 21, 5); 706 InsnType Rs = fieldFromInstruction(insn, 16, 5); 707 int64_t Imm = 0; 708 709 if (Rs >= Rt) { 710 MI.setOpcode(Mips::BOVC_MMR6); 711 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 712 Rt))); 713 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 714 Rs))); 715 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 716 } else if (Rs != 0 && Rs < Rt) { 717 MI.setOpcode(Mips::BEQC_MMR6); 718 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 719 Rs))); 720 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 721 Rt))); 722 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 723 } else { 724 MI.setOpcode(Mips::BEQZALC_MMR6); 725 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 726 Rt))); 727 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 728 } 729 730 MI.addOperand(MCOperand::createImm(Imm)); 731 732 return MCDisassembler::Success; 733 } 734 735 template <typename InsnType> 736 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, 737 uint64_t Address, 738 const void *Decoder) { 739 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 740 // (otherwise we would have matched the ADDI instruction from the earlier 741 // ISA's instead). 742 // 743 // We have: 744 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii 745 // BNVC if rs >= rt 746 // BNEZALC if rs == 0 && rt != 0 747 // BNEC if rs < rt && rs != 0 748 749 InsnType Rs = fieldFromInstruction(insn, 21, 5); 750 InsnType Rt = fieldFromInstruction(insn, 16, 5); 751 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 752 bool HasRs = false; 753 754 if (Rs >= Rt) { 755 MI.setOpcode(Mips::BNVC); 756 HasRs = true; 757 } else if (Rs != 0 && Rs < Rt) { 758 MI.setOpcode(Mips::BNEC); 759 HasRs = true; 760 } else 761 MI.setOpcode(Mips::BNEZALC); 762 763 if (HasRs) 764 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 765 Rs))); 766 767 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 768 Rt))); 769 MI.addOperand(MCOperand::createImm(Imm)); 770 771 return MCDisassembler::Success; 772 } 773 774 template <typename InsnType> 775 static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, 776 uint64_t Address, 777 const void *Decoder) { 778 InsnType Rt = fieldFromInstruction(insn, 21, 5); 779 InsnType Rs = fieldFromInstruction(insn, 16, 5); 780 int64_t Imm = 0; 781 782 if (Rs >= Rt) { 783 MI.setOpcode(Mips::BNVC_MMR6); 784 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 785 Rt))); 786 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 787 Rs))); 788 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 789 } else if (Rs != 0 && Rs < Rt) { 790 MI.setOpcode(Mips::BNEC_MMR6); 791 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 792 Rs))); 793 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 794 Rt))); 795 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 796 } else { 797 MI.setOpcode(Mips::BNEZALC_MMR6); 798 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 799 Rt))); 800 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 801 } 802 803 MI.addOperand(MCOperand::createImm(Imm)); 804 805 return MCDisassembler::Success; 806 } 807 808 template <typename InsnType> 809 static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, 810 uint64_t Address, 811 const void *Decoder) { 812 // We have: 813 // 0b110101 ttttt sssss iiiiiiiiiiiiiiii 814 // Invalid if rt == 0 815 // BGTZC_MMR6 if rs == 0 && rt != 0 816 // BLTZC_MMR6 if rs == rt && rt != 0 817 // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 818 819 InsnType Rt = fieldFromInstruction(insn, 21, 5); 820 InsnType Rs = fieldFromInstruction(insn, 16, 5); 821 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 822 bool HasRs = false; 823 824 if (Rt == 0) 825 return MCDisassembler::Fail; 826 else if (Rs == 0) 827 MI.setOpcode(Mips::BGTZC_MMR6); 828 else if (Rs == Rt) 829 MI.setOpcode(Mips::BLTZC_MMR6); 830 else { 831 MI.setOpcode(Mips::BLTC_MMR6); 832 HasRs = true; 833 } 834 835 if (HasRs) 836 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 837 Rs))); 838 839 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 840 Rt))); 841 842 MI.addOperand(MCOperand::createImm(Imm)); 843 844 return MCDisassembler::Success; 845 } 846 847 template <typename InsnType> 848 static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, 849 uint64_t Address, 850 const void *Decoder) { 851 // We have: 852 // 0b111101 ttttt sssss iiiiiiiiiiiiiiii 853 // Invalid if rt == 0 854 // BLEZC_MMR6 if rs == 0 && rt != 0 855 // BGEZC_MMR6 if rs == rt && rt != 0 856 // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 857 858 InsnType Rt = fieldFromInstruction(insn, 21, 5); 859 InsnType Rs = fieldFromInstruction(insn, 16, 5); 860 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 861 bool HasRs = false; 862 863 if (Rt == 0) 864 return MCDisassembler::Fail; 865 else if (Rs == 0) 866 MI.setOpcode(Mips::BLEZC_MMR6); 867 else if (Rs == Rt) 868 MI.setOpcode(Mips::BGEZC_MMR6); 869 else { 870 HasRs = true; 871 MI.setOpcode(Mips::BGEC_MMR6); 872 } 873 874 if (HasRs) 875 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 876 Rs))); 877 878 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 879 Rt))); 880 881 MI.addOperand(MCOperand::createImm(Imm)); 882 883 return MCDisassembler::Success; 884 } 885 886 template <typename InsnType> 887 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, 888 uint64_t Address, 889 const void *Decoder) { 890 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 891 // (otherwise we would have matched the BLEZL instruction from the earlier 892 // ISA's instead). 893 // 894 // We have: 895 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii 896 // Invalid if rs == 0 897 // BLEZC if rs == 0 && rt != 0 898 // BGEZC if rs == rt && rt != 0 899 // BGEC if rs != rt && rs != 0 && rt != 0 900 901 InsnType Rs = fieldFromInstruction(insn, 21, 5); 902 InsnType Rt = fieldFromInstruction(insn, 16, 5); 903 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 904 bool HasRs = false; 905 906 if (Rt == 0) 907 return MCDisassembler::Fail; 908 else if (Rs == 0) 909 MI.setOpcode(Mips::BLEZC); 910 else if (Rs == Rt) 911 MI.setOpcode(Mips::BGEZC); 912 else { 913 HasRs = true; 914 MI.setOpcode(Mips::BGEC); 915 } 916 917 if (HasRs) 918 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 919 Rs))); 920 921 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 922 Rt))); 923 924 MI.addOperand(MCOperand::createImm(Imm)); 925 926 return MCDisassembler::Success; 927 } 928 929 template <typename InsnType> 930 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, 931 uint64_t Address, 932 const void *Decoder) { 933 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 934 // (otherwise we would have matched the BGTZL instruction from the earlier 935 // ISA's instead). 936 // 937 // We have: 938 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii 939 // Invalid if rs == 0 940 // BGTZC if rs == 0 && rt != 0 941 // BLTZC if rs == rt && rt != 0 942 // BLTC if rs != rt && rs != 0 && rt != 0 943 944 bool HasRs = false; 945 946 InsnType Rs = fieldFromInstruction(insn, 21, 5); 947 InsnType Rt = fieldFromInstruction(insn, 16, 5); 948 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 949 950 if (Rt == 0) 951 return MCDisassembler::Fail; 952 else if (Rs == 0) 953 MI.setOpcode(Mips::BGTZC); 954 else if (Rs == Rt) 955 MI.setOpcode(Mips::BLTZC); 956 else { 957 MI.setOpcode(Mips::BLTC); 958 HasRs = true; 959 } 960 961 if (HasRs) 962 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 963 Rs))); 964 965 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 966 Rt))); 967 968 MI.addOperand(MCOperand::createImm(Imm)); 969 970 return MCDisassembler::Success; 971 } 972 973 template <typename InsnType> 974 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, 975 uint64_t Address, 976 const void *Decoder) { 977 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 978 // (otherwise we would have matched the BGTZ instruction from the earlier 979 // ISA's instead). 980 // 981 // We have: 982 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii 983 // BGTZ if rt == 0 984 // BGTZALC if rs == 0 && rt != 0 985 // BLTZALC if rs != 0 && rs == rt 986 // BLTUC if rs != 0 && rs != rt 987 988 InsnType Rs = fieldFromInstruction(insn, 21, 5); 989 InsnType Rt = fieldFromInstruction(insn, 16, 5); 990 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 991 bool HasRs = false; 992 bool HasRt = false; 993 994 if (Rt == 0) { 995 MI.setOpcode(Mips::BGTZ); 996 HasRs = true; 997 } else if (Rs == 0) { 998 MI.setOpcode(Mips::BGTZALC); 999 HasRt = true; 1000 } else if (Rs == Rt) { 1001 MI.setOpcode(Mips::BLTZALC); 1002 HasRs = true; 1003 } else { 1004 MI.setOpcode(Mips::BLTUC); 1005 HasRs = true; 1006 HasRt = true; 1007 } 1008 1009 if (HasRs) 1010 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1011 Rs))); 1012 1013 if (HasRt) 1014 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1015 Rt))); 1016 1017 MI.addOperand(MCOperand::createImm(Imm)); 1018 1019 return MCDisassembler::Success; 1020 } 1021 1022 template <typename InsnType> 1023 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, 1024 uint64_t Address, 1025 const void *Decoder) { 1026 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled 1027 // (otherwise we would have matched the BLEZL instruction from the earlier 1028 // ISA's instead). 1029 // 1030 // We have: 1031 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii 1032 // Invalid if rs == 0 1033 // BLEZALC if rs == 0 && rt != 0 1034 // BGEZALC if rs == rt && rt != 0 1035 // BGEUC if rs != rt && rs != 0 && rt != 0 1036 1037 InsnType Rs = fieldFromInstruction(insn, 21, 5); 1038 InsnType Rt = fieldFromInstruction(insn, 16, 5); 1039 int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 1040 bool HasRs = false; 1041 1042 if (Rt == 0) 1043 return MCDisassembler::Fail; 1044 else if (Rs == 0) 1045 MI.setOpcode(Mips::BLEZALC); 1046 else if (Rs == Rt) 1047 MI.setOpcode(Mips::BGEZALC); 1048 else { 1049 HasRs = true; 1050 MI.setOpcode(Mips::BGEUC); 1051 } 1052 1053 if (HasRs) 1054 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1055 Rs))); 1056 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1057 Rt))); 1058 1059 MI.addOperand(MCOperand::createImm(Imm)); 1060 1061 return MCDisassembler::Success; 1062 } 1063 1064 // Override the generated disassembler to produce DEXT all the time. This is 1065 // for feature / behaviour parity with binutils. 1066 template <typename InsnType> 1067 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address, 1068 const void *Decoder) { 1069 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1070 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1071 unsigned Size = 0; 1072 unsigned Pos = 0; 1073 1074 switch (MI.getOpcode()) { 1075 case Mips::DEXT: 1076 Pos = Lsb; 1077 Size = Msbd + 1; 1078 break; 1079 case Mips::DEXTM: 1080 Pos = Lsb; 1081 Size = Msbd + 1 + 32; 1082 break; 1083 case Mips::DEXTU: 1084 Pos = Lsb + 32; 1085 Size = Msbd + 1; 1086 break; 1087 default: 1088 llvm_unreachable("Unknown DEXT instruction!"); 1089 } 1090 1091 MI.setOpcode(Mips::DEXT); 1092 1093 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1094 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1095 1096 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1097 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1098 MI.addOperand(MCOperand::createImm(Pos)); 1099 MI.addOperand(MCOperand::createImm(Size)); 1100 1101 return MCDisassembler::Success; 1102 } 1103 1104 // Override the generated disassembler to produce DINS all the time. This is 1105 // for feature / behaviour parity with binutils. 1106 template <typename InsnType> 1107 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address, 1108 const void *Decoder) { 1109 unsigned Msbd = fieldFromInstruction(Insn, 11, 5); 1110 unsigned Lsb = fieldFromInstruction(Insn, 6, 5); 1111 unsigned Size = 0; 1112 unsigned Pos = 0; 1113 1114 switch (MI.getOpcode()) { 1115 case Mips::DINS: 1116 Pos = Lsb; 1117 Size = Msbd + 1 - Pos; 1118 break; 1119 case Mips::DINSM: 1120 Pos = Lsb; 1121 Size = Msbd + 33 - Pos; 1122 break; 1123 case Mips::DINSU: 1124 Pos = Lsb + 32; 1125 // mbsd = pos + size - 33 1126 // mbsd - pos + 33 = size 1127 Size = Msbd + 33 - Pos; 1128 break; 1129 default: 1130 llvm_unreachable("Unknown DINS instruction!"); 1131 } 1132 1133 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1134 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1135 1136 MI.setOpcode(Mips::DINS); 1137 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); 1138 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); 1139 MI.addOperand(MCOperand::createImm(Pos)); 1140 MI.addOperand(MCOperand::createImm(Size)); 1141 1142 return MCDisassembler::Success; 1143 } 1144 1145 // Auto-generated decoder wouldn't add the third operand for CRC32*. 1146 template <typename InsnType> 1147 static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address, 1148 const void *Decoder) { 1149 InsnType Rs = fieldFromInstruction(Insn, 21, 5); 1150 InsnType Rt = fieldFromInstruction(Insn, 16, 5); 1151 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1152 Rt))); 1153 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1154 Rs))); 1155 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 1156 Rt))); 1157 return MCDisassembler::Success; 1158 } 1159 1160 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted 1161 /// according to the given endianness. 1162 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, 1163 uint64_t &Size, uint32_t &Insn, 1164 bool IsBigEndian) { 1165 // We want to read exactly 2 Bytes of data. 1166 if (Bytes.size() < 2) { 1167 Size = 0; 1168 return MCDisassembler::Fail; 1169 } 1170 1171 if (IsBigEndian) { 1172 Insn = (Bytes[0] << 8) | Bytes[1]; 1173 } else { 1174 Insn = (Bytes[1] << 8) | Bytes[0]; 1175 } 1176 1177 return MCDisassembler::Success; 1178 } 1179 1180 /// Read four bytes from the ArrayRef and return 32 bit word sorted 1181 /// according to the given endianness. 1182 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 1183 uint64_t &Size, uint32_t &Insn, 1184 bool IsBigEndian, bool IsMicroMips) { 1185 // We want to read exactly 4 Bytes of data. 1186 if (Bytes.size() < 4) { 1187 Size = 0; 1188 return MCDisassembler::Fail; 1189 } 1190 1191 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) 1192 // always precede the low 16 bits in the instruction stream (that is, they 1193 // are placed at lower addresses in the instruction stream). 1194 // 1195 // microMIPS byte ordering: 1196 // Big-endian: 0 | 1 | 2 | 3 1197 // Little-endian: 1 | 0 | 3 | 2 1198 1199 if (IsBigEndian) { 1200 // Encoded as a big-endian 32-bit word in the stream. 1201 Insn = 1202 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 1203 } else { 1204 if (IsMicroMips) { 1205 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | 1206 (Bytes[1] << 24); 1207 } else { 1208 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 1209 (Bytes[3] << 24); 1210 } 1211 } 1212 1213 return MCDisassembler::Success; 1214 } 1215 1216 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 1217 ArrayRef<uint8_t> Bytes, 1218 uint64_t Address, 1219 raw_ostream &VStream, 1220 raw_ostream &CStream) const { 1221 uint32_t Insn; 1222 DecodeStatus Result; 1223 Size = 0; 1224 1225 if (IsMicroMips) { 1226 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian); 1227 if (Result == MCDisassembler::Fail) 1228 return MCDisassembler::Fail; 1229 1230 if (hasMips32r6()) { 1231 LLVM_DEBUG( 1232 dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); 1233 // Calling the auto-generated decoder function for microMIPS32R6 1234 // 16-bit instructions. 1235 Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, 1236 Address, this, STI); 1237 if (Result != MCDisassembler::Fail) { 1238 Size = 2; 1239 return Result; 1240 } 1241 } 1242 1243 LLVM_DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n"); 1244 // Calling the auto-generated decoder function for microMIPS 16-bit 1245 // instructions. 1246 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address, 1247 this, STI); 1248 if (Result != MCDisassembler::Fail) { 1249 Size = 2; 1250 return Result; 1251 } 1252 1253 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true); 1254 if (Result == MCDisassembler::Fail) 1255 return MCDisassembler::Fail; 1256 1257 if (hasMips32r6()) { 1258 LLVM_DEBUG( 1259 dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n"); 1260 // Calling the auto-generated decoder function. 1261 Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address, 1262 this, STI); 1263 if (Result != MCDisassembler::Fail) { 1264 Size = 4; 1265 return Result; 1266 } 1267 } 1268 1269 LLVM_DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n"); 1270 // Calling the auto-generated decoder function. 1271 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, 1272 this, STI); 1273 if (Result != MCDisassembler::Fail) { 1274 Size = 4; 1275 return Result; 1276 } 1277 1278 if (isFP64()) { 1279 LLVM_DEBUG(dbgs() << "Trying MicroMipsFP64 table (32-bit opcodes):\n"); 1280 Result = decodeInstruction(DecoderTableMicroMipsFP6432, Instr, Insn, 1281 Address, this, STI); 1282 if (Result != MCDisassembler::Fail) { 1283 Size = 4; 1284 return Result; 1285 } 1286 } 1287 1288 // This is an invalid instruction. Claim that the Size is 2 bytes. Since 1289 // microMIPS instructions have a minimum alignment of 2, the next 2 bytes 1290 // could form a valid instruction. The two bytes we rejected as an 1291 // instruction could have actually beeen an inline constant pool that is 1292 // unconditionally branched over. 1293 Size = 2; 1294 return MCDisassembler::Fail; 1295 } 1296 1297 // Attempt to read the instruction so that we can attempt to decode it. If 1298 // the buffer is not 4 bytes long, let the higher level logic figure out 1299 // what to do with a size of zero and MCDisassembler::Fail. 1300 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); 1301 if (Result == MCDisassembler::Fail) 1302 return MCDisassembler::Fail; 1303 1304 // The only instruction size for standard encoded MIPS. 1305 Size = 4; 1306 1307 if (hasCOP3()) { 1308 LLVM_DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); 1309 Result = 1310 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); 1311 if (Result != MCDisassembler::Fail) 1312 return Result; 1313 } 1314 1315 if (hasMips32r6() && isGP64()) { 1316 LLVM_DEBUG( 1317 dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); 1318 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, 1319 Address, this, STI); 1320 if (Result != MCDisassembler::Fail) 1321 return Result; 1322 } 1323 1324 if (hasMips32r6() && isPTR64()) { 1325 LLVM_DEBUG( 1326 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1327 Result = decodeInstruction(DecoderTableMips32r6_64r6_PTR6432, Instr, Insn, 1328 Address, this, STI); 1329 if (Result != MCDisassembler::Fail) 1330 return Result; 1331 } 1332 1333 if (hasMips32r6()) { 1334 LLVM_DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); 1335 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, 1336 Address, this, STI); 1337 if (Result != MCDisassembler::Fail) 1338 return Result; 1339 } 1340 1341 if (hasMips2() && isPTR64()) { 1342 LLVM_DEBUG( 1343 dbgs() << "Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n"); 1344 Result = decodeInstruction(DecoderTableMips32_64_PTR6432, Instr, Insn, 1345 Address, this, STI); 1346 if (Result != MCDisassembler::Fail) 1347 return Result; 1348 } 1349 1350 if (hasCnMips()) { 1351 LLVM_DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n"); 1352 Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn, 1353 Address, this, STI); 1354 if (Result != MCDisassembler::Fail) 1355 return Result; 1356 } 1357 1358 if (hasCnMipsP()) { 1359 LLVM_DEBUG(dbgs() << "Trying CnMipsP table (32-bit opcodes):\n"); 1360 Result = decodeInstruction(DecoderTableCnMipsP32, Instr, Insn, 1361 Address, this, STI); 1362 if (Result != MCDisassembler::Fail) 1363 return Result; 1364 } 1365 1366 if (isGP64()) { 1367 LLVM_DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n"); 1368 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn, 1369 Address, this, STI); 1370 if (Result != MCDisassembler::Fail) 1371 return Result; 1372 } 1373 1374 if (isFP64()) { 1375 LLVM_DEBUG( 1376 dbgs() << "Trying MipsFP64 (64 bit FPU) table (32-bit opcodes):\n"); 1377 Result = decodeInstruction(DecoderTableMipsFP6432, Instr, Insn, 1378 Address, this, STI); 1379 if (Result != MCDisassembler::Fail) 1380 return Result; 1381 } 1382 1383 LLVM_DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); 1384 // Calling the auto-generated decoder function. 1385 Result = 1386 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); 1387 if (Result != MCDisassembler::Fail) 1388 return Result; 1389 1390 return MCDisassembler::Fail; 1391 } 1392 1393 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 1394 unsigned RegNo, 1395 uint64_t Address, 1396 const void *Decoder) { 1397 return MCDisassembler::Fail; 1398 } 1399 1400 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, 1401 unsigned RegNo, 1402 uint64_t Address, 1403 const void *Decoder) { 1404 if (RegNo > 31) 1405 return MCDisassembler::Fail; 1406 1407 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); 1408 Inst.addOperand(MCOperand::createReg(Reg)); 1409 return MCDisassembler::Success; 1410 } 1411 1412 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, 1413 unsigned RegNo, 1414 uint64_t Address, 1415 const void *Decoder) { 1416 if (RegNo > 7) 1417 return MCDisassembler::Fail; 1418 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); 1419 Inst.addOperand(MCOperand::createReg(Reg)); 1420 return MCDisassembler::Success; 1421 } 1422 1423 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, 1424 unsigned RegNo, 1425 uint64_t Address, 1426 const void *Decoder) { 1427 if (RegNo > 7) 1428 return MCDisassembler::Fail; 1429 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); 1430 Inst.addOperand(MCOperand::createReg(Reg)); 1431 return MCDisassembler::Success; 1432 } 1433 1434 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, 1435 unsigned RegNo, 1436 uint64_t Address, 1437 const void *Decoder) { 1438 if (RegNo > 7) 1439 return MCDisassembler::Fail; 1440 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); 1441 Inst.addOperand(MCOperand::createReg(Reg)); 1442 return MCDisassembler::Success; 1443 } 1444 1445 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, 1446 unsigned RegNo, 1447 uint64_t Address, 1448 const void *Decoder) { 1449 if (RegNo > 31) 1450 return MCDisassembler::Fail; 1451 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); 1452 Inst.addOperand(MCOperand::createReg(Reg)); 1453 return MCDisassembler::Success; 1454 } 1455 1456 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, 1457 unsigned RegNo, 1458 uint64_t Address, 1459 const void *Decoder) { 1460 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) 1461 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); 1462 1463 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1464 } 1465 1466 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, 1467 unsigned RegNo, 1468 uint64_t Address, 1469 const void *Decoder) { 1470 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); 1471 } 1472 1473 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 1474 unsigned RegNo, 1475 uint64_t Address, 1476 const void *Decoder) { 1477 if (RegNo > 31) 1478 return MCDisassembler::Fail; 1479 1480 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); 1481 Inst.addOperand(MCOperand::createReg(Reg)); 1482 return MCDisassembler::Success; 1483 } 1484 1485 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 1486 unsigned RegNo, 1487 uint64_t Address, 1488 const void *Decoder) { 1489 if (RegNo > 31) 1490 return MCDisassembler::Fail; 1491 1492 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); 1493 Inst.addOperand(MCOperand::createReg(Reg)); 1494 return MCDisassembler::Success; 1495 } 1496 1497 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 1498 unsigned RegNo, 1499 uint64_t Address, 1500 const void *Decoder) { 1501 if (RegNo > 31) 1502 return MCDisassembler::Fail; 1503 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); 1504 Inst.addOperand(MCOperand::createReg(Reg)); 1505 return MCDisassembler::Success; 1506 } 1507 1508 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, 1509 unsigned RegNo, 1510 uint64_t Address, 1511 const void *Decoder) { 1512 if (RegNo > 7) 1513 return MCDisassembler::Fail; 1514 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); 1515 Inst.addOperand(MCOperand::createReg(Reg)); 1516 return MCDisassembler::Success; 1517 } 1518 1519 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, 1520 uint64_t Address, 1521 const void *Decoder) { 1522 if (RegNo > 31) 1523 return MCDisassembler::Fail; 1524 1525 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); 1526 Inst.addOperand(MCOperand::createReg(Reg)); 1527 return MCDisassembler::Success; 1528 } 1529 1530 static DecodeStatus DecodeMem(MCInst &Inst, 1531 unsigned Insn, 1532 uint64_t Address, 1533 const void *Decoder) { 1534 int Offset = SignExtend32<16>(Insn & 0xffff); 1535 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1536 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1537 1538 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1539 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1540 1541 if (Inst.getOpcode() == Mips::SC || 1542 Inst.getOpcode() == Mips::SCD) 1543 Inst.addOperand(MCOperand::createReg(Reg)); 1544 1545 Inst.addOperand(MCOperand::createReg(Reg)); 1546 Inst.addOperand(MCOperand::createReg(Base)); 1547 Inst.addOperand(MCOperand::createImm(Offset)); 1548 1549 return MCDisassembler::Success; 1550 } 1551 1552 static DecodeStatus DecodeMemEVA(MCInst &Inst, 1553 unsigned Insn, 1554 uint64_t Address, 1555 const void *Decoder) { 1556 int Offset = SignExtend32<9>(Insn >> 7); 1557 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1558 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1559 1560 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1561 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1562 1563 if (Inst.getOpcode() == Mips::SCE) 1564 Inst.addOperand(MCOperand::createReg(Reg)); 1565 1566 Inst.addOperand(MCOperand::createReg(Reg)); 1567 Inst.addOperand(MCOperand::createReg(Base)); 1568 Inst.addOperand(MCOperand::createImm(Offset)); 1569 1570 return MCDisassembler::Success; 1571 } 1572 1573 static DecodeStatus DecodeLoadByte15(MCInst &Inst, 1574 unsigned Insn, 1575 uint64_t Address, 1576 const void *Decoder) { 1577 int Offset = SignExtend32<16>(Insn & 0xffff); 1578 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1579 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1580 1581 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1582 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1583 1584 Inst.addOperand(MCOperand::createReg(Reg)); 1585 Inst.addOperand(MCOperand::createReg(Base)); 1586 Inst.addOperand(MCOperand::createImm(Offset)); 1587 1588 return MCDisassembler::Success; 1589 } 1590 1591 static DecodeStatus DecodeCacheOp(MCInst &Inst, 1592 unsigned Insn, 1593 uint64_t Address, 1594 const void *Decoder) { 1595 int Offset = SignExtend32<16>(Insn & 0xffff); 1596 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1597 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1598 1599 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1600 1601 Inst.addOperand(MCOperand::createReg(Base)); 1602 Inst.addOperand(MCOperand::createImm(Offset)); 1603 Inst.addOperand(MCOperand::createImm(Hint)); 1604 1605 return MCDisassembler::Success; 1606 } 1607 1608 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, 1609 unsigned Insn, 1610 uint64_t Address, 1611 const void *Decoder) { 1612 int Offset = SignExtend32<12>(Insn & 0xfff); 1613 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1614 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1615 1616 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1617 1618 Inst.addOperand(MCOperand::createReg(Base)); 1619 Inst.addOperand(MCOperand::createImm(Offset)); 1620 Inst.addOperand(MCOperand::createImm(Hint)); 1621 1622 return MCDisassembler::Success; 1623 } 1624 1625 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, 1626 unsigned Insn, 1627 uint64_t Address, 1628 const void *Decoder) { 1629 int Offset = SignExtend32<9>(Insn & 0x1ff); 1630 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1631 unsigned Hint = fieldFromInstruction(Insn, 21, 5); 1632 1633 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1634 1635 Inst.addOperand(MCOperand::createReg(Base)); 1636 Inst.addOperand(MCOperand::createImm(Offset)); 1637 Inst.addOperand(MCOperand::createImm(Hint)); 1638 1639 return MCDisassembler::Success; 1640 } 1641 1642 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, 1643 unsigned Insn, 1644 uint64_t Address, 1645 const void *Decoder) { 1646 int Offset = SignExtend32<9>(Insn >> 7); 1647 unsigned Hint = fieldFromInstruction(Insn, 16, 5); 1648 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1649 1650 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1651 1652 Inst.addOperand(MCOperand::createReg(Base)); 1653 Inst.addOperand(MCOperand::createImm(Offset)); 1654 Inst.addOperand(MCOperand::createImm(Hint)); 1655 1656 return MCDisassembler::Success; 1657 } 1658 1659 static DecodeStatus DecodeSyncI(MCInst &Inst, 1660 unsigned Insn, 1661 uint64_t Address, 1662 const void *Decoder) { 1663 int Offset = SignExtend32<16>(Insn & 0xffff); 1664 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1665 1666 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1667 1668 Inst.addOperand(MCOperand::createReg(Base)); 1669 Inst.addOperand(MCOperand::createImm(Offset)); 1670 1671 return MCDisassembler::Success; 1672 } 1673 1674 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn, 1675 uint64_t Address, const void *Decoder) { 1676 int Offset = SignExtend32<16>(Insn & 0xffff); 1677 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1678 1679 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1680 1681 Inst.addOperand(MCOperand::createReg(Base)); 1682 Inst.addOperand(MCOperand::createImm(Offset)); 1683 1684 return MCDisassembler::Success; 1685 } 1686 1687 static DecodeStatus DecodeSynciR6(MCInst &Inst, 1688 unsigned Insn, 1689 uint64_t Address, 1690 const void *Decoder) { 1691 int Immediate = SignExtend32<16>(Insn & 0xffff); 1692 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1693 1694 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1695 1696 Inst.addOperand(MCOperand::createReg(Base)); 1697 Inst.addOperand(MCOperand::createImm(Immediate)); 1698 1699 return MCDisassembler::Success; 1700 } 1701 1702 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, 1703 uint64_t Address, const void *Decoder) { 1704 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); 1705 unsigned Reg = fieldFromInstruction(Insn, 6, 5); 1706 unsigned Base = fieldFromInstruction(Insn, 11, 5); 1707 1708 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); 1709 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1710 1711 Inst.addOperand(MCOperand::createReg(Reg)); 1712 Inst.addOperand(MCOperand::createReg(Base)); 1713 1714 // The immediate field of an LD/ST instruction is scaled which means it must 1715 // be multiplied (when decoding) by the size (in bytes) of the instructions' 1716 // data format. 1717 // .b - 1 byte 1718 // .h - 2 bytes 1719 // .w - 4 bytes 1720 // .d - 8 bytes 1721 switch(Inst.getOpcode()) 1722 { 1723 default: 1724 assert(false && "Unexpected instruction"); 1725 return MCDisassembler::Fail; 1726 break; 1727 case Mips::LD_B: 1728 case Mips::ST_B: 1729 Inst.addOperand(MCOperand::createImm(Offset)); 1730 break; 1731 case Mips::LD_H: 1732 case Mips::ST_H: 1733 Inst.addOperand(MCOperand::createImm(Offset * 2)); 1734 break; 1735 case Mips::LD_W: 1736 case Mips::ST_W: 1737 Inst.addOperand(MCOperand::createImm(Offset * 4)); 1738 break; 1739 case Mips::LD_D: 1740 case Mips::ST_D: 1741 Inst.addOperand(MCOperand::createImm(Offset * 8)); 1742 break; 1743 } 1744 1745 return MCDisassembler::Success; 1746 } 1747 1748 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, 1749 unsigned Insn, 1750 uint64_t Address, 1751 const void *Decoder) { 1752 unsigned Offset = Insn & 0xf; 1753 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1754 unsigned Base = fieldFromInstruction(Insn, 4, 3); 1755 1756 switch (Inst.getOpcode()) { 1757 case Mips::LBU16_MM: 1758 case Mips::LHU16_MM: 1759 case Mips::LW16_MM: 1760 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) 1761 == MCDisassembler::Fail) 1762 return MCDisassembler::Fail; 1763 break; 1764 case Mips::SB16_MM: 1765 case Mips::SB16_MMR6: 1766 case Mips::SH16_MM: 1767 case Mips::SH16_MMR6: 1768 case Mips::SW16_MM: 1769 case Mips::SW16_MMR6: 1770 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) 1771 == MCDisassembler::Fail) 1772 return MCDisassembler::Fail; 1773 break; 1774 } 1775 1776 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) 1777 == MCDisassembler::Fail) 1778 return MCDisassembler::Fail; 1779 1780 switch (Inst.getOpcode()) { 1781 case Mips::LBU16_MM: 1782 if (Offset == 0xf) 1783 Inst.addOperand(MCOperand::createImm(-1)); 1784 else 1785 Inst.addOperand(MCOperand::createImm(Offset)); 1786 break; 1787 case Mips::SB16_MM: 1788 case Mips::SB16_MMR6: 1789 Inst.addOperand(MCOperand::createImm(Offset)); 1790 break; 1791 case Mips::LHU16_MM: 1792 case Mips::SH16_MM: 1793 case Mips::SH16_MMR6: 1794 Inst.addOperand(MCOperand::createImm(Offset << 1)); 1795 break; 1796 case Mips::LW16_MM: 1797 case Mips::SW16_MM: 1798 case Mips::SW16_MMR6: 1799 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1800 break; 1801 } 1802 1803 return MCDisassembler::Success; 1804 } 1805 1806 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, 1807 unsigned Insn, 1808 uint64_t Address, 1809 const void *Decoder) { 1810 unsigned Offset = Insn & 0x1F; 1811 unsigned Reg = fieldFromInstruction(Insn, 5, 5); 1812 1813 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1814 1815 Inst.addOperand(MCOperand::createReg(Reg)); 1816 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1817 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1818 1819 return MCDisassembler::Success; 1820 } 1821 1822 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, 1823 unsigned Insn, 1824 uint64_t Address, 1825 const void *Decoder) { 1826 unsigned Offset = Insn & 0x7F; 1827 unsigned Reg = fieldFromInstruction(Insn, 7, 3); 1828 1829 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1830 1831 Inst.addOperand(MCOperand::createReg(Reg)); 1832 Inst.addOperand(MCOperand::createReg(Mips::GP)); 1833 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1834 1835 return MCDisassembler::Success; 1836 } 1837 1838 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, 1839 unsigned Insn, 1840 uint64_t Address, 1841 const void *Decoder) { 1842 int Offset; 1843 switch (Inst.getOpcode()) { 1844 case Mips::LWM16_MMR6: 1845 case Mips::SWM16_MMR6: 1846 Offset = fieldFromInstruction(Insn, 4, 4); 1847 break; 1848 default: 1849 Offset = SignExtend32<4>(Insn & 0xf); 1850 break; 1851 } 1852 1853 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) 1854 == MCDisassembler::Fail) 1855 return MCDisassembler::Fail; 1856 1857 Inst.addOperand(MCOperand::createReg(Mips::SP)); 1858 Inst.addOperand(MCOperand::createImm(Offset << 2)); 1859 1860 return MCDisassembler::Success; 1861 } 1862 1863 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, 1864 unsigned Insn, 1865 uint64_t Address, 1866 const void *Decoder) { 1867 int Offset = SignExtend32<9>(Insn & 0x1ff); 1868 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1869 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1870 1871 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1872 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1873 1874 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6) 1875 Inst.addOperand(MCOperand::createReg(Reg)); 1876 1877 Inst.addOperand(MCOperand::createReg(Reg)); 1878 Inst.addOperand(MCOperand::createReg(Base)); 1879 Inst.addOperand(MCOperand::createImm(Offset)); 1880 1881 return MCDisassembler::Success; 1882 } 1883 1884 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, 1885 unsigned Insn, 1886 uint64_t Address, 1887 const void *Decoder) { 1888 int Offset = SignExtend32<12>(Insn & 0x0fff); 1889 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1890 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1891 1892 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1893 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1894 1895 switch (Inst.getOpcode()) { 1896 case Mips::SWM32_MM: 1897 case Mips::LWM32_MM: 1898 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) 1899 == MCDisassembler::Fail) 1900 return MCDisassembler::Fail; 1901 Inst.addOperand(MCOperand::createReg(Base)); 1902 Inst.addOperand(MCOperand::createImm(Offset)); 1903 break; 1904 case Mips::SC_MM: 1905 Inst.addOperand(MCOperand::createReg(Reg)); 1906 LLVM_FALLTHROUGH; 1907 default: 1908 Inst.addOperand(MCOperand::createReg(Reg)); 1909 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) 1910 Inst.addOperand(MCOperand::createReg(Reg+1)); 1911 1912 Inst.addOperand(MCOperand::createReg(Base)); 1913 Inst.addOperand(MCOperand::createImm(Offset)); 1914 } 1915 1916 return MCDisassembler::Success; 1917 } 1918 1919 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, 1920 unsigned Insn, 1921 uint64_t Address, 1922 const void *Decoder) { 1923 int Offset = SignExtend32<16>(Insn & 0xffff); 1924 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1925 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1926 1927 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); 1928 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1929 1930 Inst.addOperand(MCOperand::createReg(Reg)); 1931 Inst.addOperand(MCOperand::createReg(Base)); 1932 Inst.addOperand(MCOperand::createImm(Offset)); 1933 1934 return MCDisassembler::Success; 1935 } 1936 1937 static DecodeStatus DecodeFMem(MCInst &Inst, 1938 unsigned Insn, 1939 uint64_t Address, 1940 const void *Decoder) { 1941 int Offset = SignExtend32<16>(Insn & 0xffff); 1942 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1943 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1944 1945 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1946 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1947 1948 Inst.addOperand(MCOperand::createReg(Reg)); 1949 Inst.addOperand(MCOperand::createReg(Base)); 1950 Inst.addOperand(MCOperand::createImm(Offset)); 1951 1952 return MCDisassembler::Success; 1953 } 1954 1955 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, 1956 uint64_t Address, const void *Decoder) { 1957 // This function is the same as DecodeFMem but with the Reg and Base fields 1958 // swapped according to microMIPS spec. 1959 int Offset = SignExtend32<16>(Insn & 0xffff); 1960 unsigned Base = fieldFromInstruction(Insn, 16, 5); 1961 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 1962 1963 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); 1964 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1965 1966 Inst.addOperand(MCOperand::createReg(Reg)); 1967 Inst.addOperand(MCOperand::createReg(Base)); 1968 Inst.addOperand(MCOperand::createImm(Offset)); 1969 1970 return MCDisassembler::Success; 1971 } 1972 1973 static DecodeStatus DecodeFMem2(MCInst &Inst, 1974 unsigned Insn, 1975 uint64_t Address, 1976 const void *Decoder) { 1977 int Offset = SignExtend32<16>(Insn & 0xffff); 1978 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1979 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1980 1981 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 1982 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 1983 1984 Inst.addOperand(MCOperand::createReg(Reg)); 1985 Inst.addOperand(MCOperand::createReg(Base)); 1986 Inst.addOperand(MCOperand::createImm(Offset)); 1987 1988 return MCDisassembler::Success; 1989 } 1990 1991 static DecodeStatus DecodeFMem3(MCInst &Inst, 1992 unsigned Insn, 1993 uint64_t Address, 1994 const void *Decoder) { 1995 int Offset = SignExtend32<16>(Insn & 0xffff); 1996 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 1997 unsigned Base = fieldFromInstruction(Insn, 21, 5); 1998 1999 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); 2000 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2001 2002 Inst.addOperand(MCOperand::createReg(Reg)); 2003 Inst.addOperand(MCOperand::createReg(Base)); 2004 Inst.addOperand(MCOperand::createImm(Offset)); 2005 2006 return MCDisassembler::Success; 2007 } 2008 2009 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, 2010 unsigned Insn, 2011 uint64_t Address, 2012 const void *Decoder) { 2013 int Offset = SignExtend32<11>(Insn & 0x07ff); 2014 unsigned Reg = fieldFromInstruction(Insn, 16, 5); 2015 unsigned Base = fieldFromInstruction(Insn, 11, 5); 2016 2017 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2018 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2019 2020 Inst.addOperand(MCOperand::createReg(Reg)); 2021 Inst.addOperand(MCOperand::createReg(Base)); 2022 Inst.addOperand(MCOperand::createImm(Offset)); 2023 2024 return MCDisassembler::Success; 2025 } 2026 2027 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, 2028 uint64_t Address, const void *Decoder) { 2029 int Offset = SignExtend32<11>(Insn & 0x07ff); 2030 unsigned Reg = fieldFromInstruction(Insn, 21, 5); 2031 unsigned Base = fieldFromInstruction(Insn, 16, 5); 2032 2033 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); 2034 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2035 2036 Inst.addOperand(MCOperand::createReg(Reg)); 2037 Inst.addOperand(MCOperand::createReg(Base)); 2038 Inst.addOperand(MCOperand::createImm(Offset)); 2039 2040 return MCDisassembler::Success; 2041 } 2042 2043 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, 2044 unsigned Insn, 2045 uint64_t Address, 2046 const void *Decoder) { 2047 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff); 2048 unsigned Rt = fieldFromInstruction(Insn, 16, 5); 2049 unsigned Base = fieldFromInstruction(Insn, 21, 5); 2050 2051 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); 2052 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); 2053 2054 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){ 2055 Inst.addOperand(MCOperand::createReg(Rt)); 2056 } 2057 2058 Inst.addOperand(MCOperand::createReg(Rt)); 2059 Inst.addOperand(MCOperand::createReg(Base)); 2060 Inst.addOperand(MCOperand::createImm(Offset)); 2061 2062 return MCDisassembler::Success; 2063 } 2064 2065 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 2066 unsigned RegNo, 2067 uint64_t Address, 2068 const void *Decoder) { 2069 // Currently only hardware register 29 is supported. 2070 if (RegNo != 29) 2071 return MCDisassembler::Fail; 2072 Inst.addOperand(MCOperand::createReg(Mips::HWR29)); 2073 return MCDisassembler::Success; 2074 } 2075 2076 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 2077 unsigned RegNo, 2078 uint64_t Address, 2079 const void *Decoder) { 2080 if (RegNo > 30 || RegNo %2) 2081 return MCDisassembler::Fail; 2082 2083 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); 2084 Inst.addOperand(MCOperand::createReg(Reg)); 2085 return MCDisassembler::Success; 2086 } 2087 2088 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, 2089 unsigned RegNo, 2090 uint64_t Address, 2091 const void *Decoder) { 2092 if (RegNo >= 4) 2093 return MCDisassembler::Fail; 2094 2095 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); 2096 Inst.addOperand(MCOperand::createReg(Reg)); 2097 return MCDisassembler::Success; 2098 } 2099 2100 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, 2101 unsigned RegNo, 2102 uint64_t Address, 2103 const void *Decoder) { 2104 if (RegNo >= 4) 2105 return MCDisassembler::Fail; 2106 2107 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); 2108 Inst.addOperand(MCOperand::createReg(Reg)); 2109 return MCDisassembler::Success; 2110 } 2111 2112 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, 2113 unsigned RegNo, 2114 uint64_t Address, 2115 const void *Decoder) { 2116 if (RegNo >= 4) 2117 return MCDisassembler::Fail; 2118 2119 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); 2120 Inst.addOperand(MCOperand::createReg(Reg)); 2121 return MCDisassembler::Success; 2122 } 2123 2124 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, 2125 unsigned RegNo, 2126 uint64_t Address, 2127 const void *Decoder) { 2128 if (RegNo > 31) 2129 return MCDisassembler::Fail; 2130 2131 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); 2132 Inst.addOperand(MCOperand::createReg(Reg)); 2133 return MCDisassembler::Success; 2134 } 2135 2136 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, 2137 unsigned RegNo, 2138 uint64_t Address, 2139 const void *Decoder) { 2140 if (RegNo > 31) 2141 return MCDisassembler::Fail; 2142 2143 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); 2144 Inst.addOperand(MCOperand::createReg(Reg)); 2145 return MCDisassembler::Success; 2146 } 2147 2148 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, 2149 unsigned RegNo, 2150 uint64_t Address, 2151 const void *Decoder) { 2152 if (RegNo > 31) 2153 return MCDisassembler::Fail; 2154 2155 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); 2156 Inst.addOperand(MCOperand::createReg(Reg)); 2157 return MCDisassembler::Success; 2158 } 2159 2160 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, 2161 unsigned RegNo, 2162 uint64_t Address, 2163 const void *Decoder) { 2164 if (RegNo > 31) 2165 return MCDisassembler::Fail; 2166 2167 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); 2168 Inst.addOperand(MCOperand::createReg(Reg)); 2169 return MCDisassembler::Success; 2170 } 2171 2172 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, 2173 unsigned RegNo, 2174 uint64_t Address, 2175 const void *Decoder) { 2176 if (RegNo > 7) 2177 return MCDisassembler::Fail; 2178 2179 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); 2180 Inst.addOperand(MCOperand::createReg(Reg)); 2181 return MCDisassembler::Success; 2182 } 2183 2184 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, 2185 unsigned RegNo, 2186 uint64_t Address, 2187 const void *Decoder) { 2188 if (RegNo > 31) 2189 return MCDisassembler::Fail; 2190 2191 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); 2192 Inst.addOperand(MCOperand::createReg(Reg)); 2193 return MCDisassembler::Success; 2194 } 2195 2196 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, 2197 unsigned RegNo, 2198 uint64_t Address, 2199 const void *Decoder) { 2200 if (RegNo > 31) 2201 return MCDisassembler::Fail; 2202 2203 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); 2204 Inst.addOperand(MCOperand::createReg(Reg)); 2205 return MCDisassembler::Success; 2206 } 2207 2208 static DecodeStatus DecodeBranchTarget(MCInst &Inst, 2209 unsigned Offset, 2210 uint64_t Address, 2211 const void *Decoder) { 2212 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; 2213 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2214 return MCDisassembler::Success; 2215 } 2216 2217 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, 2218 unsigned Offset, 2219 uint64_t Address, 2220 const void *Decoder) { 2221 int32_t BranchOffset = (SignExtend32<16>(Offset) * 2); 2222 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2223 return MCDisassembler::Success; 2224 } 2225 2226 static DecodeStatus DecodeJumpTarget(MCInst &Inst, 2227 unsigned Insn, 2228 uint64_t Address, 2229 const void *Decoder) { 2230 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2231 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2232 return MCDisassembler::Success; 2233 } 2234 2235 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, 2236 unsigned Offset, 2237 uint64_t Address, 2238 const void *Decoder) { 2239 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2240 2241 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2242 return MCDisassembler::Success; 2243 } 2244 2245 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, 2246 unsigned Offset, 2247 uint64_t Address, 2248 const void *Decoder) { 2249 int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; 2250 2251 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2252 return MCDisassembler::Success; 2253 } 2254 2255 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, 2256 unsigned Offset, 2257 uint64_t Address, 2258 const void *Decoder) { 2259 int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4; 2260 2261 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2262 return MCDisassembler::Success; 2263 } 2264 2265 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, 2266 unsigned Offset, 2267 uint64_t Address, 2268 const void *Decoder) { 2269 int32_t BranchOffset = SignExtend32<8>(Offset << 1); 2270 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2271 return MCDisassembler::Success; 2272 } 2273 2274 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, 2275 unsigned Offset, 2276 uint64_t Address, 2277 const void *Decoder) { 2278 int32_t BranchOffset = SignExtend32<11>(Offset << 1); 2279 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2280 return MCDisassembler::Success; 2281 } 2282 2283 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, 2284 unsigned Offset, 2285 uint64_t Address, 2286 const void *Decoder) { 2287 int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; 2288 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2289 return MCDisassembler::Success; 2290 } 2291 2292 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, 2293 unsigned Offset, 2294 uint64_t Address, 2295 const void *Decoder) { 2296 int32_t BranchOffset = SignExtend32<27>(Offset << 1); 2297 2298 Inst.addOperand(MCOperand::createImm(BranchOffset)); 2299 return MCDisassembler::Success; 2300 } 2301 2302 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, 2303 unsigned Insn, 2304 uint64_t Address, 2305 const void *Decoder) { 2306 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; 2307 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2308 return MCDisassembler::Success; 2309 } 2310 2311 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, 2312 unsigned Insn, 2313 uint64_t Address, 2314 const void *Decoder) { 2315 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; 2316 Inst.addOperand(MCOperand::createImm(JumpOffset)); 2317 return MCDisassembler::Success; 2318 } 2319 2320 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, 2321 unsigned Value, 2322 uint64_t Address, 2323 const void *Decoder) { 2324 if (Value == 0) 2325 Inst.addOperand(MCOperand::createImm(1)); 2326 else if (Value == 0x7) 2327 Inst.addOperand(MCOperand::createImm(-1)); 2328 else 2329 Inst.addOperand(MCOperand::createImm(Value << 2)); 2330 return MCDisassembler::Success; 2331 } 2332 2333 static DecodeStatus DecodeLi16Imm(MCInst &Inst, 2334 unsigned Value, 2335 uint64_t Address, 2336 const void *Decoder) { 2337 if (Value == 0x7F) 2338 Inst.addOperand(MCOperand::createImm(-1)); 2339 else 2340 Inst.addOperand(MCOperand::createImm(Value)); 2341 return MCDisassembler::Success; 2342 } 2343 2344 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, 2345 unsigned Value, 2346 uint64_t Address, 2347 const void *Decoder) { 2348 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value)); 2349 return MCDisassembler::Success; 2350 } 2351 2352 template <unsigned Bits, int Offset, int Scale> 2353 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2354 uint64_t Address, 2355 const void *Decoder) { 2356 Value &= ((1 << Bits) - 1); 2357 Value *= Scale; 2358 Inst.addOperand(MCOperand::createImm(Value + Offset)); 2359 return MCDisassembler::Success; 2360 } 2361 2362 template <unsigned Bits, int Offset, int ScaleBy> 2363 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, 2364 uint64_t Address, 2365 const void *Decoder) { 2366 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy; 2367 Inst.addOperand(MCOperand::createImm(Imm + Offset)); 2368 return MCDisassembler::Success; 2369 } 2370 2371 static DecodeStatus DecodeInsSize(MCInst &Inst, 2372 unsigned Insn, 2373 uint64_t Address, 2374 const void *Decoder) { 2375 // First we need to grab the pos(lsb) from MCInst. 2376 // This function only handles the 32 bit variants of ins, as dins 2377 // variants are handled differently. 2378 int Pos = Inst.getOperand(2).getImm(); 2379 int Size = (int) Insn - Pos + 1; 2380 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size))); 2381 return MCDisassembler::Success; 2382 } 2383 2384 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, 2385 uint64_t Address, const void *Decoder) { 2386 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4)); 2387 return MCDisassembler::Success; 2388 } 2389 2390 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, 2391 uint64_t Address, const void *Decoder) { 2392 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8)); 2393 return MCDisassembler::Success; 2394 } 2395 2396 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, 2397 uint64_t Address, const void *Decoder) { 2398 int32_t DecodedValue; 2399 switch (Insn) { 2400 case 0: DecodedValue = 256; break; 2401 case 1: DecodedValue = 257; break; 2402 case 510: DecodedValue = -258; break; 2403 case 511: DecodedValue = -257; break; 2404 default: DecodedValue = SignExtend32<9>(Insn); break; 2405 } 2406 Inst.addOperand(MCOperand::createImm(DecodedValue * 4)); 2407 return MCDisassembler::Success; 2408 } 2409 2410 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, 2411 uint64_t Address, const void *Decoder) { 2412 // Insn must be >= 0, since it is unsigned that condition is always true. 2413 assert(Insn < 16); 2414 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 2415 255, 32768, 65535}; 2416 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn])); 2417 return MCDisassembler::Success; 2418 } 2419 2420 static DecodeStatus DecodeRegListOperand(MCInst &Inst, 2421 unsigned Insn, 2422 uint64_t Address, 2423 const void *Decoder) { 2424 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2425 Mips::S6, Mips::S7, Mips::FP}; 2426 unsigned RegNum; 2427 2428 unsigned RegLst = fieldFromInstruction(Insn, 21, 5); 2429 2430 // Empty register lists are not allowed. 2431 if (RegLst == 0) 2432 return MCDisassembler::Fail; 2433 2434 RegNum = RegLst & 0xf; 2435 2436 // RegLst values 10-15, and 26-31 are reserved. 2437 if (RegNum > 9) 2438 return MCDisassembler::Fail; 2439 2440 for (unsigned i = 0; i < RegNum; i++) 2441 Inst.addOperand(MCOperand::createReg(Regs[i])); 2442 2443 if (RegLst & 0x10) 2444 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2445 2446 return MCDisassembler::Success; 2447 } 2448 2449 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, 2450 uint64_t Address, 2451 const void *Decoder) { 2452 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; 2453 unsigned RegLst; 2454 switch(Inst.getOpcode()) { 2455 default: 2456 RegLst = fieldFromInstruction(Insn, 4, 2); 2457 break; 2458 case Mips::LWM16_MMR6: 2459 case Mips::SWM16_MMR6: 2460 RegLst = fieldFromInstruction(Insn, 8, 2); 2461 break; 2462 } 2463 unsigned RegNum = RegLst & 0x3; 2464 2465 for (unsigned i = 0; i <= RegNum; i++) 2466 Inst.addOperand(MCOperand::createReg(Regs[i])); 2467 2468 Inst.addOperand(MCOperand::createReg(Mips::RA)); 2469 2470 return MCDisassembler::Success; 2471 } 2472 2473 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn, 2474 uint64_t Address, 2475 const void *Decoder) { 2476 unsigned RegPair = fieldFromInstruction(Insn, 7, 3); 2477 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == 2478 MCDisassembler::Fail) 2479 return MCDisassembler::Fail; 2480 2481 unsigned RegRs; 2482 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6()) 2483 RegRs = fieldFromInstruction(Insn, 0, 2) | 2484 (fieldFromInstruction(Insn, 3, 1) << 2); 2485 else 2486 RegRs = fieldFromInstruction(Insn, 1, 3); 2487 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == 2488 MCDisassembler::Fail) 2489 return MCDisassembler::Fail; 2490 2491 unsigned RegRt = fieldFromInstruction(Insn, 4, 3); 2492 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == 2493 MCDisassembler::Fail) 2494 return MCDisassembler::Fail; 2495 2496 return MCDisassembler::Success; 2497 } 2498 2499 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair, 2500 uint64_t Address, const void *Decoder) { 2501 switch (RegPair) { 2502 default: 2503 return MCDisassembler::Fail; 2504 case 0: 2505 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2506 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2507 break; 2508 case 1: 2509 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2510 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2511 break; 2512 case 2: 2513 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2514 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2515 break; 2516 case 3: 2517 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2518 Inst.addOperand(MCOperand::createReg(Mips::S5)); 2519 break; 2520 case 4: 2521 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2522 Inst.addOperand(MCOperand::createReg(Mips::S6)); 2523 break; 2524 case 5: 2525 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2526 Inst.addOperand(MCOperand::createReg(Mips::A1)); 2527 break; 2528 case 6: 2529 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2530 Inst.addOperand(MCOperand::createReg(Mips::A2)); 2531 break; 2532 case 7: 2533 Inst.addOperand(MCOperand::createReg(Mips::A0)); 2534 Inst.addOperand(MCOperand::createReg(Mips::A3)); 2535 break; 2536 } 2537 2538 return MCDisassembler::Success; 2539 } 2540 2541 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, 2542 uint64_t Address, const void *Decoder) { 2543 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2))); 2544 return MCDisassembler::Success; 2545 } 2546 2547 template <typename InsnType> 2548 static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, 2549 uint64_t Address, 2550 const void *Decoder) { 2551 // We have: 2552 // 0b000111 ttttt sssss iiiiiiiiiiiiiiii 2553 // Invalid if rt == 0 2554 // BGTZALC_MMR6 if rs == 0 && rt != 0 2555 // BLTZALC_MMR6 if rs != 0 && rs == rt 2556 // BLTUC_MMR6 if rs != 0 && rs != rt 2557 2558 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2559 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2560 InsnType Imm = 0; 2561 bool HasRs = false; 2562 bool HasRt = false; 2563 2564 if (Rt == 0) 2565 return MCDisassembler::Fail; 2566 else if (Rs == 0) { 2567 MI.setOpcode(Mips::BGTZALC_MMR6); 2568 HasRt = true; 2569 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2570 } 2571 else if (Rs == Rt) { 2572 MI.setOpcode(Mips::BLTZALC_MMR6); 2573 HasRs = true; 2574 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2575 } 2576 else { 2577 MI.setOpcode(Mips::BLTUC_MMR6); 2578 HasRs = true; 2579 HasRt = true; 2580 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2581 } 2582 2583 if (HasRs) 2584 MI.addOperand( 2585 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2586 2587 if (HasRt) 2588 MI.addOperand( 2589 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2590 2591 MI.addOperand(MCOperand::createImm(Imm)); 2592 2593 return MCDisassembler::Success; 2594 } 2595 2596 template <typename InsnType> 2597 static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, 2598 uint64_t Address, 2599 const void *Decoder) { 2600 // We have: 2601 // 0b000110 ttttt sssss iiiiiiiiiiiiiiii 2602 // Invalid if rt == 0 2603 // BLEZALC_MMR6 if rs == 0 && rt != 0 2604 // BGEZALC_MMR6 if rs == rt && rt != 0 2605 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 2606 2607 InsnType Rt = fieldFromInstruction(insn, 21, 5); 2608 InsnType Rs = fieldFromInstruction(insn, 16, 5); 2609 InsnType Imm = 0; 2610 bool HasRs = false; 2611 2612 if (Rt == 0) 2613 return MCDisassembler::Fail; 2614 else if (Rs == 0) { 2615 MI.setOpcode(Mips::BLEZALC_MMR6); 2616 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2617 } 2618 else if (Rs == Rt) { 2619 MI.setOpcode(Mips::BGEZALC_MMR6); 2620 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; 2621 } 2622 else { 2623 HasRs = true; 2624 MI.setOpcode(Mips::BGEUC_MMR6); 2625 Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; 2626 } 2627 2628 if (HasRs) 2629 MI.addOperand( 2630 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); 2631 MI.addOperand( 2632 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); 2633 2634 MI.addOperand(MCOperand::createImm(Imm)); 2635 2636 return MCDisassembler::Success; 2637 } 2638