xref: /freebsd-src/contrib/llvm-project/llvm/lib/Target/MSP430/MSP430InstrFormats.td (revision 0b57cec536236d46e3dba9bd041533462f33dbb7)
1*0b57cec5SDimitry Andric//===-- MSP430InstrFormats.td - MSP430 Instruction Formats -*- tablegen -*-===//
2*0b57cec5SDimitry Andric//
3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information.
5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0b57cec5SDimitry Andric//
7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
8*0b57cec5SDimitry Andric
9*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
10*0b57cec5SDimitry Andric//  Describe MSP430 instructions format here
11*0b57cec5SDimitry Andric//
12*0b57cec5SDimitry Andric
13*0b57cec5SDimitry Andricclass SourceMode<bits<2> val> {
14*0b57cec5SDimitry Andric  bits<2> Value = val;
15*0b57cec5SDimitry Andric}
16*0b57cec5SDimitry Andric
17*0b57cec5SDimitry Andricdef SrcReg      : SourceMode<0>; // r
18*0b57cec5SDimitry Andricdef SrcMem      : SourceMode<1>; // m
19*0b57cec5SDimitry Andricdef SrcIndReg   : SourceMode<2>; // n
20*0b57cec5SDimitry Andricdef SrcPostInc  : SourceMode<3>; // p
21*0b57cec5SDimitry Andricdef SrcImm      : SourceMode<3>; // i
22*0b57cec5SDimitry Andric//  SrcCGImm    : SourceMode< >; // c
23*0b57cec5SDimitry Andric
24*0b57cec5SDimitry Andricclass DestMode<bit val> {
25*0b57cec5SDimitry Andric  bit Value = val;
26*0b57cec5SDimitry Andric}
27*0b57cec5SDimitry Andric
28*0b57cec5SDimitry Andricdef DstReg      : DestMode<0>;   // r
29*0b57cec5SDimitry Andricdef DstMem      : DestMode<1>;   // m
30*0b57cec5SDimitry Andric
31*0b57cec5SDimitry Andric// Generic MSP430 Format
32*0b57cec5SDimitry Andricclass MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
33*0b57cec5SDimitry Andric  field bits<48> Inst;
34*0b57cec5SDimitry Andric  field bits<48> SoftFail = 0;
35*0b57cec5SDimitry Andric
36*0b57cec5SDimitry Andric  let Namespace = "MSP430";
37*0b57cec5SDimitry Andric
38*0b57cec5SDimitry Andric  dag OutOperandList = outs;
39*0b57cec5SDimitry Andric  dag InOperandList  = ins;
40*0b57cec5SDimitry Andric
41*0b57cec5SDimitry Andric  let AsmString = asmstr;
42*0b57cec5SDimitry Andric  let Size = size;
43*0b57cec5SDimitry Andric}
44*0b57cec5SDimitry Andric
45*0b57cec5SDimitry Andric// MSP430 Double Operand (Format I) Instructions
46*0b57cec5SDimitry Andricclass IForm<bits<4> opcode, DestMode ad, bit bw, SourceMode as, int size,
47*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
48*0b57cec5SDimitry Andric  : MSP430Inst<outs, ins, size, asmstr> {
49*0b57cec5SDimitry Andric  let Pattern = pattern;
50*0b57cec5SDimitry Andric
51*0b57cec5SDimitry Andric  bits<4> rs;
52*0b57cec5SDimitry Andric  bits<4> rd;
53*0b57cec5SDimitry Andric
54*0b57cec5SDimitry Andric  let Inst{15-12} = opcode;
55*0b57cec5SDimitry Andric  let Inst{11-8}  = rs;
56*0b57cec5SDimitry Andric  let Inst{7}     = ad.Value;
57*0b57cec5SDimitry Andric  let Inst{6}     = bw;
58*0b57cec5SDimitry Andric  let Inst{5-4}   = as.Value;
59*0b57cec5SDimitry Andric  let Inst{3-0}   = rd;
60*0b57cec5SDimitry Andric}
61*0b57cec5SDimitry Andric
62*0b57cec5SDimitry Andric// 8 bit IForm instructions
63*0b57cec5SDimitry Andricclass IForm8<bits<4> opcode, DestMode dest, SourceMode src, int size,
64*0b57cec5SDimitry Andric             dag outs, dag ins, string asmstr, list<dag> pattern>
65*0b57cec5SDimitry Andric  : IForm<opcode, dest, 1, src, size, outs, ins, asmstr, pattern>;
66*0b57cec5SDimitry Andric
67*0b57cec5SDimitry Andricclass I8rr<bits<4> opcode,
68*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
69*0b57cec5SDimitry Andric  : IForm8<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
70*0b57cec5SDimitry Andric  let DecoderNamespace = "Alpha";
71*0b57cec5SDimitry Andric}
72*0b57cec5SDimitry Andric
73*0b57cec5SDimitry Andricclass I8ri<bits<4> opcode,
74*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
75*0b57cec5SDimitry Andric  : IForm8<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
76*0b57cec5SDimitry Andric  let DecoderNamespace = "Gamma";
77*0b57cec5SDimitry Andric  bits<16> imm;
78*0b57cec5SDimitry Andric  let Inst{31-16} = imm;
79*0b57cec5SDimitry Andric  let rs = 0b0000;
80*0b57cec5SDimitry Andric}
81*0b57cec5SDimitry Andric
82*0b57cec5SDimitry Andricclass I8rc<bits<4> opcode,
83*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
84*0b57cec5SDimitry Andric  : MSP430Inst<outs, ins, 2, asmstr> {
85*0b57cec5SDimitry Andric  let DecoderNamespace = "Beta";
86*0b57cec5SDimitry Andric  let Pattern = pattern;
87*0b57cec5SDimitry Andric
88*0b57cec5SDimitry Andric  bits<6> imm;
89*0b57cec5SDimitry Andric  bits<4> rd;
90*0b57cec5SDimitry Andric
91*0b57cec5SDimitry Andric  let Inst{15-12} = opcode;
92*0b57cec5SDimitry Andric  let Inst{11-8}  = imm{3-0};
93*0b57cec5SDimitry Andric  let Inst{7}     = DstReg.Value;
94*0b57cec5SDimitry Andric  let Inst{6}     = 1;
95*0b57cec5SDimitry Andric  let Inst{5-4}   = imm{5-4};
96*0b57cec5SDimitry Andric  let Inst{3-0}   = rd;
97*0b57cec5SDimitry Andric}
98*0b57cec5SDimitry Andric
99*0b57cec5SDimitry Andricclass I8rm<bits<4> opcode,
100*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
101*0b57cec5SDimitry Andric  : IForm8<opcode, DstReg, SrcMem, 4, outs, ins, asmstr, pattern> {
102*0b57cec5SDimitry Andric  let DecoderNamespace = "Gamma";
103*0b57cec5SDimitry Andric  bits<20> src;
104*0b57cec5SDimitry Andric  let rs = src{3-0};
105*0b57cec5SDimitry Andric  let Inst{31-16} = src{19-4};
106*0b57cec5SDimitry Andric}
107*0b57cec5SDimitry Andric
108*0b57cec5SDimitry Andricclass I8rn<bits<4> opcode,
109*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
110*0b57cec5SDimitry Andric  : IForm8<opcode, DstReg, SrcIndReg, 2, outs, ins, asmstr, pattern> {
111*0b57cec5SDimitry Andric  let DecoderNamespace = "Delta";
112*0b57cec5SDimitry Andric}
113*0b57cec5SDimitry Andric
114*0b57cec5SDimitry Andricclass I8rp<bits<4> opcode,
115*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
116*0b57cec5SDimitry Andric  : IForm8<opcode, DstReg, SrcPostInc, 2, outs, ins, asmstr, pattern> {
117*0b57cec5SDimitry Andric  let DecoderNamespace = "Delta";
118*0b57cec5SDimitry Andric}
119*0b57cec5SDimitry Andric
120*0b57cec5SDimitry Andricclass I8mr<bits<4> opcode,
121*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
122*0b57cec5SDimitry Andric  : IForm8<opcode, DstMem, SrcReg, 4, outs, ins, asmstr, pattern> {
123*0b57cec5SDimitry Andric  let DecoderNamespace = "Alpha";
124*0b57cec5SDimitry Andric  bits<20> dst;
125*0b57cec5SDimitry Andric  let rd = dst{3-0};
126*0b57cec5SDimitry Andric  let Inst{31-16} = dst{19-4};
127*0b57cec5SDimitry Andric}
128*0b57cec5SDimitry Andric
129*0b57cec5SDimitry Andricclass I8mi<bits<4> opcode,
130*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
131*0b57cec5SDimitry Andric  : IForm8<opcode, DstMem, SrcImm, 6, outs, ins, asmstr, pattern> {
132*0b57cec5SDimitry Andric  let DecoderNamespace = "Gamma";
133*0b57cec5SDimitry Andric  bits<16> imm;
134*0b57cec5SDimitry Andric  bits<20> dst;
135*0b57cec5SDimitry Andric  let rs = 0b0000;
136*0b57cec5SDimitry Andric  let Inst{31-16} = imm;
137*0b57cec5SDimitry Andric  let rd = dst{3-0};
138*0b57cec5SDimitry Andric  let Inst{47-32} = dst{19-4};
139*0b57cec5SDimitry Andric}
140*0b57cec5SDimitry Andric
141*0b57cec5SDimitry Andricclass I8mc<bits<4> opcode,
142*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
143*0b57cec5SDimitry Andric  : MSP430Inst<outs, ins, 4, asmstr> {
144*0b57cec5SDimitry Andric  let DecoderNamespace = "Beta";
145*0b57cec5SDimitry Andric  let Pattern = pattern;
146*0b57cec5SDimitry Andric
147*0b57cec5SDimitry Andric  bits<6> imm;
148*0b57cec5SDimitry Andric  bits<20> dst;
149*0b57cec5SDimitry Andric
150*0b57cec5SDimitry Andric  let Inst{31-16} = dst{19-4};
151*0b57cec5SDimitry Andric  let Inst{15-12} = opcode;
152*0b57cec5SDimitry Andric  let Inst{11-8}  = imm{3-0};
153*0b57cec5SDimitry Andric  let Inst{7}     = DstMem.Value;
154*0b57cec5SDimitry Andric  let Inst{6}     = 1;
155*0b57cec5SDimitry Andric  let Inst{5-4}   = imm{5-4};
156*0b57cec5SDimitry Andric  let Inst{3-0}   = dst{3-0};
157*0b57cec5SDimitry Andric}
158*0b57cec5SDimitry Andric
159*0b57cec5SDimitry Andricclass I8mm<bits<4> opcode,
160*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
161*0b57cec5SDimitry Andric  : IForm8<opcode, DstMem, SrcMem, 6, outs, ins, asmstr, pattern> {
162*0b57cec5SDimitry Andric  let DecoderNamespace = "Gamma";
163*0b57cec5SDimitry Andric  bits<20> src;
164*0b57cec5SDimitry Andric  bits<20> dst;
165*0b57cec5SDimitry Andric  let rs = src{3-0};
166*0b57cec5SDimitry Andric  let Inst{31-16} = src{19-4};
167*0b57cec5SDimitry Andric  let rd = dst{3-0};
168*0b57cec5SDimitry Andric  let Inst{47-32} = dst{19-4};
169*0b57cec5SDimitry Andric}
170*0b57cec5SDimitry Andric
171*0b57cec5SDimitry Andricclass I8mn<bits<4> opcode,
172*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
173*0b57cec5SDimitry Andric  : IForm8<opcode, DstMem, SrcIndReg, 4, outs, ins, asmstr, pattern> {
174*0b57cec5SDimitry Andric  let DecoderNamespace = "Delta";
175*0b57cec5SDimitry Andric  bits<20> dst;
176*0b57cec5SDimitry Andric  let rd = dst{3-0};
177*0b57cec5SDimitry Andric  let Inst{31-16} = dst{19-4};
178*0b57cec5SDimitry Andric}
179*0b57cec5SDimitry Andric
180*0b57cec5SDimitry Andricclass I8mp<bits<4> opcode,
181*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
182*0b57cec5SDimitry Andric  : IForm8<opcode, DstMem, SrcPostInc, 4, outs, ins, asmstr, pattern> {
183*0b57cec5SDimitry Andric  let DecoderNamespace = "Delta";
184*0b57cec5SDimitry Andric  bits<20> dst;
185*0b57cec5SDimitry Andric  let rd = dst{3-0};
186*0b57cec5SDimitry Andric  let Inst{31-16} = dst{19-4};
187*0b57cec5SDimitry Andric}
188*0b57cec5SDimitry Andric
189*0b57cec5SDimitry Andric// 16 bit IForm instructions
190*0b57cec5SDimitry Andricclass IForm16<bits<4> opcode, DestMode dest, SourceMode src, int size,
191*0b57cec5SDimitry Andric              dag outs, dag ins, string asmstr, list<dag> pattern>
192*0b57cec5SDimitry Andric  : IForm<opcode, dest, 0, src, size, outs, ins, asmstr, pattern>;
193*0b57cec5SDimitry Andric
194*0b57cec5SDimitry Andricclass I16rr<bits<4> opcode,
195*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
196*0b57cec5SDimitry Andric  : IForm16<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
197*0b57cec5SDimitry Andric  let DecoderNamespace = "Alpha";
198*0b57cec5SDimitry Andric}
199*0b57cec5SDimitry Andric
200*0b57cec5SDimitry Andricclass I16ri<bits<4> opcode,
201*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
202*0b57cec5SDimitry Andric  : IForm16<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
203*0b57cec5SDimitry Andric  let DecoderNamespace = "Gamma";
204*0b57cec5SDimitry Andric  bits<16> imm;
205*0b57cec5SDimitry Andric  let Inst{31-16} = imm;
206*0b57cec5SDimitry Andric  let rs = 0b0000;
207*0b57cec5SDimitry Andric}
208*0b57cec5SDimitry Andric
209*0b57cec5SDimitry Andricclass I16rc<bits<4> opcode,
210*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
211*0b57cec5SDimitry Andric  : MSP430Inst<outs, ins, 2, asmstr> {
212*0b57cec5SDimitry Andric  let DecoderNamespace = "Beta";
213*0b57cec5SDimitry Andric  let Pattern = pattern;
214*0b57cec5SDimitry Andric
215*0b57cec5SDimitry Andric  bits<6> imm;
216*0b57cec5SDimitry Andric  bits<4> rd;
217*0b57cec5SDimitry Andric
218*0b57cec5SDimitry Andric  let Inst{15-12} = opcode;
219*0b57cec5SDimitry Andric  let Inst{11-8}  = imm{3-0};
220*0b57cec5SDimitry Andric  let Inst{7}     = DstReg.Value;
221*0b57cec5SDimitry Andric  let Inst{6}     = 0;
222*0b57cec5SDimitry Andric  let Inst{5-4}   = imm{5-4};
223*0b57cec5SDimitry Andric  let Inst{3-0}   = rd;
224*0b57cec5SDimitry Andric}
225*0b57cec5SDimitry Andric
226*0b57cec5SDimitry Andricclass I16rm<bits<4> opcode,
227*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
228*0b57cec5SDimitry Andric  : IForm16<opcode, DstReg, SrcMem, 4, outs, ins, asmstr, pattern> {
229*0b57cec5SDimitry Andric  let DecoderNamespace = "Gamma";
230*0b57cec5SDimitry Andric  bits<20> src;
231*0b57cec5SDimitry Andric  let rs = src{3-0};
232*0b57cec5SDimitry Andric  let Inst{31-16} = src{19-4};
233*0b57cec5SDimitry Andric}
234*0b57cec5SDimitry Andric
235*0b57cec5SDimitry Andricclass I16rn<bits<4> opcode,
236*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
237*0b57cec5SDimitry Andric  : IForm16<opcode, DstReg, SrcIndReg, 2, outs, ins, asmstr, pattern> {
238*0b57cec5SDimitry Andric  let DecoderNamespace = "Delta";
239*0b57cec5SDimitry Andric}
240*0b57cec5SDimitry Andric
241*0b57cec5SDimitry Andricclass I16rp<bits<4> opcode,
242*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
243*0b57cec5SDimitry Andric  : IForm16<opcode, DstReg, SrcPostInc, 2, outs, ins, asmstr, pattern> {
244*0b57cec5SDimitry Andric  let DecoderNamespace = "Delta";
245*0b57cec5SDimitry Andric}
246*0b57cec5SDimitry Andric
247*0b57cec5SDimitry Andricclass I16mr<bits<4> opcode,
248*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
249*0b57cec5SDimitry Andric  : IForm16<opcode, DstMem, SrcReg, 4, outs, ins, asmstr, pattern> {
250*0b57cec5SDimitry Andric  let DecoderNamespace = "Alpha";
251*0b57cec5SDimitry Andric  bits<20> dst;
252*0b57cec5SDimitry Andric  let rd = dst{3-0};
253*0b57cec5SDimitry Andric  let Inst{31-16} = dst{19-4};
254*0b57cec5SDimitry Andric}
255*0b57cec5SDimitry Andric
256*0b57cec5SDimitry Andricclass I16mi<bits<4> opcode,
257*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
258*0b57cec5SDimitry Andric  : IForm16<opcode, DstMem, SrcImm, 6, outs, ins, asmstr, pattern> {
259*0b57cec5SDimitry Andric  let DecoderNamespace = "Gamma";
260*0b57cec5SDimitry Andric  bits<16> imm;
261*0b57cec5SDimitry Andric  bits<20> dst;
262*0b57cec5SDimitry Andric  let Inst{31-16} = imm;
263*0b57cec5SDimitry Andric  let rs = 0b0000;
264*0b57cec5SDimitry Andric  let rd = dst{3-0};
265*0b57cec5SDimitry Andric  let Inst{47-32} = dst{19-4};
266*0b57cec5SDimitry Andric}
267*0b57cec5SDimitry Andric
268*0b57cec5SDimitry Andricclass I16mc<bits<4> opcode,
269*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
270*0b57cec5SDimitry Andric  : MSP430Inst<outs, ins, 4, asmstr> {
271*0b57cec5SDimitry Andric  let DecoderNamespace = "Beta";
272*0b57cec5SDimitry Andric  let Pattern = pattern;
273*0b57cec5SDimitry Andric
274*0b57cec5SDimitry Andric  bits<6> imm;
275*0b57cec5SDimitry Andric  bits<20> dst;
276*0b57cec5SDimitry Andric
277*0b57cec5SDimitry Andric  let Inst{31-16} = dst{19-4};
278*0b57cec5SDimitry Andric  let Inst{15-12} = opcode;
279*0b57cec5SDimitry Andric  let Inst{11-8}  = imm{3-0};
280*0b57cec5SDimitry Andric  let Inst{7}     = DstMem.Value;
281*0b57cec5SDimitry Andric  let Inst{6}     = 0;
282*0b57cec5SDimitry Andric  let Inst{5-4}   = imm{5-4};
283*0b57cec5SDimitry Andric  let Inst{3-0}   = dst{3-0};
284*0b57cec5SDimitry Andric}
285*0b57cec5SDimitry Andric
286*0b57cec5SDimitry Andricclass I16mm<bits<4> opcode,
287*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
288*0b57cec5SDimitry Andric  : IForm16<opcode, DstMem, SrcMem, 6, outs, ins, asmstr, pattern> {
289*0b57cec5SDimitry Andric  let DecoderNamespace = "Gamma";
290*0b57cec5SDimitry Andric  bits<20> src;
291*0b57cec5SDimitry Andric  bits<20> dst;
292*0b57cec5SDimitry Andric  let rs = src{3-0};
293*0b57cec5SDimitry Andric  let Inst{31-16} = src{19-4};
294*0b57cec5SDimitry Andric  let rd = dst{3-0};
295*0b57cec5SDimitry Andric  let Inst{47-32} = dst{19-4};
296*0b57cec5SDimitry Andric}
297*0b57cec5SDimitry Andric
298*0b57cec5SDimitry Andricclass I16mn<bits<4> opcode,
299*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
300*0b57cec5SDimitry Andric  : IForm16<opcode, DstMem, SrcIndReg, 4, outs, ins, asmstr, pattern> {
301*0b57cec5SDimitry Andric  let DecoderNamespace = "Delta";
302*0b57cec5SDimitry Andric  bits<20> dst;
303*0b57cec5SDimitry Andric  let rd = dst{3-0};
304*0b57cec5SDimitry Andric  let Inst{31-16} = dst{19-4};
305*0b57cec5SDimitry Andric}
306*0b57cec5SDimitry Andric
307*0b57cec5SDimitry Andricclass I16mp<bits<4> opcode,
308*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
309*0b57cec5SDimitry Andric  : IForm16<opcode, DstMem, SrcPostInc, 4, outs, ins, asmstr, pattern> {
310*0b57cec5SDimitry Andric  let DecoderNamespace = "Delta";
311*0b57cec5SDimitry Andric  bits<20> dst;
312*0b57cec5SDimitry Andric  let rd = dst{3-0};
313*0b57cec5SDimitry Andric  let Inst{31-16} = dst{19-4};
314*0b57cec5SDimitry Andric}
315*0b57cec5SDimitry Andric
316*0b57cec5SDimitry Andric// MSP430 Single Operand (Format II) Instructions
317*0b57cec5SDimitry Andricclass IIForm<bits<3> opcode, bit bw, SourceMode as, int size,
318*0b57cec5SDimitry Andric             dag outs, dag ins, string asmstr, list<dag> pattern>
319*0b57cec5SDimitry Andric  : MSP430Inst<outs, ins, size, asmstr> {
320*0b57cec5SDimitry Andric  let Pattern = pattern;
321*0b57cec5SDimitry Andric
322*0b57cec5SDimitry Andric  bits<4> rs;
323*0b57cec5SDimitry Andric
324*0b57cec5SDimitry Andric  let Inst{15-10} = 0b000100;
325*0b57cec5SDimitry Andric  let Inst{9-7}   = opcode;
326*0b57cec5SDimitry Andric  let Inst{6}     = bw;
327*0b57cec5SDimitry Andric  let Inst{5-4}   = as.Value;
328*0b57cec5SDimitry Andric  let Inst{3-0}   = rs;
329*0b57cec5SDimitry Andric}
330*0b57cec5SDimitry Andric
331*0b57cec5SDimitry Andric// 8 bit IIForm instructions
332*0b57cec5SDimitry Andricclass IIForm8<bits<3> opcode, SourceMode src, int size,
333*0b57cec5SDimitry Andric              dag outs, dag ins, string asmstr, list<dag> pattern>
334*0b57cec5SDimitry Andric  : IIForm<opcode, 1, src, size, outs, ins, asmstr, pattern>;
335*0b57cec5SDimitry Andric
336*0b57cec5SDimitry Andricclass II8r<bits<3> opcode,
337*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
338*0b57cec5SDimitry Andric  : IIForm8<opcode, SrcReg, 2, outs, ins, asmstr, pattern>;
339*0b57cec5SDimitry Andric
340*0b57cec5SDimitry Andricclass II8m<bits<3> opcode,
341*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
342*0b57cec5SDimitry Andric  : IIForm8<opcode, SrcMem, 4, outs, ins, asmstr, pattern> {
343*0b57cec5SDimitry Andric  bits<20> src;
344*0b57cec5SDimitry Andric  let rs = src{3-0};
345*0b57cec5SDimitry Andric  let Inst{31-16} = src{19-4};
346*0b57cec5SDimitry Andric}
347*0b57cec5SDimitry Andric
348*0b57cec5SDimitry Andricclass II8i<bits<3> opcode,
349*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
350*0b57cec5SDimitry Andric  : IIForm8<opcode, SrcImm, 4, outs, ins, asmstr, pattern> {
351*0b57cec5SDimitry Andric  bits<16> imm;
352*0b57cec5SDimitry Andric  let rs = 0b0000;
353*0b57cec5SDimitry Andric  let Inst{31-16} = imm;
354*0b57cec5SDimitry Andric}
355*0b57cec5SDimitry Andric
356*0b57cec5SDimitry Andricclass II8c<bits<3> opcode,
357*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
358*0b57cec5SDimitry Andric  : MSP430Inst<outs, ins, 2, asmstr> {
359*0b57cec5SDimitry Andric  let Pattern = pattern;
360*0b57cec5SDimitry Andric
361*0b57cec5SDimitry Andric  bits<6> imm;
362*0b57cec5SDimitry Andric
363*0b57cec5SDimitry Andric  let Inst{15-10} = 0b000100;
364*0b57cec5SDimitry Andric  let Inst{9-7}   = opcode;
365*0b57cec5SDimitry Andric  let Inst{6}     = 1;
366*0b57cec5SDimitry Andric  let Inst{5-0}   = imm;
367*0b57cec5SDimitry Andric}
368*0b57cec5SDimitry Andric
369*0b57cec5SDimitry Andricclass II8n<bits<3> opcode,
370*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
371*0b57cec5SDimitry Andric  : IIForm8<opcode, SrcIndReg, 2, outs, ins, asmstr, pattern>;
372*0b57cec5SDimitry Andric
373*0b57cec5SDimitry Andricclass II8p<bits<3> opcode,
374*0b57cec5SDimitry Andric           dag outs, dag ins, string asmstr, list<dag> pattern>
375*0b57cec5SDimitry Andric  : IIForm8<opcode, SrcPostInc, 2, outs, ins, asmstr, pattern>;
376*0b57cec5SDimitry Andric
377*0b57cec5SDimitry Andric// 16 bit IIForm instructions
378*0b57cec5SDimitry Andricclass IIForm16<bits<3> opcode, SourceMode src, int size,
379*0b57cec5SDimitry Andric               dag outs, dag ins, string asmstr, list<dag> pattern>
380*0b57cec5SDimitry Andric  : IIForm<opcode, 0, src, size, outs, ins, asmstr, pattern>;
381*0b57cec5SDimitry Andric
382*0b57cec5SDimitry Andricclass II16r<bits<3> opcode,
383*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
384*0b57cec5SDimitry Andric  : IIForm16<opcode, SrcReg, 2, outs, ins, asmstr, pattern>;
385*0b57cec5SDimitry Andric
386*0b57cec5SDimitry Andricclass II16m<bits<3> opcode,
387*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
388*0b57cec5SDimitry Andric  : IIForm16<opcode, SrcMem, 4, outs, ins, asmstr, pattern> {
389*0b57cec5SDimitry Andric  bits<20> src;
390*0b57cec5SDimitry Andric  let rs = src{3-0};
391*0b57cec5SDimitry Andric  let Inst{31-16} = src{19-4};
392*0b57cec5SDimitry Andric}
393*0b57cec5SDimitry Andric
394*0b57cec5SDimitry Andricclass II16i<bits<3> opcode,
395*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
396*0b57cec5SDimitry Andric  : IIForm16<opcode, SrcImm, 4, outs, ins, asmstr, pattern> {
397*0b57cec5SDimitry Andric  bits<16> imm;
398*0b57cec5SDimitry Andric  let rs = 0b0000;
399*0b57cec5SDimitry Andric  let Inst{31-16} = imm;
400*0b57cec5SDimitry Andric}
401*0b57cec5SDimitry Andric
402*0b57cec5SDimitry Andricclass II16c<bits<3> opcode,
403*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
404*0b57cec5SDimitry Andric  : MSP430Inst<outs, ins, 2, asmstr> {
405*0b57cec5SDimitry Andric  let Pattern = pattern;
406*0b57cec5SDimitry Andric
407*0b57cec5SDimitry Andric  bits<6> imm;
408*0b57cec5SDimitry Andric
409*0b57cec5SDimitry Andric  let Inst{15-10} = 0b000100;
410*0b57cec5SDimitry Andric  let Inst{9-7}   = opcode;
411*0b57cec5SDimitry Andric  let Inst{6}     = 0;
412*0b57cec5SDimitry Andric  let Inst{5-0}   = imm;
413*0b57cec5SDimitry Andric}
414*0b57cec5SDimitry Andric
415*0b57cec5SDimitry Andricclass II16n<bits<3> opcode,
416*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
417*0b57cec5SDimitry Andric  : IIForm16<opcode, SrcIndReg, 2, outs, ins, asmstr, pattern>;
418*0b57cec5SDimitry Andric
419*0b57cec5SDimitry Andricclass II16p<bits<3> opcode,
420*0b57cec5SDimitry Andric            dag outs, dag ins, string asmstr, list<dag> pattern>
421*0b57cec5SDimitry Andric  : IIForm16<opcode, SrcPostInc, 2, outs, ins, asmstr, pattern>;
422*0b57cec5SDimitry Andric
423*0b57cec5SDimitry Andric// MSP430 Conditional Jumps Instructions
424*0b57cec5SDimitry Andricclass CJForm<dag outs, dag ins, string asmstr, list<dag> pattern>
425*0b57cec5SDimitry Andric  : MSP430Inst<outs, ins, 2, asmstr> {
426*0b57cec5SDimitry Andric  let Pattern = pattern;
427*0b57cec5SDimitry Andric
428*0b57cec5SDimitry Andric  bits<3> cond;
429*0b57cec5SDimitry Andric  bits<10> dst;
430*0b57cec5SDimitry Andric
431*0b57cec5SDimitry Andric  let Inst{15-13} = 0b001;
432*0b57cec5SDimitry Andric  let Inst{12-10} = cond;
433*0b57cec5SDimitry Andric  let Inst{9-0} = dst;
434*0b57cec5SDimitry Andric}
435*0b57cec5SDimitry Andric
436*0b57cec5SDimitry Andric// Pseudo instructions
437*0b57cec5SDimitry Andricclass Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
438*0b57cec5SDimitry Andric  : MSP430Inst<outs, ins, 0, asmstr> {
439*0b57cec5SDimitry Andric  let Pattern = pattern;
440*0b57cec5SDimitry Andric}
441