1*0b57cec5SDimitry Andric//=-LanaiSchedule.td - Lanai Scheduling Definitions --*- tablegen -*-=========// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric 9*0b57cec5SDimitry Andricdef ALU_FU : FuncUnit; 10*0b57cec5SDimitry Andricdef LDST_FU : FuncUnit; 11*0b57cec5SDimitry Andric 12*0b57cec5SDimitry Andricdef IIC_ALU : InstrItinClass; 13*0b57cec5SDimitry Andricdef IIC_LD : InstrItinClass; 14*0b57cec5SDimitry Andricdef IIC_ST : InstrItinClass; 15*0b57cec5SDimitry Andricdef IIC_LDSW : InstrItinClass; 16*0b57cec5SDimitry Andricdef IIC_STSW : InstrItinClass; 17*0b57cec5SDimitry Andric 18*0b57cec5SDimitry Andricdef LanaiItinerary : ProcessorItineraries<[ALU_FU, LDST_FU],[],[ 19*0b57cec5SDimitry Andric InstrItinData<IIC_LD, [InstrStage<1, [LDST_FU]>]>, 20*0b57cec5SDimitry Andric InstrItinData<IIC_ST, [InstrStage<1, [LDST_FU]>]>, 21*0b57cec5SDimitry Andric InstrItinData<IIC_LDSW, [InstrStage<2, [LDST_FU]>]>, 22*0b57cec5SDimitry Andric InstrItinData<IIC_STSW, [InstrStage<2, [LDST_FU]>]>, 23*0b57cec5SDimitry Andric InstrItinData<IIC_ALU, [InstrStage<1, [ALU_FU]>]> 24*0b57cec5SDimitry Andric]>; 25*0b57cec5SDimitry Andric 26*0b57cec5SDimitry Andricdef LanaiSchedModel : SchedMachineModel { 27*0b57cec5SDimitry Andric // Cycles for loads to access the cache [default = -1] 28*0b57cec5SDimitry Andric let LoadLatency = 2; 29*0b57cec5SDimitry Andric 30*0b57cec5SDimitry Andric // Max micro-ops that can be buffered for optimized loop dispatch/execution. 31*0b57cec5SDimitry Andric // [default = -1] 32*0b57cec5SDimitry Andric let LoopMicroOpBufferSize = 0; 33*0b57cec5SDimitry Andric 34*0b57cec5SDimitry Andric // Allow scheduler to assign default model to any unrecognized opcodes. 35*0b57cec5SDimitry Andric // [default = 1] 36*0b57cec5SDimitry Andric let CompleteModel = 0; 37*0b57cec5SDimitry Andric 38*0b57cec5SDimitry Andric // Max micro-ops that may be scheduled per cycle. [default = 1] 39*0b57cec5SDimitry Andric let IssueWidth = 1; 40*0b57cec5SDimitry Andric 41*0b57cec5SDimitry Andric // Extra cycles for a mispredicted branch. [default = -1] 42*0b57cec5SDimitry Andric let MispredictPenalty = 10; 43*0b57cec5SDimitry Andric 44*0b57cec5SDimitry Andric // Enable Post RegAlloc Scheduler pass. [default = 0] 45*0b57cec5SDimitry Andric let PostRAScheduler = 0; 46*0b57cec5SDimitry Andric 47*0b57cec5SDimitry Andric // Max micro-ops that can be buffered. [default = -1] 48*0b57cec5SDimitry Andric let MicroOpBufferSize = 0; 49*0b57cec5SDimitry Andric 50*0b57cec5SDimitry Andric // Per-cycle resources tables. [default = NoItineraries] 51*0b57cec5SDimitry Andric let Itineraries = LanaiItinerary; 52*0b57cec5SDimitry Andric} 53*0b57cec5SDimitry Andric 54*0b57cec5SDimitry Andricdef ALU : ProcResource<1> { let BufferSize = 0; } 55*0b57cec5SDimitry Andricdef LdSt : ProcResource<1> { let BufferSize = 0; } 56*0b57cec5SDimitry Andric 57*0b57cec5SDimitry Andricdef WriteLD : SchedWrite; 58*0b57cec5SDimitry Andricdef WriteST : SchedWrite; 59*0b57cec5SDimitry Andricdef WriteLDSW : SchedWrite; 60*0b57cec5SDimitry Andricdef WriteSTSW : SchedWrite; 61*0b57cec5SDimitry Andricdef WriteALU : SchedWrite; 62*0b57cec5SDimitry Andric 63*0b57cec5SDimitry Andriclet SchedModel = LanaiSchedModel in { 64*0b57cec5SDimitry Andric def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65*0b57cec5SDimitry Andric def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66*0b57cec5SDimitry Andric def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67*0b57cec5SDimitry Andric def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; } 68*0b57cec5SDimitry Andric def : WriteRes<WriteALU, [ALU]> { let Latency = 1; } 69*0b57cec5SDimitry Andric} 70