1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/MC/TargetRegistry.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &CStream) const override; 141 142 private: 143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 144 ArrayRef<uint8_t> Bytes, uint64_t Address, 145 raw_ostream &CStream) const; 146 147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 148 ArrayRef<uint8_t> Bytes, uint64_t Address, 149 raw_ostream &CStream) const; 150 151 mutable ITStatus ITBlock; 152 mutable VPTStatus VPTBlock; 153 154 DecodeStatus AddThumbPredicate(MCInst&) const; 155 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 156 }; 157 158 } // end anonymous namespace 159 160 static bool Check(DecodeStatus &Out, DecodeStatus In) { 161 switch (In) { 162 case MCDisassembler::Success: 163 // Out stays the same. 164 return true; 165 case MCDisassembler::SoftFail: 166 Out = In; 167 return true; 168 case MCDisassembler::Fail: 169 Out = In; 170 return false; 171 } 172 llvm_unreachable("Invalid DecodeStatus!"); 173 } 174 175 // Forward declare these because the autogenerated code will reference them. 176 // Definitions are further down. 177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus 186 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodeGPRwithZRnospRegisterClass( 198 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, 211 const void *Decoder); 212 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 223 unsigned RegNo, 224 uint64_t Address, 225 const void *Decoder); 226 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 231 uint64_t Address, 232 const void *Decoder); 233 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 234 uint64_t Address, 235 const void *Decoder); 236 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 239 unsigned RegNo, uint64_t Address, 240 const void *Decoder); 241 242 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 253 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 258 unsigned Insn, 259 uint64_t Address, 260 const void *Decoder); 261 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 270 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 271 unsigned Insn, 272 uint64_t Adddress, 273 const void *Decoder); 274 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 345 uint64_t Address, const void *Decoder); 346 template<int shift> 347 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 400 unsigned Val, 401 uint64_t Address, 402 const void *Decoder); 403 404 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 405 uint64_t Address, const void *Decoder); 406 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 407 uint64_t Address, const void *Decoder); 408 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 409 uint64_t Address, const void *Decoder); 410 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 411 uint64_t Address, const void *Decoder); 412 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 413 uint64_t Address, const void *Decoder); 414 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 415 uint64_t Address, const void *Decoder); 416 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 417 uint64_t Address, const void *Decoder); 418 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 419 uint64_t Address, const void *Decoder); 420 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 421 uint64_t Address, const void *Decoder); 422 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 423 uint64_t Address, const void *Decoder); 424 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 425 uint64_t Address, const void* Decoder); 426 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 427 uint64_t Address, const void* Decoder); 428 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 429 uint64_t Address, const void* Decoder); 430 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 431 uint64_t Address, const void* Decoder); 432 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 433 uint64_t Address, const void *Decoder); 434 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 435 uint64_t Address, const void *Decoder); 436 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 437 uint64_t Address, const void *Decoder); 438 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 439 uint64_t Address, 440 const void *Decoder); 441 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 442 uint64_t Address, const void *Decoder); 443 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 444 uint64_t Address, const void *Decoder); 445 template<int shift> 446 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 447 uint64_t Address, const void *Decoder); 448 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 449 uint64_t Address, const void *Decoder); 450 template<int shift> 451 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 452 uint64_t Address, const void *Decoder); 453 template<int shift, int WriteBack> 454 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 455 uint64_t Address, const void *Decoder); 456 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 457 uint64_t Address, const void *Decoder); 458 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 459 uint64_t Address, const void *Decoder); 460 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 461 uint64_t Address, const void *Decoder); 462 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 463 uint64_t Address, const void *Decoder); 464 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 465 uint64_t Address, const void *Decoder); 466 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 467 uint64_t Address, const void *Decoder); 468 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 469 uint64_t Address, const void *Decoder); 470 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 471 uint64_t Address, const void *Decoder); 472 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 473 uint64_t Address, const void *Decoder); 474 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 475 uint64_t Address, const void *Decoder); 476 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 477 uint64_t Address, const void *Decoder); 478 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 479 uint64_t Address, const void *Decoder); 480 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 481 uint64_t Address, const void *Decoder); 482 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 483 uint64_t Address, const void *Decoder); 484 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 485 uint64_t Address, const void *Decoder); 486 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 487 uint64_t Address, const void *Decoder); 488 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 489 uint64_t Address, const void *Decoder); 490 491 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 492 uint64_t Address, const void *Decoder); 493 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 494 uint64_t Address, const void *Decoder); 495 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 496 uint64_t Address, const void *Decoder); 497 498 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 499 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 500 uint64_t Address, const void *Decoder); 501 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 502 uint64_t Address, 503 const void *Decoder); 504 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 505 uint64_t Address, 506 const void *Decoder); 507 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 508 const void *Decoder); 509 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 510 uint64_t Address, 511 const void *Decoder); 512 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 513 const void *Decoder); 514 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 515 uint64_t Address, const void *Decoder); 516 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 517 uint64_t Address, const void *Decoder); 518 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 519 uint64_t Address, 520 const void *Decoder); 521 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 522 uint64_t Address, 523 const void *Decoder); 524 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 525 uint64_t Address, 526 const void *Decoder); 527 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 528 unsigned Val, 529 uint64_t Address, 530 const void *Decoder); 531 template<bool Writeback> 532 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 533 uint64_t Address, 534 const void *Decoder); 535 template<int shift> 536 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 537 uint64_t Address, const void *Decoder); 538 template<int shift> 539 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 540 uint64_t Address, const void *Decoder); 541 template<int shift> 542 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 543 uint64_t Address, const void *Decoder); 544 template<unsigned MinLog, unsigned MaxLog> 545 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 546 uint64_t Address, 547 const void *Decoder); 548 template<unsigned start> 549 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 550 uint64_t Address, 551 const void *Decoder); 552 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 553 uint64_t Address, 554 const void *Decoder); 555 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 556 uint64_t Address, 557 const void *Decoder); 558 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 559 uint64_t Address, const void *Decoder); 560 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 561 uint64_t Address, const void *Decoder); 562 template<bool scalar, OperandDecoder predicate_decoder> 563 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 564 uint64_t Address, const void *Decoder); 565 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 566 uint64_t Address, const void *Decoder); 567 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 568 uint64_t Address, const void *Decoder); 569 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 570 uint64_t Address, 571 const void *Decoder); 572 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 573 uint64_t Address, const void *Decoder); 574 575 #include "ARMGenDisassemblerTables.inc" 576 577 static MCDisassembler *createARMDisassembler(const Target &T, 578 const MCSubtargetInfo &STI, 579 MCContext &Ctx) { 580 return new ARMDisassembler(STI, Ctx); 581 } 582 583 // Post-decoding checks 584 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 585 uint64_t Address, raw_ostream &CS, 586 uint32_t Insn, 587 DecodeStatus Result) { 588 switch (MI.getOpcode()) { 589 case ARM::HVC: { 590 // HVC is undefined if condition = 0xf otherwise upredictable 591 // if condition != 0xe 592 uint32_t Cond = (Insn >> 28) & 0xF; 593 if (Cond == 0xF) 594 return MCDisassembler::Fail; 595 if (Cond != 0xE) 596 return MCDisassembler::SoftFail; 597 return Result; 598 } 599 case ARM::t2ADDri: 600 case ARM::t2ADDri12: 601 case ARM::t2ADDrr: 602 case ARM::t2ADDrs: 603 case ARM::t2SUBri: 604 case ARM::t2SUBri12: 605 case ARM::t2SUBrr: 606 case ARM::t2SUBrs: 607 if (MI.getOperand(0).getReg() == ARM::SP && 608 MI.getOperand(1).getReg() != ARM::SP) 609 return MCDisassembler::SoftFail; 610 return Result; 611 default: return Result; 612 } 613 } 614 615 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 616 ArrayRef<uint8_t> Bytes, 617 uint64_t Address, 618 raw_ostream &CS) const { 619 if (STI.getFeatureBits()[ARM::ModeThumb]) 620 return getThumbInstruction(MI, Size, Bytes, Address, CS); 621 return getARMInstruction(MI, Size, Bytes, Address, CS); 622 } 623 624 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 625 ArrayRef<uint8_t> Bytes, 626 uint64_t Address, 627 raw_ostream &CS) const { 628 CommentStream = &CS; 629 630 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 631 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 632 "mode!"); 633 634 // We want to read exactly 4 bytes of data. 635 if (Bytes.size() < 4) { 636 Size = 0; 637 return MCDisassembler::Fail; 638 } 639 640 // Encoded as a small-endian 32-bit word in the stream. 641 uint32_t Insn = 642 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 643 644 // Calling the auto-generated decoder function. 645 DecodeStatus Result = 646 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 647 if (Result != MCDisassembler::Fail) { 648 Size = 4; 649 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 650 } 651 652 struct DecodeTable { 653 const uint8_t *P; 654 bool DecodePred; 655 }; 656 657 const DecodeTable Tables[] = { 658 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 659 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 660 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 661 {DecoderTablev8Crypto32, false}, 662 }; 663 664 for (auto Table : Tables) { 665 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 666 if (Result != MCDisassembler::Fail) { 667 Size = 4; 668 // Add a fake predicate operand, because we share these instruction 669 // definitions with Thumb2 where these instructions are predicable. 670 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 671 return MCDisassembler::Fail; 672 return Result; 673 } 674 } 675 676 Result = 677 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 678 if (Result != MCDisassembler::Fail) { 679 Size = 4; 680 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 681 } 682 683 Size = 4; 684 return MCDisassembler::Fail; 685 } 686 687 namespace llvm { 688 689 extern const MCInstrDesc ARMInsts[]; 690 691 } // end namespace llvm 692 693 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 694 /// immediate Value in the MCInst. The immediate Value has had any PC 695 /// adjustment made by the caller. If the instruction is a branch instruction 696 /// then isBranch is true, else false. If the getOpInfo() function was set as 697 /// part of the setupForSymbolicDisassembly() call then that function is called 698 /// to get any symbolic information at the Address for this instruction. If 699 /// that returns non-zero then the symbolic information it returns is used to 700 /// create an MCExpr and that is added as an operand to the MCInst. If 701 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 702 /// Value is done and if a symbol is found an MCExpr is created with that, else 703 /// an MCExpr with Value is created. This function returns true if it adds an 704 /// operand to the MCInst and false otherwise. 705 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 706 bool isBranch, uint64_t InstSize, 707 MCInst &MI, const void *Decoder) { 708 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 709 // FIXME: Does it make sense for value to be negative? 710 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 711 /* Offset */ 0, InstSize); 712 } 713 714 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 715 /// referenced by a load instruction with the base register that is the Pc. 716 /// These can often be values in a literal pool near the Address of the 717 /// instruction. The Address of the instruction and its immediate Value are 718 /// used as a possible literal pool entry. The SymbolLookUp call back will 719 /// return the name of a symbol referenced by the literal pool's entry if 720 /// the referenced address is that of a symbol. Or it will return a pointer to 721 /// a literal 'C' string if the referenced address of the literal pool's entry 722 /// is an address into a section with 'C' string literals. 723 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 724 const void *Decoder) { 725 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 726 Dis->tryAddingPcLoadReferenceComment(Value, Address); 727 } 728 729 // Thumb1 instructions don't have explicit S bits. Rather, they 730 // implicitly set CPSR. Since it's not represented in the encoding, the 731 // auto-generated decoder won't inject the CPSR operand. We need to fix 732 // that as a post-pass. 733 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 734 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 735 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 736 MCInst::iterator I = MI.begin(); 737 for (unsigned i = 0; i < NumOps; ++i, ++I) { 738 if (I == MI.end()) break; 739 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 740 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 741 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 742 return; 743 } 744 } 745 746 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 747 } 748 749 static bool isVectorPredicable(unsigned Opcode) { 750 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 751 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 752 for (unsigned i = 0; i < NumOps; ++i) { 753 if (ARM::isVpred(OpInfo[i].OperandType)) 754 return true; 755 } 756 return false; 757 } 758 759 // Most Thumb instructions don't have explicit predicates in the 760 // encoding, but rather get their predicates from IT context. We need 761 // to fix up the predicate operands using this context information as a 762 // post-pass. 763 MCDisassembler::DecodeStatus 764 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 765 MCDisassembler::DecodeStatus S = Success; 766 767 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 768 769 // A few instructions actually have predicates encoded in them. Don't 770 // try to overwrite it if we're seeing one of those. 771 switch (MI.getOpcode()) { 772 case ARM::tBcc: 773 case ARM::t2Bcc: 774 case ARM::tCBZ: 775 case ARM::tCBNZ: 776 case ARM::tCPS: 777 case ARM::t2CPS3p: 778 case ARM::t2CPS2p: 779 case ARM::t2CPS1p: 780 case ARM::t2CSEL: 781 case ARM::t2CSINC: 782 case ARM::t2CSINV: 783 case ARM::t2CSNEG: 784 case ARM::tMOVSr: 785 case ARM::tSETEND: 786 // Some instructions (mostly conditional branches) are not 787 // allowed in IT blocks. 788 if (ITBlock.instrInITBlock()) 789 S = SoftFail; 790 else 791 return Success; 792 break; 793 case ARM::t2HINT: 794 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 795 S = SoftFail; 796 break; 797 case ARM::tB: 798 case ARM::t2B: 799 case ARM::t2TBB: 800 case ARM::t2TBH: 801 // Some instructions (mostly unconditional branches) can 802 // only appears at the end of, or outside of, an IT. 803 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 804 S = SoftFail; 805 break; 806 default: 807 break; 808 } 809 810 // Warn on non-VPT predicable instruction in a VPT block and a VPT 811 // predicable instruction in an IT block 812 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 813 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 814 S = SoftFail; 815 816 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 817 // assume a predicate of AL. 818 unsigned CC = ARMCC::AL; 819 unsigned VCC = ARMVCC::None; 820 if (ITBlock.instrInITBlock()) { 821 CC = ITBlock.getITCC(); 822 ITBlock.advanceITState(); 823 } else if (VPTBlock.instrInVPTBlock()) { 824 VCC = VPTBlock.getVPTPred(); 825 VPTBlock.advanceVPTState(); 826 } 827 828 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 829 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 830 831 MCInst::iterator CCI = MI.begin(); 832 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 833 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 834 } 835 836 if (ARMInsts[MI.getOpcode()].isPredicable()) { 837 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 838 ++CCI; 839 if (CC == ARMCC::AL) 840 MI.insert(CCI, MCOperand::createReg(0)); 841 else 842 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 843 } else if (CC != ARMCC::AL) { 844 Check(S, SoftFail); 845 } 846 847 MCInst::iterator VCCI = MI.begin(); 848 unsigned VCCPos; 849 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 850 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 851 } 852 853 if (isVectorPredicable(MI.getOpcode())) { 854 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 855 ++VCCI; 856 if (VCC == ARMVCC::None) 857 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 858 else 859 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 860 ++VCCI; 861 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 862 ++VCCI; 863 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 864 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 865 VCCPos + 3, MCOI::TIED_TO); 866 assert(TiedOp >= 0 && 867 "Inactive register in vpred_r is not tied to an output!"); 868 // Copy the operand to ensure it's not invalidated when MI grows. 869 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); 870 } 871 } else if (VCC != ARMVCC::None) { 872 Check(S, SoftFail); 873 } 874 875 return S; 876 } 877 878 // Thumb VFP instructions are a special case. Because we share their 879 // encodings between ARM and Thumb modes, and they are predicable in ARM 880 // mode, the auto-generated decoder will give them an (incorrect) 881 // predicate operand. We need to rewrite these operands based on the IT 882 // context as a post-pass. 883 void ARMDisassembler::UpdateThumbVFPPredicate( 884 DecodeStatus &S, MCInst &MI) const { 885 unsigned CC; 886 CC = ITBlock.getITCC(); 887 if (CC == 0xF) 888 CC = ARMCC::AL; 889 if (ITBlock.instrInITBlock()) 890 ITBlock.advanceITState(); 891 else if (VPTBlock.instrInVPTBlock()) { 892 CC = VPTBlock.getVPTPred(); 893 VPTBlock.advanceVPTState(); 894 } 895 896 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 897 MCInst::iterator I = MI.begin(); 898 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 899 for (unsigned i = 0; i < NumOps; ++i, ++I) { 900 if (OpInfo[i].isPredicate() ) { 901 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 902 Check(S, SoftFail); 903 I->setImm(CC); 904 ++I; 905 if (CC == ARMCC::AL) 906 I->setReg(0); 907 else 908 I->setReg(ARM::CPSR); 909 return; 910 } 911 } 912 } 913 914 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 915 ArrayRef<uint8_t> Bytes, 916 uint64_t Address, 917 raw_ostream &CS) const { 918 CommentStream = &CS; 919 920 assert(STI.getFeatureBits()[ARM::ModeThumb] && 921 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 922 923 // We want to read exactly 2 bytes of data. 924 if (Bytes.size() < 2) { 925 Size = 0; 926 return MCDisassembler::Fail; 927 } 928 929 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 930 DecodeStatus Result = 931 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 932 if (Result != MCDisassembler::Fail) { 933 Size = 2; 934 Check(Result, AddThumbPredicate(MI)); 935 return Result; 936 } 937 938 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 939 STI); 940 if (Result) { 941 Size = 2; 942 bool InITBlock = ITBlock.instrInITBlock(); 943 Check(Result, AddThumbPredicate(MI)); 944 AddThumb1SBit(MI, InITBlock); 945 return Result; 946 } 947 948 Result = 949 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 950 if (Result != MCDisassembler::Fail) { 951 Size = 2; 952 953 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 954 // the Thumb predicate. 955 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 956 Result = MCDisassembler::SoftFail; 957 958 Check(Result, AddThumbPredicate(MI)); 959 960 // If we find an IT instruction, we need to parse its condition 961 // code and mask operands so that we can apply them correctly 962 // to the subsequent instructions. 963 if (MI.getOpcode() == ARM::t2IT) { 964 unsigned Firstcond = MI.getOperand(0).getImm(); 965 unsigned Mask = MI.getOperand(1).getImm(); 966 ITBlock.setITState(Firstcond, Mask); 967 968 // An IT instruction that would give a 'NV' predicate is unpredictable. 969 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 970 CS << "unpredictable IT predicate sequence"; 971 } 972 973 return Result; 974 } 975 976 // We want to read exactly 4 bytes of data. 977 if (Bytes.size() < 4) { 978 Size = 0; 979 return MCDisassembler::Fail; 980 } 981 982 uint32_t Insn32 = 983 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 984 985 Result = 986 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 987 if (Result != MCDisassembler::Fail) { 988 Size = 4; 989 990 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 991 // the VPT predicate. 992 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 993 Result = MCDisassembler::SoftFail; 994 995 Check(Result, AddThumbPredicate(MI)); 996 997 if (isVPTOpcode(MI.getOpcode())) { 998 unsigned Mask = MI.getOperand(0).getImm(); 999 VPTBlock.setVPTState(Mask); 1000 } 1001 1002 return Result; 1003 } 1004 1005 Result = 1006 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1007 if (Result != MCDisassembler::Fail) { 1008 Size = 4; 1009 bool InITBlock = ITBlock.instrInITBlock(); 1010 Check(Result, AddThumbPredicate(MI)); 1011 AddThumb1SBit(MI, InITBlock); 1012 return Result; 1013 } 1014 1015 Result = 1016 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1017 if (Result != MCDisassembler::Fail) { 1018 Size = 4; 1019 Check(Result, AddThumbPredicate(MI)); 1020 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1021 } 1022 1023 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1024 Result = 1025 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1026 if (Result != MCDisassembler::Fail) { 1027 Size = 4; 1028 UpdateThumbVFPPredicate(Result, MI); 1029 return Result; 1030 } 1031 } 1032 1033 Result = 1034 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1035 if (Result != MCDisassembler::Fail) { 1036 Size = 4; 1037 return Result; 1038 } 1039 1040 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1041 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1042 STI); 1043 if (Result != MCDisassembler::Fail) { 1044 Size = 4; 1045 Check(Result, AddThumbPredicate(MI)); 1046 return Result; 1047 } 1048 } 1049 1050 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1051 uint32_t NEONLdStInsn = Insn32; 1052 NEONLdStInsn &= 0xF0FFFFFF; 1053 NEONLdStInsn |= 0x04000000; 1054 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1055 Address, this, STI); 1056 if (Result != MCDisassembler::Fail) { 1057 Size = 4; 1058 Check(Result, AddThumbPredicate(MI)); 1059 return Result; 1060 } 1061 } 1062 1063 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1064 uint32_t NEONDataInsn = Insn32; 1065 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1066 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1067 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1068 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1069 Address, this, STI); 1070 if (Result != MCDisassembler::Fail) { 1071 Size = 4; 1072 Check(Result, AddThumbPredicate(MI)); 1073 return Result; 1074 } 1075 1076 uint32_t NEONCryptoInsn = Insn32; 1077 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1078 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1079 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1080 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1081 Address, this, STI); 1082 if (Result != MCDisassembler::Fail) { 1083 Size = 4; 1084 return Result; 1085 } 1086 1087 uint32_t NEONv8Insn = Insn32; 1088 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1089 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1090 this, STI); 1091 if (Result != MCDisassembler::Fail) { 1092 Size = 4; 1093 return Result; 1094 } 1095 } 1096 1097 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1098 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1099 ? DecoderTableThumb2CDE32 1100 : DecoderTableThumb2CoProc32; 1101 Result = 1102 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1103 if (Result != MCDisassembler::Fail) { 1104 Size = 4; 1105 Check(Result, AddThumbPredicate(MI)); 1106 return Result; 1107 } 1108 1109 Size = 0; 1110 return MCDisassembler::Fail; 1111 } 1112 1113 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1114 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1115 createARMDisassembler); 1116 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1117 createARMDisassembler); 1118 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1119 createARMDisassembler); 1120 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1121 createARMDisassembler); 1122 } 1123 1124 static const uint16_t GPRDecoderTable[] = { 1125 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1126 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1127 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1128 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1129 }; 1130 1131 static const uint16_t CLRMGPRDecoderTable[] = { 1132 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1133 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1134 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1135 ARM::R12, 0, ARM::LR, ARM::APSR 1136 }; 1137 1138 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1139 uint64_t Address, const void *Decoder) { 1140 if (RegNo > 15) 1141 return MCDisassembler::Fail; 1142 1143 unsigned Register = GPRDecoderTable[RegNo]; 1144 Inst.addOperand(MCOperand::createReg(Register)); 1145 return MCDisassembler::Success; 1146 } 1147 1148 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1149 uint64_t Address, 1150 const void *Decoder) { 1151 if (RegNo > 15) 1152 return MCDisassembler::Fail; 1153 1154 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1155 if (Register == 0) 1156 return MCDisassembler::Fail; 1157 1158 Inst.addOperand(MCOperand::createReg(Register)); 1159 return MCDisassembler::Success; 1160 } 1161 1162 static DecodeStatus 1163 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1164 uint64_t Address, const void *Decoder) { 1165 DecodeStatus S = MCDisassembler::Success; 1166 1167 if (RegNo == 15) 1168 S = MCDisassembler::SoftFail; 1169 1170 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1171 1172 return S; 1173 } 1174 1175 static DecodeStatus 1176 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1177 uint64_t Address, const void *Decoder) { 1178 DecodeStatus S = MCDisassembler::Success; 1179 1180 if (RegNo == 15) 1181 { 1182 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1183 return MCDisassembler::Success; 1184 } 1185 1186 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1187 return S; 1188 } 1189 1190 static DecodeStatus 1191 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1192 uint64_t Address, const void *Decoder) { 1193 DecodeStatus S = MCDisassembler::Success; 1194 1195 if (RegNo == 15) 1196 { 1197 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1198 return MCDisassembler::Success; 1199 } 1200 1201 if (RegNo == 13) 1202 Check(S, MCDisassembler::SoftFail); 1203 1204 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1205 return S; 1206 } 1207 1208 static DecodeStatus 1209 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1210 uint64_t Address, const void *Decoder) { 1211 DecodeStatus S = MCDisassembler::Success; 1212 if (RegNo == 13) 1213 return MCDisassembler::Fail; 1214 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1215 return S; 1216 } 1217 1218 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1219 uint64_t Address, const void *Decoder) { 1220 if (RegNo > 7) 1221 return MCDisassembler::Fail; 1222 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1223 } 1224 1225 static const uint16_t GPRPairDecoderTable[] = { 1226 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1227 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1228 }; 1229 1230 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1231 uint64_t Address, const void *Decoder) { 1232 DecodeStatus S = MCDisassembler::Success; 1233 1234 // According to the Arm ARM RegNo = 14 is undefined, but we return fail 1235 // rather than SoftFail as there is no GPRPair table entry for index 7. 1236 if (RegNo > 13) 1237 return MCDisassembler::Fail; 1238 1239 if (RegNo & 1) 1240 S = MCDisassembler::SoftFail; 1241 1242 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1243 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1244 return S; 1245 } 1246 1247 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, 1248 uint64_t Address, const void *Decoder) { 1249 if (RegNo > 13) 1250 return MCDisassembler::Fail; 1251 1252 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1253 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1254 1255 if ((RegNo & 1) || RegNo > 10) 1256 return MCDisassembler::SoftFail; 1257 return MCDisassembler::Success; 1258 } 1259 1260 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1261 uint64_t Address, 1262 const void *Decoder) { 1263 if (RegNo != 13) 1264 return MCDisassembler::Fail; 1265 1266 unsigned Register = GPRDecoderTable[RegNo]; 1267 Inst.addOperand(MCOperand::createReg(Register)); 1268 return MCDisassembler::Success; 1269 } 1270 1271 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1272 uint64_t Address, const void *Decoder) { 1273 unsigned Register = 0; 1274 switch (RegNo) { 1275 case 0: 1276 Register = ARM::R0; 1277 break; 1278 case 1: 1279 Register = ARM::R1; 1280 break; 1281 case 2: 1282 Register = ARM::R2; 1283 break; 1284 case 3: 1285 Register = ARM::R3; 1286 break; 1287 case 9: 1288 Register = ARM::R9; 1289 break; 1290 case 12: 1291 Register = ARM::R12; 1292 break; 1293 default: 1294 return MCDisassembler::Fail; 1295 } 1296 1297 Inst.addOperand(MCOperand::createReg(Register)); 1298 return MCDisassembler::Success; 1299 } 1300 1301 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1302 uint64_t Address, const void *Decoder) { 1303 DecodeStatus S = MCDisassembler::Success; 1304 1305 const FeatureBitset &featureBits = 1306 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1307 1308 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1309 S = MCDisassembler::SoftFail; 1310 1311 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1312 return S; 1313 } 1314 1315 static const uint16_t SPRDecoderTable[] = { 1316 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1317 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1318 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1319 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1320 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1321 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1322 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1323 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1324 }; 1325 1326 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1327 uint64_t Address, const void *Decoder) { 1328 if (RegNo > 31) 1329 return MCDisassembler::Fail; 1330 1331 unsigned Register = SPRDecoderTable[RegNo]; 1332 Inst.addOperand(MCOperand::createReg(Register)); 1333 return MCDisassembler::Success; 1334 } 1335 1336 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1337 uint64_t Address, const void *Decoder) { 1338 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1339 } 1340 1341 static const uint16_t DPRDecoderTable[] = { 1342 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1343 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1344 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1345 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1346 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1347 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1348 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1349 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1350 }; 1351 1352 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1353 uint64_t Address, const void *Decoder) { 1354 const FeatureBitset &featureBits = 1355 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1356 1357 bool hasD32 = featureBits[ARM::FeatureD32]; 1358 1359 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1360 return MCDisassembler::Fail; 1361 1362 unsigned Register = DPRDecoderTable[RegNo]; 1363 Inst.addOperand(MCOperand::createReg(Register)); 1364 return MCDisassembler::Success; 1365 } 1366 1367 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1368 uint64_t Address, const void *Decoder) { 1369 if (RegNo > 7) 1370 return MCDisassembler::Fail; 1371 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1372 } 1373 1374 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1375 uint64_t Address, const void *Decoder) { 1376 if (RegNo > 15) 1377 return MCDisassembler::Fail; 1378 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1379 } 1380 1381 static DecodeStatus 1382 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1383 uint64_t Address, const void *Decoder) { 1384 if (RegNo > 15) 1385 return MCDisassembler::Fail; 1386 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1387 } 1388 1389 static const uint16_t QPRDecoderTable[] = { 1390 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1391 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1392 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1393 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1394 }; 1395 1396 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1397 uint64_t Address, const void *Decoder) { 1398 if (RegNo > 31 || (RegNo & 1) != 0) 1399 return MCDisassembler::Fail; 1400 RegNo >>= 1; 1401 1402 unsigned Register = QPRDecoderTable[RegNo]; 1403 Inst.addOperand(MCOperand::createReg(Register)); 1404 return MCDisassembler::Success; 1405 } 1406 1407 static const uint16_t DPairDecoderTable[] = { 1408 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1409 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1410 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1411 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1412 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1413 ARM::Q15 1414 }; 1415 1416 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1417 uint64_t Address, const void *Decoder) { 1418 if (RegNo > 30) 1419 return MCDisassembler::Fail; 1420 1421 unsigned Register = DPairDecoderTable[RegNo]; 1422 Inst.addOperand(MCOperand::createReg(Register)); 1423 return MCDisassembler::Success; 1424 } 1425 1426 static const uint16_t DPairSpacedDecoderTable[] = { 1427 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1428 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1429 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1430 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1431 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1432 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1433 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1434 ARM::D28_D30, ARM::D29_D31 1435 }; 1436 1437 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1438 unsigned RegNo, 1439 uint64_t Address, 1440 const void *Decoder) { 1441 if (RegNo > 29) 1442 return MCDisassembler::Fail; 1443 1444 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1445 Inst.addOperand(MCOperand::createReg(Register)); 1446 return MCDisassembler::Success; 1447 } 1448 1449 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1450 uint64_t Address, const void *Decoder) { 1451 DecodeStatus S = MCDisassembler::Success; 1452 if (Val == 0xF) return MCDisassembler::Fail; 1453 // AL predicate is not allowed on Thumb1 branches. 1454 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1455 return MCDisassembler::Fail; 1456 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1457 Check(S, MCDisassembler::SoftFail); 1458 Inst.addOperand(MCOperand::createImm(Val)); 1459 if (Val == ARMCC::AL) { 1460 Inst.addOperand(MCOperand::createReg(0)); 1461 } else 1462 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1463 return S; 1464 } 1465 1466 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1467 uint64_t Address, const void *Decoder) { 1468 if (Val) 1469 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1470 else 1471 Inst.addOperand(MCOperand::createReg(0)); 1472 return MCDisassembler::Success; 1473 } 1474 1475 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1476 uint64_t Address, const void *Decoder) { 1477 DecodeStatus S = MCDisassembler::Success; 1478 1479 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1480 unsigned type = fieldFromInstruction(Val, 5, 2); 1481 unsigned imm = fieldFromInstruction(Val, 7, 5); 1482 1483 // Register-immediate 1484 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1485 return MCDisassembler::Fail; 1486 1487 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1488 switch (type) { 1489 case 0: 1490 Shift = ARM_AM::lsl; 1491 break; 1492 case 1: 1493 Shift = ARM_AM::lsr; 1494 break; 1495 case 2: 1496 Shift = ARM_AM::asr; 1497 break; 1498 case 3: 1499 Shift = ARM_AM::ror; 1500 break; 1501 } 1502 1503 if (Shift == ARM_AM::ror && imm == 0) 1504 Shift = ARM_AM::rrx; 1505 1506 unsigned Op = Shift | (imm << 3); 1507 Inst.addOperand(MCOperand::createImm(Op)); 1508 1509 return S; 1510 } 1511 1512 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1513 uint64_t Address, const void *Decoder) { 1514 DecodeStatus S = MCDisassembler::Success; 1515 1516 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1517 unsigned type = fieldFromInstruction(Val, 5, 2); 1518 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1519 1520 // Register-register 1521 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1522 return MCDisassembler::Fail; 1523 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1524 return MCDisassembler::Fail; 1525 1526 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1527 switch (type) { 1528 case 0: 1529 Shift = ARM_AM::lsl; 1530 break; 1531 case 1: 1532 Shift = ARM_AM::lsr; 1533 break; 1534 case 2: 1535 Shift = ARM_AM::asr; 1536 break; 1537 case 3: 1538 Shift = ARM_AM::ror; 1539 break; 1540 } 1541 1542 Inst.addOperand(MCOperand::createImm(Shift)); 1543 1544 return S; 1545 } 1546 1547 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1548 uint64_t Address, const void *Decoder) { 1549 DecodeStatus S = MCDisassembler::Success; 1550 1551 bool NeedDisjointWriteback = false; 1552 unsigned WritebackReg = 0; 1553 bool CLRM = false; 1554 switch (Inst.getOpcode()) { 1555 default: 1556 break; 1557 case ARM::LDMIA_UPD: 1558 case ARM::LDMDB_UPD: 1559 case ARM::LDMIB_UPD: 1560 case ARM::LDMDA_UPD: 1561 case ARM::t2LDMIA_UPD: 1562 case ARM::t2LDMDB_UPD: 1563 case ARM::t2STMIA_UPD: 1564 case ARM::t2STMDB_UPD: 1565 NeedDisjointWriteback = true; 1566 WritebackReg = Inst.getOperand(0).getReg(); 1567 break; 1568 case ARM::t2CLRM: 1569 CLRM = true; 1570 break; 1571 } 1572 1573 // Empty register lists are not allowed. 1574 if (Val == 0) return MCDisassembler::Fail; 1575 for (unsigned i = 0; i < 16; ++i) { 1576 if (Val & (1 << i)) { 1577 if (CLRM) { 1578 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1579 return MCDisassembler::Fail; 1580 } 1581 } else { 1582 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1583 return MCDisassembler::Fail; 1584 // Writeback not allowed if Rn is in the target list. 1585 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1586 Check(S, MCDisassembler::SoftFail); 1587 } 1588 } 1589 } 1590 1591 return S; 1592 } 1593 1594 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1595 uint64_t Address, const void *Decoder) { 1596 DecodeStatus S = MCDisassembler::Success; 1597 1598 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1599 unsigned regs = fieldFromInstruction(Val, 0, 8); 1600 1601 // In case of unpredictable encoding, tweak the operands. 1602 if (regs == 0 || (Vd + regs) > 32) { 1603 regs = Vd + regs > 32 ? 32 - Vd : regs; 1604 regs = std::max( 1u, regs); 1605 S = MCDisassembler::SoftFail; 1606 } 1607 1608 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1609 return MCDisassembler::Fail; 1610 for (unsigned i = 0; i < (regs - 1); ++i) { 1611 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1612 return MCDisassembler::Fail; 1613 } 1614 1615 return S; 1616 } 1617 1618 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1619 uint64_t Address, const void *Decoder) { 1620 DecodeStatus S = MCDisassembler::Success; 1621 1622 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1623 unsigned regs = fieldFromInstruction(Val, 1, 7); 1624 1625 // In case of unpredictable encoding, tweak the operands. 1626 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1627 regs = Vd + regs > 32 ? 32 - Vd : regs; 1628 regs = std::max( 1u, regs); 1629 regs = std::min(16u, regs); 1630 S = MCDisassembler::SoftFail; 1631 } 1632 1633 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1634 return MCDisassembler::Fail; 1635 for (unsigned i = 0; i < (regs - 1); ++i) { 1636 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1637 return MCDisassembler::Fail; 1638 } 1639 1640 return S; 1641 } 1642 1643 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1644 uint64_t Address, const void *Decoder) { 1645 // This operand encodes a mask of contiguous zeros between a specified MSB 1646 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1647 // the mask of all bits LSB-and-lower, and then xor them to create 1648 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1649 // create the final mask. 1650 unsigned msb = fieldFromInstruction(Val, 5, 5); 1651 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1652 1653 DecodeStatus S = MCDisassembler::Success; 1654 if (lsb > msb) { 1655 Check(S, MCDisassembler::SoftFail); 1656 // The check above will cause the warning for the "potentially undefined 1657 // instruction encoding" but we can't build a bad MCOperand value here 1658 // with a lsb > msb or else printing the MCInst will cause a crash. 1659 lsb = msb; 1660 } 1661 1662 uint32_t msb_mask = 0xFFFFFFFF; 1663 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1664 uint32_t lsb_mask = (1U << lsb) - 1; 1665 1666 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1667 return S; 1668 } 1669 1670 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1671 uint64_t Address, const void *Decoder) { 1672 DecodeStatus S = MCDisassembler::Success; 1673 1674 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1675 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1676 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1677 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1678 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1679 unsigned U = fieldFromInstruction(Insn, 23, 1); 1680 const FeatureBitset &featureBits = 1681 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1682 1683 switch (Inst.getOpcode()) { 1684 case ARM::LDC_OFFSET: 1685 case ARM::LDC_PRE: 1686 case ARM::LDC_POST: 1687 case ARM::LDC_OPTION: 1688 case ARM::LDCL_OFFSET: 1689 case ARM::LDCL_PRE: 1690 case ARM::LDCL_POST: 1691 case ARM::LDCL_OPTION: 1692 case ARM::STC_OFFSET: 1693 case ARM::STC_PRE: 1694 case ARM::STC_POST: 1695 case ARM::STC_OPTION: 1696 case ARM::STCL_OFFSET: 1697 case ARM::STCL_PRE: 1698 case ARM::STCL_POST: 1699 case ARM::STCL_OPTION: 1700 case ARM::t2LDC_OFFSET: 1701 case ARM::t2LDC_PRE: 1702 case ARM::t2LDC_POST: 1703 case ARM::t2LDC_OPTION: 1704 case ARM::t2LDCL_OFFSET: 1705 case ARM::t2LDCL_PRE: 1706 case ARM::t2LDCL_POST: 1707 case ARM::t2LDCL_OPTION: 1708 case ARM::t2STC_OFFSET: 1709 case ARM::t2STC_PRE: 1710 case ARM::t2STC_POST: 1711 case ARM::t2STC_OPTION: 1712 case ARM::t2STCL_OFFSET: 1713 case ARM::t2STCL_PRE: 1714 case ARM::t2STCL_POST: 1715 case ARM::t2STCL_OPTION: 1716 case ARM::t2LDC2_OFFSET: 1717 case ARM::t2LDC2L_OFFSET: 1718 case ARM::t2LDC2_PRE: 1719 case ARM::t2LDC2L_PRE: 1720 case ARM::t2STC2_OFFSET: 1721 case ARM::t2STC2L_OFFSET: 1722 case ARM::t2STC2_PRE: 1723 case ARM::t2STC2L_PRE: 1724 case ARM::LDC2_OFFSET: 1725 case ARM::LDC2L_OFFSET: 1726 case ARM::LDC2_PRE: 1727 case ARM::LDC2L_PRE: 1728 case ARM::STC2_OFFSET: 1729 case ARM::STC2L_OFFSET: 1730 case ARM::STC2_PRE: 1731 case ARM::STC2L_PRE: 1732 case ARM::t2LDC2_OPTION: 1733 case ARM::t2STC2_OPTION: 1734 case ARM::t2LDC2_POST: 1735 case ARM::t2LDC2L_POST: 1736 case ARM::t2STC2_POST: 1737 case ARM::t2STC2L_POST: 1738 case ARM::LDC2_POST: 1739 case ARM::LDC2L_POST: 1740 case ARM::STC2_POST: 1741 case ARM::STC2L_POST: 1742 if (coproc == 0xA || coproc == 0xB || 1743 (featureBits[ARM::HasV8_1MMainlineOps] && 1744 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1745 coproc == 0xE || coproc == 0xF))) 1746 return MCDisassembler::Fail; 1747 break; 1748 default: 1749 break; 1750 } 1751 1752 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1753 return MCDisassembler::Fail; 1754 1755 Inst.addOperand(MCOperand::createImm(coproc)); 1756 Inst.addOperand(MCOperand::createImm(CRd)); 1757 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1758 return MCDisassembler::Fail; 1759 1760 switch (Inst.getOpcode()) { 1761 case ARM::t2LDC2_OFFSET: 1762 case ARM::t2LDC2L_OFFSET: 1763 case ARM::t2LDC2_PRE: 1764 case ARM::t2LDC2L_PRE: 1765 case ARM::t2STC2_OFFSET: 1766 case ARM::t2STC2L_OFFSET: 1767 case ARM::t2STC2_PRE: 1768 case ARM::t2STC2L_PRE: 1769 case ARM::LDC2_OFFSET: 1770 case ARM::LDC2L_OFFSET: 1771 case ARM::LDC2_PRE: 1772 case ARM::LDC2L_PRE: 1773 case ARM::STC2_OFFSET: 1774 case ARM::STC2L_OFFSET: 1775 case ARM::STC2_PRE: 1776 case ARM::STC2L_PRE: 1777 case ARM::t2LDC_OFFSET: 1778 case ARM::t2LDCL_OFFSET: 1779 case ARM::t2LDC_PRE: 1780 case ARM::t2LDCL_PRE: 1781 case ARM::t2STC_OFFSET: 1782 case ARM::t2STCL_OFFSET: 1783 case ARM::t2STC_PRE: 1784 case ARM::t2STCL_PRE: 1785 case ARM::LDC_OFFSET: 1786 case ARM::LDCL_OFFSET: 1787 case ARM::LDC_PRE: 1788 case ARM::LDCL_PRE: 1789 case ARM::STC_OFFSET: 1790 case ARM::STCL_OFFSET: 1791 case ARM::STC_PRE: 1792 case ARM::STCL_PRE: 1793 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1794 Inst.addOperand(MCOperand::createImm(imm)); 1795 break; 1796 case ARM::t2LDC2_POST: 1797 case ARM::t2LDC2L_POST: 1798 case ARM::t2STC2_POST: 1799 case ARM::t2STC2L_POST: 1800 case ARM::LDC2_POST: 1801 case ARM::LDC2L_POST: 1802 case ARM::STC2_POST: 1803 case ARM::STC2L_POST: 1804 case ARM::t2LDC_POST: 1805 case ARM::t2LDCL_POST: 1806 case ARM::t2STC_POST: 1807 case ARM::t2STCL_POST: 1808 case ARM::LDC_POST: 1809 case ARM::LDCL_POST: 1810 case ARM::STC_POST: 1811 case ARM::STCL_POST: 1812 imm |= U << 8; 1813 LLVM_FALLTHROUGH; 1814 default: 1815 // The 'option' variant doesn't encode 'U' in the immediate since 1816 // the immediate is unsigned [0,255]. 1817 Inst.addOperand(MCOperand::createImm(imm)); 1818 break; 1819 } 1820 1821 switch (Inst.getOpcode()) { 1822 case ARM::LDC_OFFSET: 1823 case ARM::LDC_PRE: 1824 case ARM::LDC_POST: 1825 case ARM::LDC_OPTION: 1826 case ARM::LDCL_OFFSET: 1827 case ARM::LDCL_PRE: 1828 case ARM::LDCL_POST: 1829 case ARM::LDCL_OPTION: 1830 case ARM::STC_OFFSET: 1831 case ARM::STC_PRE: 1832 case ARM::STC_POST: 1833 case ARM::STC_OPTION: 1834 case ARM::STCL_OFFSET: 1835 case ARM::STCL_PRE: 1836 case ARM::STCL_POST: 1837 case ARM::STCL_OPTION: 1838 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1839 return MCDisassembler::Fail; 1840 break; 1841 default: 1842 break; 1843 } 1844 1845 return S; 1846 } 1847 1848 static DecodeStatus 1849 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1850 uint64_t Address, const void *Decoder) { 1851 DecodeStatus S = MCDisassembler::Success; 1852 1853 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1854 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1855 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1856 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1857 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1858 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1859 unsigned P = fieldFromInstruction(Insn, 24, 1); 1860 unsigned W = fieldFromInstruction(Insn, 21, 1); 1861 1862 // On stores, the writeback operand precedes Rt. 1863 switch (Inst.getOpcode()) { 1864 case ARM::STR_POST_IMM: 1865 case ARM::STR_POST_REG: 1866 case ARM::STRB_POST_IMM: 1867 case ARM::STRB_POST_REG: 1868 case ARM::STRT_POST_REG: 1869 case ARM::STRT_POST_IMM: 1870 case ARM::STRBT_POST_REG: 1871 case ARM::STRBT_POST_IMM: 1872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1873 return MCDisassembler::Fail; 1874 break; 1875 default: 1876 break; 1877 } 1878 1879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1880 return MCDisassembler::Fail; 1881 1882 // On loads, the writeback operand comes after Rt. 1883 switch (Inst.getOpcode()) { 1884 case ARM::LDR_POST_IMM: 1885 case ARM::LDR_POST_REG: 1886 case ARM::LDRB_POST_IMM: 1887 case ARM::LDRB_POST_REG: 1888 case ARM::LDRBT_POST_REG: 1889 case ARM::LDRBT_POST_IMM: 1890 case ARM::LDRT_POST_REG: 1891 case ARM::LDRT_POST_IMM: 1892 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1893 return MCDisassembler::Fail; 1894 break; 1895 default: 1896 break; 1897 } 1898 1899 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1900 return MCDisassembler::Fail; 1901 1902 ARM_AM::AddrOpc Op = ARM_AM::add; 1903 if (!fieldFromInstruction(Insn, 23, 1)) 1904 Op = ARM_AM::sub; 1905 1906 bool writeback = (P == 0) || (W == 1); 1907 unsigned idx_mode = 0; 1908 if (P && writeback) 1909 idx_mode = ARMII::IndexModePre; 1910 else if (!P && writeback) 1911 idx_mode = ARMII::IndexModePost; 1912 1913 if (writeback && (Rn == 15 || Rn == Rt)) 1914 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1915 1916 if (reg) { 1917 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1918 return MCDisassembler::Fail; 1919 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1920 switch( fieldFromInstruction(Insn, 5, 2)) { 1921 case 0: 1922 Opc = ARM_AM::lsl; 1923 break; 1924 case 1: 1925 Opc = ARM_AM::lsr; 1926 break; 1927 case 2: 1928 Opc = ARM_AM::asr; 1929 break; 1930 case 3: 1931 Opc = ARM_AM::ror; 1932 break; 1933 default: 1934 return MCDisassembler::Fail; 1935 } 1936 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1937 if (Opc == ARM_AM::ror && amt == 0) 1938 Opc = ARM_AM::rrx; 1939 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1940 1941 Inst.addOperand(MCOperand::createImm(imm)); 1942 } else { 1943 Inst.addOperand(MCOperand::createReg(0)); 1944 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1945 Inst.addOperand(MCOperand::createImm(tmp)); 1946 } 1947 1948 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1949 return MCDisassembler::Fail; 1950 1951 return S; 1952 } 1953 1954 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1955 uint64_t Address, const void *Decoder) { 1956 DecodeStatus S = MCDisassembler::Success; 1957 1958 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1959 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1960 unsigned type = fieldFromInstruction(Val, 5, 2); 1961 unsigned imm = fieldFromInstruction(Val, 7, 5); 1962 unsigned U = fieldFromInstruction(Val, 12, 1); 1963 1964 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1965 switch (type) { 1966 case 0: 1967 ShOp = ARM_AM::lsl; 1968 break; 1969 case 1: 1970 ShOp = ARM_AM::lsr; 1971 break; 1972 case 2: 1973 ShOp = ARM_AM::asr; 1974 break; 1975 case 3: 1976 ShOp = ARM_AM::ror; 1977 break; 1978 } 1979 1980 if (ShOp == ARM_AM::ror && imm == 0) 1981 ShOp = ARM_AM::rrx; 1982 1983 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1984 return MCDisassembler::Fail; 1985 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1986 return MCDisassembler::Fail; 1987 unsigned shift; 1988 if (U) 1989 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1990 else 1991 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1992 Inst.addOperand(MCOperand::createImm(shift)); 1993 1994 return S; 1995 } 1996 1997 static DecodeStatus 1998 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1999 uint64_t Address, const void *Decoder) { 2000 DecodeStatus S = MCDisassembler::Success; 2001 2002 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2003 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2004 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2005 unsigned type = fieldFromInstruction(Insn, 22, 1); 2006 unsigned imm = fieldFromInstruction(Insn, 8, 4); 2007 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2008 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2009 unsigned W = fieldFromInstruction(Insn, 21, 1); 2010 unsigned P = fieldFromInstruction(Insn, 24, 1); 2011 unsigned Rt2 = Rt + 1; 2012 2013 bool writeback = (W == 1) | (P == 0); 2014 2015 // For {LD,ST}RD, Rt must be even, else undefined. 2016 switch (Inst.getOpcode()) { 2017 case ARM::STRD: 2018 case ARM::STRD_PRE: 2019 case ARM::STRD_POST: 2020 case ARM::LDRD: 2021 case ARM::LDRD_PRE: 2022 case ARM::LDRD_POST: 2023 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2024 break; 2025 default: 2026 break; 2027 } 2028 switch (Inst.getOpcode()) { 2029 case ARM::STRD: 2030 case ARM::STRD_PRE: 2031 case ARM::STRD_POST: 2032 if (P == 0 && W == 1) 2033 S = MCDisassembler::SoftFail; 2034 2035 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2036 S = MCDisassembler::SoftFail; 2037 if (type && Rm == 15) 2038 S = MCDisassembler::SoftFail; 2039 if (Rt2 == 15) 2040 S = MCDisassembler::SoftFail; 2041 if (!type && fieldFromInstruction(Insn, 8, 4)) 2042 S = MCDisassembler::SoftFail; 2043 break; 2044 case ARM::STRH: 2045 case ARM::STRH_PRE: 2046 case ARM::STRH_POST: 2047 if (Rt == 15) 2048 S = MCDisassembler::SoftFail; 2049 if (writeback && (Rn == 15 || Rn == Rt)) 2050 S = MCDisassembler::SoftFail; 2051 if (!type && Rm == 15) 2052 S = MCDisassembler::SoftFail; 2053 break; 2054 case ARM::LDRD: 2055 case ARM::LDRD_PRE: 2056 case ARM::LDRD_POST: 2057 if (type && Rn == 15) { 2058 if (Rt2 == 15) 2059 S = MCDisassembler::SoftFail; 2060 break; 2061 } 2062 if (P == 0 && W == 1) 2063 S = MCDisassembler::SoftFail; 2064 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2065 S = MCDisassembler::SoftFail; 2066 if (!type && writeback && Rn == 15) 2067 S = MCDisassembler::SoftFail; 2068 if (writeback && (Rn == Rt || Rn == Rt2)) 2069 S = MCDisassembler::SoftFail; 2070 break; 2071 case ARM::LDRH: 2072 case ARM::LDRH_PRE: 2073 case ARM::LDRH_POST: 2074 if (type && Rn == 15) { 2075 if (Rt == 15) 2076 S = MCDisassembler::SoftFail; 2077 break; 2078 } 2079 if (Rt == 15) 2080 S = MCDisassembler::SoftFail; 2081 if (!type && Rm == 15) 2082 S = MCDisassembler::SoftFail; 2083 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2084 S = MCDisassembler::SoftFail; 2085 break; 2086 case ARM::LDRSH: 2087 case ARM::LDRSH_PRE: 2088 case ARM::LDRSH_POST: 2089 case ARM::LDRSB: 2090 case ARM::LDRSB_PRE: 2091 case ARM::LDRSB_POST: 2092 if (type && Rn == 15) { 2093 if (Rt == 15) 2094 S = MCDisassembler::SoftFail; 2095 break; 2096 } 2097 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2098 S = MCDisassembler::SoftFail; 2099 if (!type && (Rt == 15 || Rm == 15)) 2100 S = MCDisassembler::SoftFail; 2101 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2102 S = MCDisassembler::SoftFail; 2103 break; 2104 default: 2105 break; 2106 } 2107 2108 if (writeback) { // Writeback 2109 if (P) 2110 U |= ARMII::IndexModePre << 9; 2111 else 2112 U |= ARMII::IndexModePost << 9; 2113 2114 // On stores, the writeback operand precedes Rt. 2115 switch (Inst.getOpcode()) { 2116 case ARM::STRD: 2117 case ARM::STRD_PRE: 2118 case ARM::STRD_POST: 2119 case ARM::STRH: 2120 case ARM::STRH_PRE: 2121 case ARM::STRH_POST: 2122 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2123 return MCDisassembler::Fail; 2124 break; 2125 default: 2126 break; 2127 } 2128 } 2129 2130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2131 return MCDisassembler::Fail; 2132 switch (Inst.getOpcode()) { 2133 case ARM::STRD: 2134 case ARM::STRD_PRE: 2135 case ARM::STRD_POST: 2136 case ARM::LDRD: 2137 case ARM::LDRD_PRE: 2138 case ARM::LDRD_POST: 2139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2140 return MCDisassembler::Fail; 2141 break; 2142 default: 2143 break; 2144 } 2145 2146 if (writeback) { 2147 // On loads, the writeback operand comes after Rt. 2148 switch (Inst.getOpcode()) { 2149 case ARM::LDRD: 2150 case ARM::LDRD_PRE: 2151 case ARM::LDRD_POST: 2152 case ARM::LDRH: 2153 case ARM::LDRH_PRE: 2154 case ARM::LDRH_POST: 2155 case ARM::LDRSH: 2156 case ARM::LDRSH_PRE: 2157 case ARM::LDRSH_POST: 2158 case ARM::LDRSB: 2159 case ARM::LDRSB_PRE: 2160 case ARM::LDRSB_POST: 2161 case ARM::LDRHTr: 2162 case ARM::LDRSBTr: 2163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2164 return MCDisassembler::Fail; 2165 break; 2166 default: 2167 break; 2168 } 2169 } 2170 2171 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2172 return MCDisassembler::Fail; 2173 2174 if (type) { 2175 Inst.addOperand(MCOperand::createReg(0)); 2176 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2177 } else { 2178 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2179 return MCDisassembler::Fail; 2180 Inst.addOperand(MCOperand::createImm(U)); 2181 } 2182 2183 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2184 return MCDisassembler::Fail; 2185 2186 return S; 2187 } 2188 2189 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2190 uint64_t Address, const void *Decoder) { 2191 DecodeStatus S = MCDisassembler::Success; 2192 2193 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2194 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2195 2196 switch (mode) { 2197 case 0: 2198 mode = ARM_AM::da; 2199 break; 2200 case 1: 2201 mode = ARM_AM::ia; 2202 break; 2203 case 2: 2204 mode = ARM_AM::db; 2205 break; 2206 case 3: 2207 mode = ARM_AM::ib; 2208 break; 2209 } 2210 2211 Inst.addOperand(MCOperand::createImm(mode)); 2212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2213 return MCDisassembler::Fail; 2214 2215 return S; 2216 } 2217 2218 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2219 uint64_t Address, const void *Decoder) { 2220 DecodeStatus S = MCDisassembler::Success; 2221 2222 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2223 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2224 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2225 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2226 2227 if (pred == 0xF) 2228 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2229 2230 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2231 return MCDisassembler::Fail; 2232 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2233 return MCDisassembler::Fail; 2234 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2235 return MCDisassembler::Fail; 2236 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2237 return MCDisassembler::Fail; 2238 return S; 2239 } 2240 2241 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2242 unsigned Insn, 2243 uint64_t Address, const void *Decoder) { 2244 DecodeStatus S = MCDisassembler::Success; 2245 2246 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2247 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2248 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2249 2250 if (pred == 0xF) { 2251 // Ambiguous with RFE and SRS 2252 switch (Inst.getOpcode()) { 2253 case ARM::LDMDA: 2254 Inst.setOpcode(ARM::RFEDA); 2255 break; 2256 case ARM::LDMDA_UPD: 2257 Inst.setOpcode(ARM::RFEDA_UPD); 2258 break; 2259 case ARM::LDMDB: 2260 Inst.setOpcode(ARM::RFEDB); 2261 break; 2262 case ARM::LDMDB_UPD: 2263 Inst.setOpcode(ARM::RFEDB_UPD); 2264 break; 2265 case ARM::LDMIA: 2266 Inst.setOpcode(ARM::RFEIA); 2267 break; 2268 case ARM::LDMIA_UPD: 2269 Inst.setOpcode(ARM::RFEIA_UPD); 2270 break; 2271 case ARM::LDMIB: 2272 Inst.setOpcode(ARM::RFEIB); 2273 break; 2274 case ARM::LDMIB_UPD: 2275 Inst.setOpcode(ARM::RFEIB_UPD); 2276 break; 2277 case ARM::STMDA: 2278 Inst.setOpcode(ARM::SRSDA); 2279 break; 2280 case ARM::STMDA_UPD: 2281 Inst.setOpcode(ARM::SRSDA_UPD); 2282 break; 2283 case ARM::STMDB: 2284 Inst.setOpcode(ARM::SRSDB); 2285 break; 2286 case ARM::STMDB_UPD: 2287 Inst.setOpcode(ARM::SRSDB_UPD); 2288 break; 2289 case ARM::STMIA: 2290 Inst.setOpcode(ARM::SRSIA); 2291 break; 2292 case ARM::STMIA_UPD: 2293 Inst.setOpcode(ARM::SRSIA_UPD); 2294 break; 2295 case ARM::STMIB: 2296 Inst.setOpcode(ARM::SRSIB); 2297 break; 2298 case ARM::STMIB_UPD: 2299 Inst.setOpcode(ARM::SRSIB_UPD); 2300 break; 2301 default: 2302 return MCDisassembler::Fail; 2303 } 2304 2305 // For stores (which become SRS's, the only operand is the mode. 2306 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2307 // Check SRS encoding constraints 2308 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2309 fieldFromInstruction(Insn, 20, 1) == 0)) 2310 return MCDisassembler::Fail; 2311 2312 Inst.addOperand( 2313 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2314 return S; 2315 } 2316 2317 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2318 } 2319 2320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2321 return MCDisassembler::Fail; 2322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2323 return MCDisassembler::Fail; // Tied 2324 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2325 return MCDisassembler::Fail; 2326 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2327 return MCDisassembler::Fail; 2328 2329 return S; 2330 } 2331 2332 // Check for UNPREDICTABLE predicated ESB instruction 2333 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2334 uint64_t Address, const void *Decoder) { 2335 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2336 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2337 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2338 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2339 2340 DecodeStatus S = MCDisassembler::Success; 2341 2342 Inst.addOperand(MCOperand::createImm(imm8)); 2343 2344 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2345 return MCDisassembler::Fail; 2346 2347 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2348 // so all predicates should be allowed. 2349 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2350 S = MCDisassembler::SoftFail; 2351 2352 return S; 2353 } 2354 2355 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2356 uint64_t Address, const void *Decoder) { 2357 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2358 unsigned M = fieldFromInstruction(Insn, 17, 1); 2359 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2360 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2361 2362 DecodeStatus S = MCDisassembler::Success; 2363 2364 // This decoder is called from multiple location that do not check 2365 // the full encoding is valid before they do. 2366 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2367 fieldFromInstruction(Insn, 16, 1) != 0 || 2368 fieldFromInstruction(Insn, 20, 8) != 0x10) 2369 return MCDisassembler::Fail; 2370 2371 // imod == '01' --> UNPREDICTABLE 2372 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2373 // return failure here. The '01' imod value is unprintable, so there's 2374 // nothing useful we could do even if we returned UNPREDICTABLE. 2375 2376 if (imod == 1) return MCDisassembler::Fail; 2377 2378 if (imod && M) { 2379 Inst.setOpcode(ARM::CPS3p); 2380 Inst.addOperand(MCOperand::createImm(imod)); 2381 Inst.addOperand(MCOperand::createImm(iflags)); 2382 Inst.addOperand(MCOperand::createImm(mode)); 2383 } else if (imod && !M) { 2384 Inst.setOpcode(ARM::CPS2p); 2385 Inst.addOperand(MCOperand::createImm(imod)); 2386 Inst.addOperand(MCOperand::createImm(iflags)); 2387 if (mode) S = MCDisassembler::SoftFail; 2388 } else if (!imod && M) { 2389 Inst.setOpcode(ARM::CPS1p); 2390 Inst.addOperand(MCOperand::createImm(mode)); 2391 if (iflags) S = MCDisassembler::SoftFail; 2392 } else { 2393 // imod == '00' && M == '0' --> UNPREDICTABLE 2394 Inst.setOpcode(ARM::CPS1p); 2395 Inst.addOperand(MCOperand::createImm(mode)); 2396 S = MCDisassembler::SoftFail; 2397 } 2398 2399 return S; 2400 } 2401 2402 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2403 uint64_t Address, const void *Decoder) { 2404 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2405 unsigned M = fieldFromInstruction(Insn, 8, 1); 2406 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2407 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2408 2409 DecodeStatus S = MCDisassembler::Success; 2410 2411 // imod == '01' --> UNPREDICTABLE 2412 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2413 // return failure here. The '01' imod value is unprintable, so there's 2414 // nothing useful we could do even if we returned UNPREDICTABLE. 2415 2416 if (imod == 1) return MCDisassembler::Fail; 2417 2418 if (imod && M) { 2419 Inst.setOpcode(ARM::t2CPS3p); 2420 Inst.addOperand(MCOperand::createImm(imod)); 2421 Inst.addOperand(MCOperand::createImm(iflags)); 2422 Inst.addOperand(MCOperand::createImm(mode)); 2423 } else if (imod && !M) { 2424 Inst.setOpcode(ARM::t2CPS2p); 2425 Inst.addOperand(MCOperand::createImm(imod)); 2426 Inst.addOperand(MCOperand::createImm(iflags)); 2427 if (mode) S = MCDisassembler::SoftFail; 2428 } else if (!imod && M) { 2429 Inst.setOpcode(ARM::t2CPS1p); 2430 Inst.addOperand(MCOperand::createImm(mode)); 2431 if (iflags) S = MCDisassembler::SoftFail; 2432 } else { 2433 // imod == '00' && M == '0' --> this is a HINT instruction 2434 int imm = fieldFromInstruction(Insn, 0, 8); 2435 // HINT are defined only for immediate in [0..4] 2436 if(imm > 4) return MCDisassembler::Fail; 2437 Inst.setOpcode(ARM::t2HINT); 2438 Inst.addOperand(MCOperand::createImm(imm)); 2439 } 2440 2441 return S; 2442 } 2443 2444 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2445 uint64_t Address, const void *Decoder) { 2446 DecodeStatus S = MCDisassembler::Success; 2447 2448 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2449 unsigned imm = 0; 2450 2451 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2452 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2453 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2454 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2455 2456 if (Inst.getOpcode() == ARM::t2MOVTi16) 2457 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2458 return MCDisassembler::Fail; 2459 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2460 return MCDisassembler::Fail; 2461 2462 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2463 Inst.addOperand(MCOperand::createImm(imm)); 2464 2465 return S; 2466 } 2467 2468 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2469 uint64_t Address, const void *Decoder) { 2470 DecodeStatus S = MCDisassembler::Success; 2471 2472 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2473 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2474 unsigned imm = 0; 2475 2476 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2477 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2478 2479 if (Inst.getOpcode() == ARM::MOVTi16) 2480 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2481 return MCDisassembler::Fail; 2482 2483 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2484 return MCDisassembler::Fail; 2485 2486 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2487 Inst.addOperand(MCOperand::createImm(imm)); 2488 2489 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2490 return MCDisassembler::Fail; 2491 2492 return S; 2493 } 2494 2495 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2496 uint64_t Address, const void *Decoder) { 2497 DecodeStatus S = MCDisassembler::Success; 2498 2499 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2500 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2501 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2502 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2503 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2504 2505 if (pred == 0xF) 2506 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2507 2508 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2509 return MCDisassembler::Fail; 2510 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2511 return MCDisassembler::Fail; 2512 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2513 return MCDisassembler::Fail; 2514 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2515 return MCDisassembler::Fail; 2516 2517 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2518 return MCDisassembler::Fail; 2519 2520 return S; 2521 } 2522 2523 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2524 uint64_t Address, const void *Decoder) { 2525 DecodeStatus S = MCDisassembler::Success; 2526 2527 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2528 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2529 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2530 2531 if (Pred == 0xF) 2532 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2533 2534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2535 return MCDisassembler::Fail; 2536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2537 return MCDisassembler::Fail; 2538 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2539 return MCDisassembler::Fail; 2540 2541 return S; 2542 } 2543 2544 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2545 uint64_t Address, const void *Decoder) { 2546 DecodeStatus S = MCDisassembler::Success; 2547 2548 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2549 2550 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2551 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2552 2553 if (!FeatureBits[ARM::HasV8_1aOps] || 2554 !FeatureBits[ARM::HasV8Ops]) 2555 return MCDisassembler::Fail; 2556 2557 // Decoder can be called from DecodeTST, which does not check the full 2558 // encoding is valid. 2559 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2560 fieldFromInstruction(Insn, 4,4) != 0) 2561 return MCDisassembler::Fail; 2562 if (fieldFromInstruction(Insn, 10,10) != 0 || 2563 fieldFromInstruction(Insn, 0,4) != 0) 2564 S = MCDisassembler::SoftFail; 2565 2566 Inst.setOpcode(ARM::SETPAN); 2567 Inst.addOperand(MCOperand::createImm(Imm)); 2568 2569 return S; 2570 } 2571 2572 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2573 uint64_t Address, const void *Decoder) { 2574 DecodeStatus S = MCDisassembler::Success; 2575 2576 unsigned add = fieldFromInstruction(Val, 12, 1); 2577 unsigned imm = fieldFromInstruction(Val, 0, 12); 2578 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2579 2580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2581 return MCDisassembler::Fail; 2582 2583 if (!add) imm *= -1; 2584 if (imm == 0 && !add) imm = INT32_MIN; 2585 Inst.addOperand(MCOperand::createImm(imm)); 2586 if (Rn == 15) 2587 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2588 2589 return S; 2590 } 2591 2592 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2593 uint64_t Address, const void *Decoder) { 2594 DecodeStatus S = MCDisassembler::Success; 2595 2596 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2597 // U == 1 to add imm, 0 to subtract it. 2598 unsigned U = fieldFromInstruction(Val, 8, 1); 2599 unsigned imm = fieldFromInstruction(Val, 0, 8); 2600 2601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2602 return MCDisassembler::Fail; 2603 2604 if (U) 2605 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2606 else 2607 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2608 2609 return S; 2610 } 2611 2612 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2613 uint64_t Address, const void *Decoder) { 2614 DecodeStatus S = MCDisassembler::Success; 2615 2616 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2617 // U == 1 to add imm, 0 to subtract it. 2618 unsigned U = fieldFromInstruction(Val, 8, 1); 2619 unsigned imm = fieldFromInstruction(Val, 0, 8); 2620 2621 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2622 return MCDisassembler::Fail; 2623 2624 if (U) 2625 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2626 else 2627 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2628 2629 return S; 2630 } 2631 2632 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2633 uint64_t Address, const void *Decoder) { 2634 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2635 } 2636 2637 static DecodeStatus 2638 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2639 uint64_t Address, const void *Decoder) { 2640 DecodeStatus Status = MCDisassembler::Success; 2641 2642 // Note the J1 and J2 values are from the encoded instruction. So here 2643 // change them to I1 and I2 values via as documented: 2644 // I1 = NOT(J1 EOR S); 2645 // I2 = NOT(J2 EOR S); 2646 // and build the imm32 with one trailing zero as documented: 2647 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2648 unsigned S = fieldFromInstruction(Insn, 26, 1); 2649 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2650 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2651 unsigned I1 = !(J1 ^ S); 2652 unsigned I2 = !(J2 ^ S); 2653 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2654 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2655 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2656 int imm32 = SignExtend32<25>(tmp << 1); 2657 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2658 true, 4, Inst, Decoder)) 2659 Inst.addOperand(MCOperand::createImm(imm32)); 2660 2661 return Status; 2662 } 2663 2664 static DecodeStatus 2665 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2666 uint64_t Address, const void *Decoder) { 2667 DecodeStatus S = MCDisassembler::Success; 2668 2669 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2670 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2671 2672 if (pred == 0xF) { 2673 Inst.setOpcode(ARM::BLXi); 2674 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2675 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2676 true, 4, Inst, Decoder)) 2677 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2678 return S; 2679 } 2680 2681 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2682 true, 4, Inst, Decoder)) 2683 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2684 2685 // We already have BL_pred for BL w/ predicate, no need to add addition 2686 // predicate opreands for BL 2687 if (Inst.getOpcode() != ARM::BL) 2688 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2689 return MCDisassembler::Fail; 2690 2691 return S; 2692 } 2693 2694 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2695 uint64_t Address, const void *Decoder) { 2696 DecodeStatus S = MCDisassembler::Success; 2697 2698 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2699 unsigned align = fieldFromInstruction(Val, 4, 2); 2700 2701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2702 return MCDisassembler::Fail; 2703 if (!align) 2704 Inst.addOperand(MCOperand::createImm(0)); 2705 else 2706 Inst.addOperand(MCOperand::createImm(4 << align)); 2707 2708 return S; 2709 } 2710 2711 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2712 uint64_t Address, const void *Decoder) { 2713 DecodeStatus S = MCDisassembler::Success; 2714 2715 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2716 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2717 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2718 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2719 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2720 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2721 2722 // First output register 2723 switch (Inst.getOpcode()) { 2724 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2725 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2726 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2727 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2728 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2729 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2730 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2731 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2732 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2733 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2734 return MCDisassembler::Fail; 2735 break; 2736 case ARM::VLD2b16: 2737 case ARM::VLD2b32: 2738 case ARM::VLD2b8: 2739 case ARM::VLD2b16wb_fixed: 2740 case ARM::VLD2b16wb_register: 2741 case ARM::VLD2b32wb_fixed: 2742 case ARM::VLD2b32wb_register: 2743 case ARM::VLD2b8wb_fixed: 2744 case ARM::VLD2b8wb_register: 2745 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2746 return MCDisassembler::Fail; 2747 break; 2748 default: 2749 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2750 return MCDisassembler::Fail; 2751 } 2752 2753 // Second output register 2754 switch (Inst.getOpcode()) { 2755 case ARM::VLD3d8: 2756 case ARM::VLD3d16: 2757 case ARM::VLD3d32: 2758 case ARM::VLD3d8_UPD: 2759 case ARM::VLD3d16_UPD: 2760 case ARM::VLD3d32_UPD: 2761 case ARM::VLD4d8: 2762 case ARM::VLD4d16: 2763 case ARM::VLD4d32: 2764 case ARM::VLD4d8_UPD: 2765 case ARM::VLD4d16_UPD: 2766 case ARM::VLD4d32_UPD: 2767 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2768 return MCDisassembler::Fail; 2769 break; 2770 case ARM::VLD3q8: 2771 case ARM::VLD3q16: 2772 case ARM::VLD3q32: 2773 case ARM::VLD3q8_UPD: 2774 case ARM::VLD3q16_UPD: 2775 case ARM::VLD3q32_UPD: 2776 case ARM::VLD4q8: 2777 case ARM::VLD4q16: 2778 case ARM::VLD4q32: 2779 case ARM::VLD4q8_UPD: 2780 case ARM::VLD4q16_UPD: 2781 case ARM::VLD4q32_UPD: 2782 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2783 return MCDisassembler::Fail; 2784 break; 2785 default: 2786 break; 2787 } 2788 2789 // Third output register 2790 switch(Inst.getOpcode()) { 2791 case ARM::VLD3d8: 2792 case ARM::VLD3d16: 2793 case ARM::VLD3d32: 2794 case ARM::VLD3d8_UPD: 2795 case ARM::VLD3d16_UPD: 2796 case ARM::VLD3d32_UPD: 2797 case ARM::VLD4d8: 2798 case ARM::VLD4d16: 2799 case ARM::VLD4d32: 2800 case ARM::VLD4d8_UPD: 2801 case ARM::VLD4d16_UPD: 2802 case ARM::VLD4d32_UPD: 2803 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2804 return MCDisassembler::Fail; 2805 break; 2806 case ARM::VLD3q8: 2807 case ARM::VLD3q16: 2808 case ARM::VLD3q32: 2809 case ARM::VLD3q8_UPD: 2810 case ARM::VLD3q16_UPD: 2811 case ARM::VLD3q32_UPD: 2812 case ARM::VLD4q8: 2813 case ARM::VLD4q16: 2814 case ARM::VLD4q32: 2815 case ARM::VLD4q8_UPD: 2816 case ARM::VLD4q16_UPD: 2817 case ARM::VLD4q32_UPD: 2818 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2819 return MCDisassembler::Fail; 2820 break; 2821 default: 2822 break; 2823 } 2824 2825 // Fourth output register 2826 switch (Inst.getOpcode()) { 2827 case ARM::VLD4d8: 2828 case ARM::VLD4d16: 2829 case ARM::VLD4d32: 2830 case ARM::VLD4d8_UPD: 2831 case ARM::VLD4d16_UPD: 2832 case ARM::VLD4d32_UPD: 2833 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 break; 2836 case ARM::VLD4q8: 2837 case ARM::VLD4q16: 2838 case ARM::VLD4q32: 2839 case ARM::VLD4q8_UPD: 2840 case ARM::VLD4q16_UPD: 2841 case ARM::VLD4q32_UPD: 2842 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2843 return MCDisassembler::Fail; 2844 break; 2845 default: 2846 break; 2847 } 2848 2849 // Writeback operand 2850 switch (Inst.getOpcode()) { 2851 case ARM::VLD1d8wb_fixed: 2852 case ARM::VLD1d16wb_fixed: 2853 case ARM::VLD1d32wb_fixed: 2854 case ARM::VLD1d64wb_fixed: 2855 case ARM::VLD1d8wb_register: 2856 case ARM::VLD1d16wb_register: 2857 case ARM::VLD1d32wb_register: 2858 case ARM::VLD1d64wb_register: 2859 case ARM::VLD1q8wb_fixed: 2860 case ARM::VLD1q16wb_fixed: 2861 case ARM::VLD1q32wb_fixed: 2862 case ARM::VLD1q64wb_fixed: 2863 case ARM::VLD1q8wb_register: 2864 case ARM::VLD1q16wb_register: 2865 case ARM::VLD1q32wb_register: 2866 case ARM::VLD1q64wb_register: 2867 case ARM::VLD1d8Twb_fixed: 2868 case ARM::VLD1d8Twb_register: 2869 case ARM::VLD1d16Twb_fixed: 2870 case ARM::VLD1d16Twb_register: 2871 case ARM::VLD1d32Twb_fixed: 2872 case ARM::VLD1d32Twb_register: 2873 case ARM::VLD1d64Twb_fixed: 2874 case ARM::VLD1d64Twb_register: 2875 case ARM::VLD1d8Qwb_fixed: 2876 case ARM::VLD1d8Qwb_register: 2877 case ARM::VLD1d16Qwb_fixed: 2878 case ARM::VLD1d16Qwb_register: 2879 case ARM::VLD1d32Qwb_fixed: 2880 case ARM::VLD1d32Qwb_register: 2881 case ARM::VLD1d64Qwb_fixed: 2882 case ARM::VLD1d64Qwb_register: 2883 case ARM::VLD2d8wb_fixed: 2884 case ARM::VLD2d16wb_fixed: 2885 case ARM::VLD2d32wb_fixed: 2886 case ARM::VLD2q8wb_fixed: 2887 case ARM::VLD2q16wb_fixed: 2888 case ARM::VLD2q32wb_fixed: 2889 case ARM::VLD2d8wb_register: 2890 case ARM::VLD2d16wb_register: 2891 case ARM::VLD2d32wb_register: 2892 case ARM::VLD2q8wb_register: 2893 case ARM::VLD2q16wb_register: 2894 case ARM::VLD2q32wb_register: 2895 case ARM::VLD2b8wb_fixed: 2896 case ARM::VLD2b16wb_fixed: 2897 case ARM::VLD2b32wb_fixed: 2898 case ARM::VLD2b8wb_register: 2899 case ARM::VLD2b16wb_register: 2900 case ARM::VLD2b32wb_register: 2901 Inst.addOperand(MCOperand::createImm(0)); 2902 break; 2903 case ARM::VLD3d8_UPD: 2904 case ARM::VLD3d16_UPD: 2905 case ARM::VLD3d32_UPD: 2906 case ARM::VLD3q8_UPD: 2907 case ARM::VLD3q16_UPD: 2908 case ARM::VLD3q32_UPD: 2909 case ARM::VLD4d8_UPD: 2910 case ARM::VLD4d16_UPD: 2911 case ARM::VLD4d32_UPD: 2912 case ARM::VLD4q8_UPD: 2913 case ARM::VLD4q16_UPD: 2914 case ARM::VLD4q32_UPD: 2915 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2916 return MCDisassembler::Fail; 2917 break; 2918 default: 2919 break; 2920 } 2921 2922 // AddrMode6 Base (register+alignment) 2923 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2924 return MCDisassembler::Fail; 2925 2926 // AddrMode6 Offset (register) 2927 switch (Inst.getOpcode()) { 2928 default: 2929 // The below have been updated to have explicit am6offset split 2930 // between fixed and register offset. For those instructions not 2931 // yet updated, we need to add an additional reg0 operand for the 2932 // fixed variant. 2933 // 2934 // The fixed offset encodes as Rm == 0xd, so we check for that. 2935 if (Rm == 0xd) { 2936 Inst.addOperand(MCOperand::createReg(0)); 2937 break; 2938 } 2939 // Fall through to handle the register offset variant. 2940 LLVM_FALLTHROUGH; 2941 case ARM::VLD1d8wb_fixed: 2942 case ARM::VLD1d16wb_fixed: 2943 case ARM::VLD1d32wb_fixed: 2944 case ARM::VLD1d64wb_fixed: 2945 case ARM::VLD1d8Twb_fixed: 2946 case ARM::VLD1d16Twb_fixed: 2947 case ARM::VLD1d32Twb_fixed: 2948 case ARM::VLD1d64Twb_fixed: 2949 case ARM::VLD1d8Qwb_fixed: 2950 case ARM::VLD1d16Qwb_fixed: 2951 case ARM::VLD1d32Qwb_fixed: 2952 case ARM::VLD1d64Qwb_fixed: 2953 case ARM::VLD1d8wb_register: 2954 case ARM::VLD1d16wb_register: 2955 case ARM::VLD1d32wb_register: 2956 case ARM::VLD1d64wb_register: 2957 case ARM::VLD1q8wb_fixed: 2958 case ARM::VLD1q16wb_fixed: 2959 case ARM::VLD1q32wb_fixed: 2960 case ARM::VLD1q64wb_fixed: 2961 case ARM::VLD1q8wb_register: 2962 case ARM::VLD1q16wb_register: 2963 case ARM::VLD1q32wb_register: 2964 case ARM::VLD1q64wb_register: 2965 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2966 // variant encodes Rm == 0xf. Anything else is a register offset post- 2967 // increment and we need to add the register operand to the instruction. 2968 if (Rm != 0xD && Rm != 0xF && 2969 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2970 return MCDisassembler::Fail; 2971 break; 2972 case ARM::VLD2d8wb_fixed: 2973 case ARM::VLD2d16wb_fixed: 2974 case ARM::VLD2d32wb_fixed: 2975 case ARM::VLD2b8wb_fixed: 2976 case ARM::VLD2b16wb_fixed: 2977 case ARM::VLD2b32wb_fixed: 2978 case ARM::VLD2q8wb_fixed: 2979 case ARM::VLD2q16wb_fixed: 2980 case ARM::VLD2q32wb_fixed: 2981 break; 2982 } 2983 2984 return S; 2985 } 2986 2987 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2988 uint64_t Address, const void *Decoder) { 2989 unsigned type = fieldFromInstruction(Insn, 8, 4); 2990 unsigned align = fieldFromInstruction(Insn, 4, 2); 2991 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2992 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2993 if (type == 10 && align == 3) return MCDisassembler::Fail; 2994 2995 unsigned load = fieldFromInstruction(Insn, 21, 1); 2996 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2997 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2998 } 2999 3000 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 3001 uint64_t Address, const void *Decoder) { 3002 unsigned size = fieldFromInstruction(Insn, 6, 2); 3003 if (size == 3) return MCDisassembler::Fail; 3004 3005 unsigned type = fieldFromInstruction(Insn, 8, 4); 3006 unsigned align = fieldFromInstruction(Insn, 4, 2); 3007 if (type == 8 && align == 3) return MCDisassembler::Fail; 3008 if (type == 9 && align == 3) return MCDisassembler::Fail; 3009 3010 unsigned load = fieldFromInstruction(Insn, 21, 1); 3011 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3012 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3013 } 3014 3015 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3016 uint64_t Address, const void *Decoder) { 3017 unsigned size = fieldFromInstruction(Insn, 6, 2); 3018 if (size == 3) return MCDisassembler::Fail; 3019 3020 unsigned align = fieldFromInstruction(Insn, 4, 2); 3021 if (align & 2) return MCDisassembler::Fail; 3022 3023 unsigned load = fieldFromInstruction(Insn, 21, 1); 3024 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3025 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3026 } 3027 3028 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3029 uint64_t Address, const void *Decoder) { 3030 unsigned size = fieldFromInstruction(Insn, 6, 2); 3031 if (size == 3) return MCDisassembler::Fail; 3032 3033 unsigned load = fieldFromInstruction(Insn, 21, 1); 3034 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3035 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3036 } 3037 3038 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3039 uint64_t Address, const void *Decoder) { 3040 DecodeStatus S = MCDisassembler::Success; 3041 3042 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3043 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3044 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3045 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3046 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3047 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3048 3049 // Writeback Operand 3050 switch (Inst.getOpcode()) { 3051 case ARM::VST1d8wb_fixed: 3052 case ARM::VST1d16wb_fixed: 3053 case ARM::VST1d32wb_fixed: 3054 case ARM::VST1d64wb_fixed: 3055 case ARM::VST1d8wb_register: 3056 case ARM::VST1d16wb_register: 3057 case ARM::VST1d32wb_register: 3058 case ARM::VST1d64wb_register: 3059 case ARM::VST1q8wb_fixed: 3060 case ARM::VST1q16wb_fixed: 3061 case ARM::VST1q32wb_fixed: 3062 case ARM::VST1q64wb_fixed: 3063 case ARM::VST1q8wb_register: 3064 case ARM::VST1q16wb_register: 3065 case ARM::VST1q32wb_register: 3066 case ARM::VST1q64wb_register: 3067 case ARM::VST1d8Twb_fixed: 3068 case ARM::VST1d16Twb_fixed: 3069 case ARM::VST1d32Twb_fixed: 3070 case ARM::VST1d64Twb_fixed: 3071 case ARM::VST1d8Twb_register: 3072 case ARM::VST1d16Twb_register: 3073 case ARM::VST1d32Twb_register: 3074 case ARM::VST1d64Twb_register: 3075 case ARM::VST1d8Qwb_fixed: 3076 case ARM::VST1d16Qwb_fixed: 3077 case ARM::VST1d32Qwb_fixed: 3078 case ARM::VST1d64Qwb_fixed: 3079 case ARM::VST1d8Qwb_register: 3080 case ARM::VST1d16Qwb_register: 3081 case ARM::VST1d32Qwb_register: 3082 case ARM::VST1d64Qwb_register: 3083 case ARM::VST2d8wb_fixed: 3084 case ARM::VST2d16wb_fixed: 3085 case ARM::VST2d32wb_fixed: 3086 case ARM::VST2d8wb_register: 3087 case ARM::VST2d16wb_register: 3088 case ARM::VST2d32wb_register: 3089 case ARM::VST2q8wb_fixed: 3090 case ARM::VST2q16wb_fixed: 3091 case ARM::VST2q32wb_fixed: 3092 case ARM::VST2q8wb_register: 3093 case ARM::VST2q16wb_register: 3094 case ARM::VST2q32wb_register: 3095 case ARM::VST2b8wb_fixed: 3096 case ARM::VST2b16wb_fixed: 3097 case ARM::VST2b32wb_fixed: 3098 case ARM::VST2b8wb_register: 3099 case ARM::VST2b16wb_register: 3100 case ARM::VST2b32wb_register: 3101 if (Rm == 0xF) 3102 return MCDisassembler::Fail; 3103 Inst.addOperand(MCOperand::createImm(0)); 3104 break; 3105 case ARM::VST3d8_UPD: 3106 case ARM::VST3d16_UPD: 3107 case ARM::VST3d32_UPD: 3108 case ARM::VST3q8_UPD: 3109 case ARM::VST3q16_UPD: 3110 case ARM::VST3q32_UPD: 3111 case ARM::VST4d8_UPD: 3112 case ARM::VST4d16_UPD: 3113 case ARM::VST4d32_UPD: 3114 case ARM::VST4q8_UPD: 3115 case ARM::VST4q16_UPD: 3116 case ARM::VST4q32_UPD: 3117 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3118 return MCDisassembler::Fail; 3119 break; 3120 default: 3121 break; 3122 } 3123 3124 // AddrMode6 Base (register+alignment) 3125 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3126 return MCDisassembler::Fail; 3127 3128 // AddrMode6 Offset (register) 3129 switch (Inst.getOpcode()) { 3130 default: 3131 if (Rm == 0xD) 3132 Inst.addOperand(MCOperand::createReg(0)); 3133 else if (Rm != 0xF) { 3134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3135 return MCDisassembler::Fail; 3136 } 3137 break; 3138 case ARM::VST1d8wb_fixed: 3139 case ARM::VST1d16wb_fixed: 3140 case ARM::VST1d32wb_fixed: 3141 case ARM::VST1d64wb_fixed: 3142 case ARM::VST1q8wb_fixed: 3143 case ARM::VST1q16wb_fixed: 3144 case ARM::VST1q32wb_fixed: 3145 case ARM::VST1q64wb_fixed: 3146 case ARM::VST1d8Twb_fixed: 3147 case ARM::VST1d16Twb_fixed: 3148 case ARM::VST1d32Twb_fixed: 3149 case ARM::VST1d64Twb_fixed: 3150 case ARM::VST1d8Qwb_fixed: 3151 case ARM::VST1d16Qwb_fixed: 3152 case ARM::VST1d32Qwb_fixed: 3153 case ARM::VST1d64Qwb_fixed: 3154 case ARM::VST2d8wb_fixed: 3155 case ARM::VST2d16wb_fixed: 3156 case ARM::VST2d32wb_fixed: 3157 case ARM::VST2q8wb_fixed: 3158 case ARM::VST2q16wb_fixed: 3159 case ARM::VST2q32wb_fixed: 3160 case ARM::VST2b8wb_fixed: 3161 case ARM::VST2b16wb_fixed: 3162 case ARM::VST2b32wb_fixed: 3163 break; 3164 } 3165 3166 // First input register 3167 switch (Inst.getOpcode()) { 3168 case ARM::VST1q16: 3169 case ARM::VST1q32: 3170 case ARM::VST1q64: 3171 case ARM::VST1q8: 3172 case ARM::VST1q16wb_fixed: 3173 case ARM::VST1q16wb_register: 3174 case ARM::VST1q32wb_fixed: 3175 case ARM::VST1q32wb_register: 3176 case ARM::VST1q64wb_fixed: 3177 case ARM::VST1q64wb_register: 3178 case ARM::VST1q8wb_fixed: 3179 case ARM::VST1q8wb_register: 3180 case ARM::VST2d16: 3181 case ARM::VST2d32: 3182 case ARM::VST2d8: 3183 case ARM::VST2d16wb_fixed: 3184 case ARM::VST2d16wb_register: 3185 case ARM::VST2d32wb_fixed: 3186 case ARM::VST2d32wb_register: 3187 case ARM::VST2d8wb_fixed: 3188 case ARM::VST2d8wb_register: 3189 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3190 return MCDisassembler::Fail; 3191 break; 3192 case ARM::VST2b16: 3193 case ARM::VST2b32: 3194 case ARM::VST2b8: 3195 case ARM::VST2b16wb_fixed: 3196 case ARM::VST2b16wb_register: 3197 case ARM::VST2b32wb_fixed: 3198 case ARM::VST2b32wb_register: 3199 case ARM::VST2b8wb_fixed: 3200 case ARM::VST2b8wb_register: 3201 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3202 return MCDisassembler::Fail; 3203 break; 3204 default: 3205 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3206 return MCDisassembler::Fail; 3207 } 3208 3209 // Second input register 3210 switch (Inst.getOpcode()) { 3211 case ARM::VST3d8: 3212 case ARM::VST3d16: 3213 case ARM::VST3d32: 3214 case ARM::VST3d8_UPD: 3215 case ARM::VST3d16_UPD: 3216 case ARM::VST3d32_UPD: 3217 case ARM::VST4d8: 3218 case ARM::VST4d16: 3219 case ARM::VST4d32: 3220 case ARM::VST4d8_UPD: 3221 case ARM::VST4d16_UPD: 3222 case ARM::VST4d32_UPD: 3223 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3224 return MCDisassembler::Fail; 3225 break; 3226 case ARM::VST3q8: 3227 case ARM::VST3q16: 3228 case ARM::VST3q32: 3229 case ARM::VST3q8_UPD: 3230 case ARM::VST3q16_UPD: 3231 case ARM::VST3q32_UPD: 3232 case ARM::VST4q8: 3233 case ARM::VST4q16: 3234 case ARM::VST4q32: 3235 case ARM::VST4q8_UPD: 3236 case ARM::VST4q16_UPD: 3237 case ARM::VST4q32_UPD: 3238 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3239 return MCDisassembler::Fail; 3240 break; 3241 default: 3242 break; 3243 } 3244 3245 // Third input register 3246 switch (Inst.getOpcode()) { 3247 case ARM::VST3d8: 3248 case ARM::VST3d16: 3249 case ARM::VST3d32: 3250 case ARM::VST3d8_UPD: 3251 case ARM::VST3d16_UPD: 3252 case ARM::VST3d32_UPD: 3253 case ARM::VST4d8: 3254 case ARM::VST4d16: 3255 case ARM::VST4d32: 3256 case ARM::VST4d8_UPD: 3257 case ARM::VST4d16_UPD: 3258 case ARM::VST4d32_UPD: 3259 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3260 return MCDisassembler::Fail; 3261 break; 3262 case ARM::VST3q8: 3263 case ARM::VST3q16: 3264 case ARM::VST3q32: 3265 case ARM::VST3q8_UPD: 3266 case ARM::VST3q16_UPD: 3267 case ARM::VST3q32_UPD: 3268 case ARM::VST4q8: 3269 case ARM::VST4q16: 3270 case ARM::VST4q32: 3271 case ARM::VST4q8_UPD: 3272 case ARM::VST4q16_UPD: 3273 case ARM::VST4q32_UPD: 3274 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3275 return MCDisassembler::Fail; 3276 break; 3277 default: 3278 break; 3279 } 3280 3281 // Fourth input register 3282 switch (Inst.getOpcode()) { 3283 case ARM::VST4d8: 3284 case ARM::VST4d16: 3285 case ARM::VST4d32: 3286 case ARM::VST4d8_UPD: 3287 case ARM::VST4d16_UPD: 3288 case ARM::VST4d32_UPD: 3289 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3290 return MCDisassembler::Fail; 3291 break; 3292 case ARM::VST4q8: 3293 case ARM::VST4q16: 3294 case ARM::VST4q32: 3295 case ARM::VST4q8_UPD: 3296 case ARM::VST4q16_UPD: 3297 case ARM::VST4q32_UPD: 3298 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3299 return MCDisassembler::Fail; 3300 break; 3301 default: 3302 break; 3303 } 3304 3305 return S; 3306 } 3307 3308 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3309 uint64_t Address, const void *Decoder) { 3310 DecodeStatus S = MCDisassembler::Success; 3311 3312 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3313 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3314 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3315 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3316 unsigned align = fieldFromInstruction(Insn, 4, 1); 3317 unsigned size = fieldFromInstruction(Insn, 6, 2); 3318 3319 if (size == 0 && align == 1) 3320 return MCDisassembler::Fail; 3321 align *= (1 << size); 3322 3323 switch (Inst.getOpcode()) { 3324 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3325 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3326 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3327 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3328 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3329 return MCDisassembler::Fail; 3330 break; 3331 default: 3332 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3333 return MCDisassembler::Fail; 3334 break; 3335 } 3336 if (Rm != 0xF) { 3337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3338 return MCDisassembler::Fail; 3339 } 3340 3341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3342 return MCDisassembler::Fail; 3343 Inst.addOperand(MCOperand::createImm(align)); 3344 3345 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3346 // variant encodes Rm == 0xf. Anything else is a register offset post- 3347 // increment and we need to add the register operand to the instruction. 3348 if (Rm != 0xD && Rm != 0xF && 3349 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3350 return MCDisassembler::Fail; 3351 3352 return S; 3353 } 3354 3355 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3356 uint64_t Address, const void *Decoder) { 3357 DecodeStatus S = MCDisassembler::Success; 3358 3359 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3360 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3361 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3362 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3363 unsigned align = fieldFromInstruction(Insn, 4, 1); 3364 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3365 align *= 2*size; 3366 3367 switch (Inst.getOpcode()) { 3368 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3369 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3370 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3371 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3372 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3373 return MCDisassembler::Fail; 3374 break; 3375 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3376 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3377 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3378 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3379 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3380 return MCDisassembler::Fail; 3381 break; 3382 default: 3383 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3384 return MCDisassembler::Fail; 3385 break; 3386 } 3387 3388 if (Rm != 0xF) 3389 Inst.addOperand(MCOperand::createImm(0)); 3390 3391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3392 return MCDisassembler::Fail; 3393 Inst.addOperand(MCOperand::createImm(align)); 3394 3395 if (Rm != 0xD && Rm != 0xF) { 3396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3397 return MCDisassembler::Fail; 3398 } 3399 3400 return S; 3401 } 3402 3403 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3404 uint64_t Address, const void *Decoder) { 3405 DecodeStatus S = MCDisassembler::Success; 3406 3407 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3408 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3409 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3410 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3411 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3412 3413 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3414 return MCDisassembler::Fail; 3415 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3416 return MCDisassembler::Fail; 3417 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3418 return MCDisassembler::Fail; 3419 if (Rm != 0xF) { 3420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3421 return MCDisassembler::Fail; 3422 } 3423 3424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3425 return MCDisassembler::Fail; 3426 Inst.addOperand(MCOperand::createImm(0)); 3427 3428 if (Rm == 0xD) 3429 Inst.addOperand(MCOperand::createReg(0)); 3430 else if (Rm != 0xF) { 3431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3432 return MCDisassembler::Fail; 3433 } 3434 3435 return S; 3436 } 3437 3438 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3439 uint64_t Address, const void *Decoder) { 3440 DecodeStatus S = MCDisassembler::Success; 3441 3442 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3443 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3444 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3445 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3446 unsigned size = fieldFromInstruction(Insn, 6, 2); 3447 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3448 unsigned align = fieldFromInstruction(Insn, 4, 1); 3449 3450 if (size == 0x3) { 3451 if (align == 0) 3452 return MCDisassembler::Fail; 3453 align = 16; 3454 } else { 3455 if (size == 2) { 3456 align *= 8; 3457 } else { 3458 size = 1 << size; 3459 align *= 4*size; 3460 } 3461 } 3462 3463 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3464 return MCDisassembler::Fail; 3465 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3466 return MCDisassembler::Fail; 3467 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3468 return MCDisassembler::Fail; 3469 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3470 return MCDisassembler::Fail; 3471 if (Rm != 0xF) { 3472 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3473 return MCDisassembler::Fail; 3474 } 3475 3476 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3477 return MCDisassembler::Fail; 3478 Inst.addOperand(MCOperand::createImm(align)); 3479 3480 if (Rm == 0xD) 3481 Inst.addOperand(MCOperand::createReg(0)); 3482 else if (Rm != 0xF) { 3483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3484 return MCDisassembler::Fail; 3485 } 3486 3487 return S; 3488 } 3489 3490 static DecodeStatus 3491 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3492 uint64_t Address, const void *Decoder) { 3493 DecodeStatus S = MCDisassembler::Success; 3494 3495 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3496 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3497 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3498 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3499 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3500 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3501 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3502 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3503 3504 if (Q) { 3505 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3506 return MCDisassembler::Fail; 3507 } else { 3508 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3509 return MCDisassembler::Fail; 3510 } 3511 3512 Inst.addOperand(MCOperand::createImm(imm)); 3513 3514 switch (Inst.getOpcode()) { 3515 case ARM::VORRiv4i16: 3516 case ARM::VORRiv2i32: 3517 case ARM::VBICiv4i16: 3518 case ARM::VBICiv2i32: 3519 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3520 return MCDisassembler::Fail; 3521 break; 3522 case ARM::VORRiv8i16: 3523 case ARM::VORRiv4i32: 3524 case ARM::VBICiv8i16: 3525 case ARM::VBICiv4i32: 3526 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3527 return MCDisassembler::Fail; 3528 break; 3529 default: 3530 break; 3531 } 3532 3533 return S; 3534 } 3535 3536 static DecodeStatus 3537 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3538 uint64_t Address, const void *Decoder) { 3539 DecodeStatus S = MCDisassembler::Success; 3540 3541 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3542 fieldFromInstruction(Insn, 13, 3)); 3543 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3544 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3545 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3546 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3547 imm |= cmode << 8; 3548 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3549 3550 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3551 return MCDisassembler::Fail; 3552 3553 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3554 return MCDisassembler::Fail; 3555 3556 Inst.addOperand(MCOperand::createImm(imm)); 3557 3558 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3559 Inst.addOperand(MCOperand::createReg(0)); 3560 Inst.addOperand(MCOperand::createImm(0)); 3561 3562 return S; 3563 } 3564 3565 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3566 uint64_t Address, const void *Decoder) { 3567 DecodeStatus S = MCDisassembler::Success; 3568 3569 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3570 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3571 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3572 return MCDisassembler::Fail; 3573 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3574 3575 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3576 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3577 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3578 return MCDisassembler::Fail; 3579 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3580 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3581 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3582 return MCDisassembler::Fail; 3583 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3584 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3585 Inst.addOperand(MCOperand::createImm(Qd)); 3586 3587 return S; 3588 } 3589 3590 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3591 uint64_t Address, const void *Decoder) { 3592 DecodeStatus S = MCDisassembler::Success; 3593 3594 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3595 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3596 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3597 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3598 unsigned size = fieldFromInstruction(Insn, 18, 2); 3599 3600 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3601 return MCDisassembler::Fail; 3602 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3603 return MCDisassembler::Fail; 3604 Inst.addOperand(MCOperand::createImm(8 << size)); 3605 3606 return S; 3607 } 3608 3609 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3610 uint64_t Address, const void *Decoder) { 3611 Inst.addOperand(MCOperand::createImm(8 - Val)); 3612 return MCDisassembler::Success; 3613 } 3614 3615 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3616 uint64_t Address, const void *Decoder) { 3617 Inst.addOperand(MCOperand::createImm(16 - Val)); 3618 return MCDisassembler::Success; 3619 } 3620 3621 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3622 uint64_t Address, const void *Decoder) { 3623 Inst.addOperand(MCOperand::createImm(32 - Val)); 3624 return MCDisassembler::Success; 3625 } 3626 3627 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3628 uint64_t Address, const void *Decoder) { 3629 Inst.addOperand(MCOperand::createImm(64 - Val)); 3630 return MCDisassembler::Success; 3631 } 3632 3633 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3634 uint64_t Address, const void *Decoder) { 3635 DecodeStatus S = MCDisassembler::Success; 3636 3637 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3638 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3639 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3640 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3641 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3642 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3643 unsigned op = fieldFromInstruction(Insn, 6, 1); 3644 3645 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3646 return MCDisassembler::Fail; 3647 if (op) { 3648 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3649 return MCDisassembler::Fail; // Writeback 3650 } 3651 3652 switch (Inst.getOpcode()) { 3653 case ARM::VTBL2: 3654 case ARM::VTBX2: 3655 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3656 return MCDisassembler::Fail; 3657 break; 3658 default: 3659 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3660 return MCDisassembler::Fail; 3661 } 3662 3663 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3664 return MCDisassembler::Fail; 3665 3666 return S; 3667 } 3668 3669 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3670 uint64_t Address, const void *Decoder) { 3671 DecodeStatus S = MCDisassembler::Success; 3672 3673 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3674 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3675 3676 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3677 return MCDisassembler::Fail; 3678 3679 switch(Inst.getOpcode()) { 3680 default: 3681 return MCDisassembler::Fail; 3682 case ARM::tADR: 3683 break; // tADR does not explicitly represent the PC as an operand. 3684 case ARM::tADDrSPi: 3685 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3686 break; 3687 } 3688 3689 Inst.addOperand(MCOperand::createImm(imm)); 3690 return S; 3691 } 3692 3693 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3694 uint64_t Address, const void *Decoder) { 3695 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3696 true, 2, Inst, Decoder)) 3697 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3698 return MCDisassembler::Success; 3699 } 3700 3701 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3702 uint64_t Address, const void *Decoder) { 3703 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3704 true, 4, Inst, Decoder)) 3705 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3706 return MCDisassembler::Success; 3707 } 3708 3709 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3710 uint64_t Address, const void *Decoder) { 3711 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3712 true, 2, Inst, Decoder)) 3713 Inst.addOperand(MCOperand::createImm(Val << 1)); 3714 return MCDisassembler::Success; 3715 } 3716 3717 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3718 uint64_t Address, const void *Decoder) { 3719 DecodeStatus S = MCDisassembler::Success; 3720 3721 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3722 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3723 3724 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3725 return MCDisassembler::Fail; 3726 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3727 return MCDisassembler::Fail; 3728 3729 return S; 3730 } 3731 3732 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3733 uint64_t Address, const void *Decoder) { 3734 DecodeStatus S = MCDisassembler::Success; 3735 3736 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3737 unsigned imm = fieldFromInstruction(Val, 3, 5); 3738 3739 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3740 return MCDisassembler::Fail; 3741 Inst.addOperand(MCOperand::createImm(imm)); 3742 3743 return S; 3744 } 3745 3746 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3747 uint64_t Address, const void *Decoder) { 3748 unsigned imm = Val << 2; 3749 3750 Inst.addOperand(MCOperand::createImm(imm)); 3751 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3752 3753 return MCDisassembler::Success; 3754 } 3755 3756 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3757 uint64_t Address, const void *Decoder) { 3758 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3759 Inst.addOperand(MCOperand::createImm(Val)); 3760 3761 return MCDisassembler::Success; 3762 } 3763 3764 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3765 uint64_t Address, const void *Decoder) { 3766 DecodeStatus S = MCDisassembler::Success; 3767 3768 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3769 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3770 unsigned imm = fieldFromInstruction(Val, 0, 2); 3771 3772 // Thumb stores cannot use PC as dest register. 3773 switch (Inst.getOpcode()) { 3774 case ARM::t2STRHs: 3775 case ARM::t2STRBs: 3776 case ARM::t2STRs: 3777 if (Rn == 15) 3778 return MCDisassembler::Fail; 3779 break; 3780 default: 3781 break; 3782 } 3783 3784 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3785 return MCDisassembler::Fail; 3786 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3787 return MCDisassembler::Fail; 3788 Inst.addOperand(MCOperand::createImm(imm)); 3789 3790 return S; 3791 } 3792 3793 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3794 uint64_t Address, const void *Decoder) { 3795 DecodeStatus S = MCDisassembler::Success; 3796 3797 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3798 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3799 3800 const FeatureBitset &featureBits = 3801 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3802 3803 bool hasMP = featureBits[ARM::FeatureMP]; 3804 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3805 3806 if (Rn == 15) { 3807 switch (Inst.getOpcode()) { 3808 case ARM::t2LDRBs: 3809 Inst.setOpcode(ARM::t2LDRBpci); 3810 break; 3811 case ARM::t2LDRHs: 3812 Inst.setOpcode(ARM::t2LDRHpci); 3813 break; 3814 case ARM::t2LDRSHs: 3815 Inst.setOpcode(ARM::t2LDRSHpci); 3816 break; 3817 case ARM::t2LDRSBs: 3818 Inst.setOpcode(ARM::t2LDRSBpci); 3819 break; 3820 case ARM::t2LDRs: 3821 Inst.setOpcode(ARM::t2LDRpci); 3822 break; 3823 case ARM::t2PLDs: 3824 Inst.setOpcode(ARM::t2PLDpci); 3825 break; 3826 case ARM::t2PLIs: 3827 Inst.setOpcode(ARM::t2PLIpci); 3828 break; 3829 default: 3830 return MCDisassembler::Fail; 3831 } 3832 3833 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3834 } 3835 3836 if (Rt == 15) { 3837 switch (Inst.getOpcode()) { 3838 case ARM::t2LDRSHs: 3839 return MCDisassembler::Fail; 3840 case ARM::t2LDRHs: 3841 Inst.setOpcode(ARM::t2PLDWs); 3842 break; 3843 case ARM::t2LDRSBs: 3844 Inst.setOpcode(ARM::t2PLIs); 3845 break; 3846 default: 3847 break; 3848 } 3849 } 3850 3851 switch (Inst.getOpcode()) { 3852 case ARM::t2PLDs: 3853 break; 3854 case ARM::t2PLIs: 3855 if (!hasV7Ops) 3856 return MCDisassembler::Fail; 3857 break; 3858 case ARM::t2PLDWs: 3859 if (!hasV7Ops || !hasMP) 3860 return MCDisassembler::Fail; 3861 break; 3862 default: 3863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3864 return MCDisassembler::Fail; 3865 } 3866 3867 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3868 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3869 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3870 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3871 return MCDisassembler::Fail; 3872 3873 return S; 3874 } 3875 3876 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3877 uint64_t Address, const void* Decoder) { 3878 DecodeStatus S = MCDisassembler::Success; 3879 3880 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3881 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3882 unsigned U = fieldFromInstruction(Insn, 9, 1); 3883 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3884 imm |= (U << 8); 3885 imm |= (Rn << 9); 3886 unsigned add = fieldFromInstruction(Insn, 9, 1); 3887 3888 const FeatureBitset &featureBits = 3889 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3890 3891 bool hasMP = featureBits[ARM::FeatureMP]; 3892 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3893 3894 if (Rn == 15) { 3895 switch (Inst.getOpcode()) { 3896 case ARM::t2LDRi8: 3897 Inst.setOpcode(ARM::t2LDRpci); 3898 break; 3899 case ARM::t2LDRBi8: 3900 Inst.setOpcode(ARM::t2LDRBpci); 3901 break; 3902 case ARM::t2LDRSBi8: 3903 Inst.setOpcode(ARM::t2LDRSBpci); 3904 break; 3905 case ARM::t2LDRHi8: 3906 Inst.setOpcode(ARM::t2LDRHpci); 3907 break; 3908 case ARM::t2LDRSHi8: 3909 Inst.setOpcode(ARM::t2LDRSHpci); 3910 break; 3911 case ARM::t2PLDi8: 3912 Inst.setOpcode(ARM::t2PLDpci); 3913 break; 3914 case ARM::t2PLIi8: 3915 Inst.setOpcode(ARM::t2PLIpci); 3916 break; 3917 default: 3918 return MCDisassembler::Fail; 3919 } 3920 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3921 } 3922 3923 if (Rt == 15) { 3924 switch (Inst.getOpcode()) { 3925 case ARM::t2LDRSHi8: 3926 return MCDisassembler::Fail; 3927 case ARM::t2LDRHi8: 3928 if (!add) 3929 Inst.setOpcode(ARM::t2PLDWi8); 3930 break; 3931 case ARM::t2LDRSBi8: 3932 Inst.setOpcode(ARM::t2PLIi8); 3933 break; 3934 default: 3935 break; 3936 } 3937 } 3938 3939 switch (Inst.getOpcode()) { 3940 case ARM::t2PLDi8: 3941 break; 3942 case ARM::t2PLIi8: 3943 if (!hasV7Ops) 3944 return MCDisassembler::Fail; 3945 break; 3946 case ARM::t2PLDWi8: 3947 if (!hasV7Ops || !hasMP) 3948 return MCDisassembler::Fail; 3949 break; 3950 default: 3951 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3952 return MCDisassembler::Fail; 3953 } 3954 3955 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3956 return MCDisassembler::Fail; 3957 return S; 3958 } 3959 3960 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3961 uint64_t Address, const void* Decoder) { 3962 DecodeStatus S = MCDisassembler::Success; 3963 3964 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3965 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3966 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3967 imm |= (Rn << 13); 3968 3969 const FeatureBitset &featureBits = 3970 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3971 3972 bool hasMP = featureBits[ARM::FeatureMP]; 3973 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3974 3975 if (Rn == 15) { 3976 switch (Inst.getOpcode()) { 3977 case ARM::t2LDRi12: 3978 Inst.setOpcode(ARM::t2LDRpci); 3979 break; 3980 case ARM::t2LDRHi12: 3981 Inst.setOpcode(ARM::t2LDRHpci); 3982 break; 3983 case ARM::t2LDRSHi12: 3984 Inst.setOpcode(ARM::t2LDRSHpci); 3985 break; 3986 case ARM::t2LDRBi12: 3987 Inst.setOpcode(ARM::t2LDRBpci); 3988 break; 3989 case ARM::t2LDRSBi12: 3990 Inst.setOpcode(ARM::t2LDRSBpci); 3991 break; 3992 case ARM::t2PLDi12: 3993 Inst.setOpcode(ARM::t2PLDpci); 3994 break; 3995 case ARM::t2PLIi12: 3996 Inst.setOpcode(ARM::t2PLIpci); 3997 break; 3998 default: 3999 return MCDisassembler::Fail; 4000 } 4001 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4002 } 4003 4004 if (Rt == 15) { 4005 switch (Inst.getOpcode()) { 4006 case ARM::t2LDRSHi12: 4007 return MCDisassembler::Fail; 4008 case ARM::t2LDRHi12: 4009 Inst.setOpcode(ARM::t2PLDWi12); 4010 break; 4011 case ARM::t2LDRSBi12: 4012 Inst.setOpcode(ARM::t2PLIi12); 4013 break; 4014 default: 4015 break; 4016 } 4017 } 4018 4019 switch (Inst.getOpcode()) { 4020 case ARM::t2PLDi12: 4021 break; 4022 case ARM::t2PLIi12: 4023 if (!hasV7Ops) 4024 return MCDisassembler::Fail; 4025 break; 4026 case ARM::t2PLDWi12: 4027 if (!hasV7Ops || !hasMP) 4028 return MCDisassembler::Fail; 4029 break; 4030 default: 4031 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4032 return MCDisassembler::Fail; 4033 } 4034 4035 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4036 return MCDisassembler::Fail; 4037 return S; 4038 } 4039 4040 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 4041 uint64_t Address, const void* Decoder) { 4042 DecodeStatus S = MCDisassembler::Success; 4043 4044 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4045 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4046 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4047 imm |= (Rn << 9); 4048 4049 if (Rn == 15) { 4050 switch (Inst.getOpcode()) { 4051 case ARM::t2LDRT: 4052 Inst.setOpcode(ARM::t2LDRpci); 4053 break; 4054 case ARM::t2LDRBT: 4055 Inst.setOpcode(ARM::t2LDRBpci); 4056 break; 4057 case ARM::t2LDRHT: 4058 Inst.setOpcode(ARM::t2LDRHpci); 4059 break; 4060 case ARM::t2LDRSBT: 4061 Inst.setOpcode(ARM::t2LDRSBpci); 4062 break; 4063 case ARM::t2LDRSHT: 4064 Inst.setOpcode(ARM::t2LDRSHpci); 4065 break; 4066 default: 4067 return MCDisassembler::Fail; 4068 } 4069 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4070 } 4071 4072 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4073 return MCDisassembler::Fail; 4074 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4075 return MCDisassembler::Fail; 4076 return S; 4077 } 4078 4079 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4080 uint64_t Address, const void* Decoder) { 4081 DecodeStatus S = MCDisassembler::Success; 4082 4083 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4084 unsigned U = fieldFromInstruction(Insn, 23, 1); 4085 int imm = fieldFromInstruction(Insn, 0, 12); 4086 4087 const FeatureBitset &featureBits = 4088 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4089 4090 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4091 4092 if (Rt == 15) { 4093 switch (Inst.getOpcode()) { 4094 case ARM::t2LDRBpci: 4095 case ARM::t2LDRHpci: 4096 Inst.setOpcode(ARM::t2PLDpci); 4097 break; 4098 case ARM::t2LDRSBpci: 4099 Inst.setOpcode(ARM::t2PLIpci); 4100 break; 4101 case ARM::t2LDRSHpci: 4102 return MCDisassembler::Fail; 4103 default: 4104 break; 4105 } 4106 } 4107 4108 switch(Inst.getOpcode()) { 4109 case ARM::t2PLDpci: 4110 break; 4111 case ARM::t2PLIpci: 4112 if (!hasV7Ops) 4113 return MCDisassembler::Fail; 4114 break; 4115 default: 4116 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4117 return MCDisassembler::Fail; 4118 } 4119 4120 if (!U) { 4121 // Special case for #-0. 4122 if (imm == 0) 4123 imm = INT32_MIN; 4124 else 4125 imm = -imm; 4126 } 4127 Inst.addOperand(MCOperand::createImm(imm)); 4128 4129 return S; 4130 } 4131 4132 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4133 uint64_t Address, const void *Decoder) { 4134 if (Val == 0) 4135 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4136 else { 4137 int imm = Val & 0xFF; 4138 4139 if (!(Val & 0x100)) imm *= -1; 4140 Inst.addOperand(MCOperand::createImm(imm * 4)); 4141 } 4142 4143 return MCDisassembler::Success; 4144 } 4145 4146 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4147 const void *Decoder) { 4148 if (Val == 0) 4149 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4150 else { 4151 int imm = Val & 0x7F; 4152 4153 if (!(Val & 0x80)) 4154 imm *= -1; 4155 Inst.addOperand(MCOperand::createImm(imm * 4)); 4156 } 4157 4158 return MCDisassembler::Success; 4159 } 4160 4161 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4162 uint64_t Address, const void *Decoder) { 4163 DecodeStatus S = MCDisassembler::Success; 4164 4165 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4166 unsigned imm = fieldFromInstruction(Val, 0, 9); 4167 4168 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4169 return MCDisassembler::Fail; 4170 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4171 return MCDisassembler::Fail; 4172 4173 return S; 4174 } 4175 4176 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4177 uint64_t Address, 4178 const void *Decoder) { 4179 DecodeStatus S = MCDisassembler::Success; 4180 4181 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4182 unsigned imm = fieldFromInstruction(Val, 0, 8); 4183 4184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4185 return MCDisassembler::Fail; 4186 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4187 return MCDisassembler::Fail; 4188 4189 return S; 4190 } 4191 4192 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4193 uint64_t Address, const void *Decoder) { 4194 DecodeStatus S = MCDisassembler::Success; 4195 4196 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4197 unsigned imm = fieldFromInstruction(Val, 0, 8); 4198 4199 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4200 return MCDisassembler::Fail; 4201 4202 Inst.addOperand(MCOperand::createImm(imm)); 4203 4204 return S; 4205 } 4206 4207 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4208 uint64_t Address, const void *Decoder) { 4209 int imm = Val & 0xFF; 4210 if (Val == 0) 4211 imm = INT32_MIN; 4212 else if (!(Val & 0x100)) 4213 imm *= -1; 4214 Inst.addOperand(MCOperand::createImm(imm)); 4215 4216 return MCDisassembler::Success; 4217 } 4218 4219 template<int shift> 4220 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 4221 uint64_t Address, const void *Decoder) { 4222 int imm = Val & 0x7F; 4223 if (Val == 0) 4224 imm = INT32_MIN; 4225 else if (!(Val & 0x80)) 4226 imm *= -1; 4227 if (imm != INT32_MIN) 4228 imm *= (1U << shift); 4229 Inst.addOperand(MCOperand::createImm(imm)); 4230 4231 return MCDisassembler::Success; 4232 } 4233 4234 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4235 uint64_t Address, const void *Decoder) { 4236 DecodeStatus S = MCDisassembler::Success; 4237 4238 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4239 unsigned imm = fieldFromInstruction(Val, 0, 9); 4240 4241 // Thumb stores cannot use PC as dest register. 4242 switch (Inst.getOpcode()) { 4243 case ARM::t2STRT: 4244 case ARM::t2STRBT: 4245 case ARM::t2STRHT: 4246 case ARM::t2STRi8: 4247 case ARM::t2STRHi8: 4248 case ARM::t2STRBi8: 4249 if (Rn == 15) 4250 return MCDisassembler::Fail; 4251 break; 4252 default: 4253 break; 4254 } 4255 4256 // Some instructions always use an additive offset. 4257 switch (Inst.getOpcode()) { 4258 case ARM::t2LDRT: 4259 case ARM::t2LDRBT: 4260 case ARM::t2LDRHT: 4261 case ARM::t2LDRSBT: 4262 case ARM::t2LDRSHT: 4263 case ARM::t2STRT: 4264 case ARM::t2STRBT: 4265 case ARM::t2STRHT: 4266 imm |= 0x100; 4267 break; 4268 default: 4269 break; 4270 } 4271 4272 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4273 return MCDisassembler::Fail; 4274 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4275 return MCDisassembler::Fail; 4276 4277 return S; 4278 } 4279 4280 template<int shift> 4281 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4282 uint64_t Address, 4283 const void *Decoder) { 4284 DecodeStatus S = MCDisassembler::Success; 4285 4286 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4287 unsigned imm = fieldFromInstruction(Val, 0, 8); 4288 4289 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4290 return MCDisassembler::Fail; 4291 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4292 return MCDisassembler::Fail; 4293 4294 return S; 4295 } 4296 4297 template<int shift, int WriteBack> 4298 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4299 uint64_t Address, 4300 const void *Decoder) { 4301 DecodeStatus S = MCDisassembler::Success; 4302 4303 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4304 unsigned imm = fieldFromInstruction(Val, 0, 8); 4305 if (WriteBack) { 4306 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4307 return MCDisassembler::Fail; 4308 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4309 return MCDisassembler::Fail; 4310 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4311 return MCDisassembler::Fail; 4312 4313 return S; 4314 } 4315 4316 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4317 uint64_t Address, const void *Decoder) { 4318 DecodeStatus S = MCDisassembler::Success; 4319 4320 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4321 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4322 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4323 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4324 addr |= Rn << 9; 4325 unsigned load = fieldFromInstruction(Insn, 20, 1); 4326 4327 if (Rn == 15) { 4328 switch (Inst.getOpcode()) { 4329 case ARM::t2LDR_PRE: 4330 case ARM::t2LDR_POST: 4331 Inst.setOpcode(ARM::t2LDRpci); 4332 break; 4333 case ARM::t2LDRB_PRE: 4334 case ARM::t2LDRB_POST: 4335 Inst.setOpcode(ARM::t2LDRBpci); 4336 break; 4337 case ARM::t2LDRH_PRE: 4338 case ARM::t2LDRH_POST: 4339 Inst.setOpcode(ARM::t2LDRHpci); 4340 break; 4341 case ARM::t2LDRSB_PRE: 4342 case ARM::t2LDRSB_POST: 4343 if (Rt == 15) 4344 Inst.setOpcode(ARM::t2PLIpci); 4345 else 4346 Inst.setOpcode(ARM::t2LDRSBpci); 4347 break; 4348 case ARM::t2LDRSH_PRE: 4349 case ARM::t2LDRSH_POST: 4350 Inst.setOpcode(ARM::t2LDRSHpci); 4351 break; 4352 default: 4353 return MCDisassembler::Fail; 4354 } 4355 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4356 } 4357 4358 if (!load) { 4359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4360 return MCDisassembler::Fail; 4361 } 4362 4363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4364 return MCDisassembler::Fail; 4365 4366 if (load) { 4367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4368 return MCDisassembler::Fail; 4369 } 4370 4371 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4372 return MCDisassembler::Fail; 4373 4374 return S; 4375 } 4376 4377 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4378 uint64_t Address, const void *Decoder) { 4379 DecodeStatus S = MCDisassembler::Success; 4380 4381 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4382 unsigned imm = fieldFromInstruction(Val, 0, 12); 4383 4384 // Thumb stores cannot use PC as dest register. 4385 switch (Inst.getOpcode()) { 4386 case ARM::t2STRi12: 4387 case ARM::t2STRBi12: 4388 case ARM::t2STRHi12: 4389 if (Rn == 15) 4390 return MCDisassembler::Fail; 4391 break; 4392 default: 4393 break; 4394 } 4395 4396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4397 return MCDisassembler::Fail; 4398 Inst.addOperand(MCOperand::createImm(imm)); 4399 4400 return S; 4401 } 4402 4403 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4404 uint64_t Address, const void *Decoder) { 4405 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4406 4407 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4408 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4409 Inst.addOperand(MCOperand::createImm(imm)); 4410 4411 return MCDisassembler::Success; 4412 } 4413 4414 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4415 uint64_t Address, const void *Decoder) { 4416 DecodeStatus S = MCDisassembler::Success; 4417 4418 if (Inst.getOpcode() == ARM::tADDrSP) { 4419 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4420 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4421 4422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4423 return MCDisassembler::Fail; 4424 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4426 return MCDisassembler::Fail; 4427 } else if (Inst.getOpcode() == ARM::tADDspr) { 4428 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4429 4430 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4431 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4433 return MCDisassembler::Fail; 4434 } 4435 4436 return S; 4437 } 4438 4439 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4440 uint64_t Address, const void *Decoder) { 4441 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4442 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4443 4444 Inst.addOperand(MCOperand::createImm(imod)); 4445 Inst.addOperand(MCOperand::createImm(flags)); 4446 4447 return MCDisassembler::Success; 4448 } 4449 4450 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4451 uint64_t Address, const void *Decoder) { 4452 DecodeStatus S = MCDisassembler::Success; 4453 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4454 unsigned add = fieldFromInstruction(Insn, 4, 1); 4455 4456 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4457 return MCDisassembler::Fail; 4458 Inst.addOperand(MCOperand::createImm(add)); 4459 4460 return S; 4461 } 4462 4463 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4464 uint64_t Address, const void *Decoder) { 4465 DecodeStatus S = MCDisassembler::Success; 4466 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4467 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4468 4469 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4470 return MCDisassembler::Fail; 4471 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4472 return MCDisassembler::Fail; 4473 4474 return S; 4475 } 4476 4477 template<int shift> 4478 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4479 uint64_t Address, const void *Decoder) { 4480 DecodeStatus S = MCDisassembler::Success; 4481 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4482 int imm = fieldFromInstruction(Insn, 0, 7); 4483 4484 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4485 return MCDisassembler::Fail; 4486 4487 if(!fieldFromInstruction(Insn, 7, 1)) { 4488 if (imm == 0) 4489 imm = INT32_MIN; // indicate -0 4490 else 4491 imm *= -1; 4492 } 4493 if (imm != INT32_MIN) 4494 imm *= (1U << shift); 4495 Inst.addOperand(MCOperand::createImm(imm)); 4496 4497 return S; 4498 } 4499 4500 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4501 uint64_t Address, const void *Decoder) { 4502 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4503 // Note only one trailing zero not two. Also the J1 and J2 values are from 4504 // the encoded instruction. So here change to I1 and I2 values via: 4505 // I1 = NOT(J1 EOR S); 4506 // I2 = NOT(J2 EOR S); 4507 // and build the imm32 with two trailing zeros as documented: 4508 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4509 unsigned S = (Val >> 23) & 1; 4510 unsigned J1 = (Val >> 22) & 1; 4511 unsigned J2 = (Val >> 21) & 1; 4512 unsigned I1 = !(J1 ^ S); 4513 unsigned I2 = !(J2 ^ S); 4514 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4515 int imm32 = SignExtend32<25>(tmp << 1); 4516 4517 if (!tryAddingSymbolicOperand(Address, 4518 (Address & ~2u) + imm32 + 4, 4519 true, 4, Inst, Decoder)) 4520 Inst.addOperand(MCOperand::createImm(imm32)); 4521 return MCDisassembler::Success; 4522 } 4523 4524 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4525 uint64_t Address, const void *Decoder) { 4526 if (Val == 0xA || Val == 0xB) 4527 return MCDisassembler::Fail; 4528 4529 const FeatureBitset &featureBits = 4530 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4531 4532 if (!isValidCoprocessorNumber(Val, featureBits)) 4533 return MCDisassembler::Fail; 4534 4535 Inst.addOperand(MCOperand::createImm(Val)); 4536 return MCDisassembler::Success; 4537 } 4538 4539 static DecodeStatus 4540 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4541 uint64_t Address, const void *Decoder) { 4542 const FeatureBitset &FeatureBits = 4543 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4544 DecodeStatus S = MCDisassembler::Success; 4545 4546 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4547 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4548 4549 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; 4550 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4551 return MCDisassembler::Fail; 4552 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4553 return MCDisassembler::Fail; 4554 return S; 4555 } 4556 4557 static DecodeStatus 4558 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4559 uint64_t Address, const void *Decoder) { 4560 DecodeStatus S = MCDisassembler::Success; 4561 4562 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4563 if (pred == 0xE || pred == 0xF) { 4564 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4565 switch (opc) { 4566 default: 4567 return MCDisassembler::Fail; 4568 case 0xf3bf8f4: 4569 Inst.setOpcode(ARM::t2DSB); 4570 break; 4571 case 0xf3bf8f5: 4572 Inst.setOpcode(ARM::t2DMB); 4573 break; 4574 case 0xf3bf8f6: 4575 Inst.setOpcode(ARM::t2ISB); 4576 break; 4577 } 4578 4579 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4580 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4581 } 4582 4583 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4584 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4585 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4586 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4587 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4588 4589 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4590 return MCDisassembler::Fail; 4591 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4592 return MCDisassembler::Fail; 4593 4594 return S; 4595 } 4596 4597 // Decode a shifted immediate operand. These basically consist 4598 // of an 8-bit value, and a 4-bit directive that specifies either 4599 // a splat operation or a rotation. 4600 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4601 uint64_t Address, const void *Decoder) { 4602 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4603 if (ctrl == 0) { 4604 unsigned byte = fieldFromInstruction(Val, 8, 2); 4605 unsigned imm = fieldFromInstruction(Val, 0, 8); 4606 switch (byte) { 4607 case 0: 4608 Inst.addOperand(MCOperand::createImm(imm)); 4609 break; 4610 case 1: 4611 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4612 break; 4613 case 2: 4614 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4615 break; 4616 case 3: 4617 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4618 (imm << 8) | imm)); 4619 break; 4620 } 4621 } else { 4622 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4623 unsigned rot = fieldFromInstruction(Val, 7, 5); 4624 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4625 Inst.addOperand(MCOperand::createImm(imm)); 4626 } 4627 4628 return MCDisassembler::Success; 4629 } 4630 4631 static DecodeStatus 4632 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4633 uint64_t Address, const void *Decoder) { 4634 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4635 true, 2, Inst, Decoder)) 4636 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4637 return MCDisassembler::Success; 4638 } 4639 4640 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4641 uint64_t Address, 4642 const void *Decoder) { 4643 // Val is passed in as S:J1:J2:imm10:imm11 4644 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4645 // the encoded instruction. So here change to I1 and I2 values via: 4646 // I1 = NOT(J1 EOR S); 4647 // I2 = NOT(J2 EOR S); 4648 // and build the imm32 with one trailing zero as documented: 4649 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4650 unsigned S = (Val >> 23) & 1; 4651 unsigned J1 = (Val >> 22) & 1; 4652 unsigned J2 = (Val >> 21) & 1; 4653 unsigned I1 = !(J1 ^ S); 4654 unsigned I2 = !(J2 ^ S); 4655 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4656 int imm32 = SignExtend32<25>(tmp << 1); 4657 4658 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4659 true, 4, Inst, Decoder)) 4660 Inst.addOperand(MCOperand::createImm(imm32)); 4661 return MCDisassembler::Success; 4662 } 4663 4664 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4665 uint64_t Address, const void *Decoder) { 4666 if (Val & ~0xf) 4667 return MCDisassembler::Fail; 4668 4669 Inst.addOperand(MCOperand::createImm(Val)); 4670 return MCDisassembler::Success; 4671 } 4672 4673 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4674 uint64_t Address, const void *Decoder) { 4675 if (Val & ~0xf) 4676 return MCDisassembler::Fail; 4677 4678 Inst.addOperand(MCOperand::createImm(Val)); 4679 return MCDisassembler::Success; 4680 } 4681 4682 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4683 uint64_t Address, const void *Decoder) { 4684 DecodeStatus S = MCDisassembler::Success; 4685 const FeatureBitset &FeatureBits = 4686 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4687 4688 if (FeatureBits[ARM::FeatureMClass]) { 4689 unsigned ValLow = Val & 0xff; 4690 4691 // Validate the SYSm value first. 4692 switch (ValLow) { 4693 case 0: // apsr 4694 case 1: // iapsr 4695 case 2: // eapsr 4696 case 3: // xpsr 4697 case 5: // ipsr 4698 case 6: // epsr 4699 case 7: // iepsr 4700 case 8: // msp 4701 case 9: // psp 4702 case 16: // primask 4703 case 20: // control 4704 break; 4705 case 17: // basepri 4706 case 18: // basepri_max 4707 case 19: // faultmask 4708 if (!(FeatureBits[ARM::HasV7Ops])) 4709 // Values basepri, basepri_max and faultmask are only valid for v7m. 4710 return MCDisassembler::Fail; 4711 break; 4712 case 0x8a: // msplim_ns 4713 case 0x8b: // psplim_ns 4714 case 0x91: // basepri_ns 4715 case 0x93: // faultmask_ns 4716 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4717 return MCDisassembler::Fail; 4718 LLVM_FALLTHROUGH; 4719 case 10: // msplim 4720 case 11: // psplim 4721 case 0x88: // msp_ns 4722 case 0x89: // psp_ns 4723 case 0x90: // primask_ns 4724 case 0x94: // control_ns 4725 case 0x98: // sp_ns 4726 if (!(FeatureBits[ARM::Feature8MSecExt])) 4727 return MCDisassembler::Fail; 4728 break; 4729 default: 4730 // Architecturally defined as unpredictable 4731 S = MCDisassembler::SoftFail; 4732 break; 4733 } 4734 4735 if (Inst.getOpcode() == ARM::t2MSR_M) { 4736 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4737 if (!(FeatureBits[ARM::HasV7Ops])) { 4738 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4739 // unpredictable. 4740 if (Mask != 2) 4741 S = MCDisassembler::SoftFail; 4742 } 4743 else { 4744 // The ARMv7-M architecture stores an additional 2-bit mask value in 4745 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4746 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4747 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4748 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4749 // only if the processor includes the DSP extension. 4750 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4751 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4752 S = MCDisassembler::SoftFail; 4753 } 4754 } 4755 } else { 4756 // A/R class 4757 if (Val == 0) 4758 return MCDisassembler::Fail; 4759 } 4760 Inst.addOperand(MCOperand::createImm(Val)); 4761 return S; 4762 } 4763 4764 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4765 uint64_t Address, const void *Decoder) { 4766 unsigned R = fieldFromInstruction(Val, 5, 1); 4767 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4768 4769 // The table of encodings for these banked registers comes from B9.2.3 of the 4770 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4771 // neater. So by fiat, these values are UNPREDICTABLE: 4772 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4773 return MCDisassembler::Fail; 4774 4775 Inst.addOperand(MCOperand::createImm(Val)); 4776 return MCDisassembler::Success; 4777 } 4778 4779 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4780 uint64_t Address, const void *Decoder) { 4781 DecodeStatus S = MCDisassembler::Success; 4782 4783 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4784 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4785 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4786 4787 if (Rn == 0xF) 4788 S = MCDisassembler::SoftFail; 4789 4790 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4791 return MCDisassembler::Fail; 4792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4793 return MCDisassembler::Fail; 4794 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4795 return MCDisassembler::Fail; 4796 4797 return S; 4798 } 4799 4800 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4801 uint64_t Address, 4802 const void *Decoder) { 4803 DecodeStatus S = MCDisassembler::Success; 4804 4805 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4806 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4807 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4808 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4809 4810 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4811 return MCDisassembler::Fail; 4812 4813 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4814 S = MCDisassembler::SoftFail; 4815 4816 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4817 return MCDisassembler::Fail; 4818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4819 return MCDisassembler::Fail; 4820 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4821 return MCDisassembler::Fail; 4822 4823 return S; 4824 } 4825 4826 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4827 uint64_t Address, const void *Decoder) { 4828 DecodeStatus S = MCDisassembler::Success; 4829 4830 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4831 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4832 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4833 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4834 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4835 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4836 4837 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4838 4839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4840 return MCDisassembler::Fail; 4841 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4842 return MCDisassembler::Fail; 4843 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4844 return MCDisassembler::Fail; 4845 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4846 return MCDisassembler::Fail; 4847 4848 return S; 4849 } 4850 4851 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4852 uint64_t Address, const void *Decoder) { 4853 DecodeStatus S = MCDisassembler::Success; 4854 4855 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4856 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4857 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4858 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4859 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4860 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4861 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4862 4863 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4864 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4865 4866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4867 return MCDisassembler::Fail; 4868 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4869 return MCDisassembler::Fail; 4870 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4871 return MCDisassembler::Fail; 4872 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4873 return MCDisassembler::Fail; 4874 4875 return S; 4876 } 4877 4878 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4879 uint64_t Address, const void *Decoder) { 4880 DecodeStatus S = MCDisassembler::Success; 4881 4882 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4883 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4884 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4885 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4886 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4887 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4888 4889 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4890 4891 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4892 return MCDisassembler::Fail; 4893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4894 return MCDisassembler::Fail; 4895 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4896 return MCDisassembler::Fail; 4897 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4898 return MCDisassembler::Fail; 4899 4900 return S; 4901 } 4902 4903 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4904 uint64_t Address, const void *Decoder) { 4905 DecodeStatus S = MCDisassembler::Success; 4906 4907 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4908 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4909 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4910 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4911 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4912 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4913 4914 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4915 4916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4917 return MCDisassembler::Fail; 4918 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4919 return MCDisassembler::Fail; 4920 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4921 return MCDisassembler::Fail; 4922 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4923 return MCDisassembler::Fail; 4924 4925 return S; 4926 } 4927 4928 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4929 uint64_t Address, const void *Decoder) { 4930 DecodeStatus S = MCDisassembler::Success; 4931 4932 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4933 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4934 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4935 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4936 unsigned size = fieldFromInstruction(Insn, 10, 2); 4937 4938 unsigned align = 0; 4939 unsigned index = 0; 4940 switch (size) { 4941 default: 4942 return MCDisassembler::Fail; 4943 case 0: 4944 if (fieldFromInstruction(Insn, 4, 1)) 4945 return MCDisassembler::Fail; // UNDEFINED 4946 index = fieldFromInstruction(Insn, 5, 3); 4947 break; 4948 case 1: 4949 if (fieldFromInstruction(Insn, 5, 1)) 4950 return MCDisassembler::Fail; // UNDEFINED 4951 index = fieldFromInstruction(Insn, 6, 2); 4952 if (fieldFromInstruction(Insn, 4, 1)) 4953 align = 2; 4954 break; 4955 case 2: 4956 if (fieldFromInstruction(Insn, 6, 1)) 4957 return MCDisassembler::Fail; // UNDEFINED 4958 index = fieldFromInstruction(Insn, 7, 1); 4959 4960 switch (fieldFromInstruction(Insn, 4, 2)) { 4961 case 0 : 4962 align = 0; break; 4963 case 3: 4964 align = 4; break; 4965 default: 4966 return MCDisassembler::Fail; 4967 } 4968 break; 4969 } 4970 4971 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4972 return MCDisassembler::Fail; 4973 if (Rm != 0xF) { // Writeback 4974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4975 return MCDisassembler::Fail; 4976 } 4977 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4978 return MCDisassembler::Fail; 4979 Inst.addOperand(MCOperand::createImm(align)); 4980 if (Rm != 0xF) { 4981 if (Rm != 0xD) { 4982 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4983 return MCDisassembler::Fail; 4984 } else 4985 Inst.addOperand(MCOperand::createReg(0)); 4986 } 4987 4988 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4989 return MCDisassembler::Fail; 4990 Inst.addOperand(MCOperand::createImm(index)); 4991 4992 return S; 4993 } 4994 4995 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4996 uint64_t Address, const void *Decoder) { 4997 DecodeStatus S = MCDisassembler::Success; 4998 4999 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5000 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5001 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5002 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5003 unsigned size = fieldFromInstruction(Insn, 10, 2); 5004 5005 unsigned align = 0; 5006 unsigned index = 0; 5007 switch (size) { 5008 default: 5009 return MCDisassembler::Fail; 5010 case 0: 5011 if (fieldFromInstruction(Insn, 4, 1)) 5012 return MCDisassembler::Fail; // UNDEFINED 5013 index = fieldFromInstruction(Insn, 5, 3); 5014 break; 5015 case 1: 5016 if (fieldFromInstruction(Insn, 5, 1)) 5017 return MCDisassembler::Fail; // UNDEFINED 5018 index = fieldFromInstruction(Insn, 6, 2); 5019 if (fieldFromInstruction(Insn, 4, 1)) 5020 align = 2; 5021 break; 5022 case 2: 5023 if (fieldFromInstruction(Insn, 6, 1)) 5024 return MCDisassembler::Fail; // UNDEFINED 5025 index = fieldFromInstruction(Insn, 7, 1); 5026 5027 switch (fieldFromInstruction(Insn, 4, 2)) { 5028 case 0: 5029 align = 0; break; 5030 case 3: 5031 align = 4; break; 5032 default: 5033 return MCDisassembler::Fail; 5034 } 5035 break; 5036 } 5037 5038 if (Rm != 0xF) { // Writeback 5039 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5040 return MCDisassembler::Fail; 5041 } 5042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5043 return MCDisassembler::Fail; 5044 Inst.addOperand(MCOperand::createImm(align)); 5045 if (Rm != 0xF) { 5046 if (Rm != 0xD) { 5047 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5048 return MCDisassembler::Fail; 5049 } else 5050 Inst.addOperand(MCOperand::createReg(0)); 5051 } 5052 5053 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5054 return MCDisassembler::Fail; 5055 Inst.addOperand(MCOperand::createImm(index)); 5056 5057 return S; 5058 } 5059 5060 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 5061 uint64_t Address, const void *Decoder) { 5062 DecodeStatus S = MCDisassembler::Success; 5063 5064 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5065 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5066 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5067 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5068 unsigned size = fieldFromInstruction(Insn, 10, 2); 5069 5070 unsigned align = 0; 5071 unsigned index = 0; 5072 unsigned inc = 1; 5073 switch (size) { 5074 default: 5075 return MCDisassembler::Fail; 5076 case 0: 5077 index = fieldFromInstruction(Insn, 5, 3); 5078 if (fieldFromInstruction(Insn, 4, 1)) 5079 align = 2; 5080 break; 5081 case 1: 5082 index = fieldFromInstruction(Insn, 6, 2); 5083 if (fieldFromInstruction(Insn, 4, 1)) 5084 align = 4; 5085 if (fieldFromInstruction(Insn, 5, 1)) 5086 inc = 2; 5087 break; 5088 case 2: 5089 if (fieldFromInstruction(Insn, 5, 1)) 5090 return MCDisassembler::Fail; // UNDEFINED 5091 index = fieldFromInstruction(Insn, 7, 1); 5092 if (fieldFromInstruction(Insn, 4, 1) != 0) 5093 align = 8; 5094 if (fieldFromInstruction(Insn, 6, 1)) 5095 inc = 2; 5096 break; 5097 } 5098 5099 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5100 return MCDisassembler::Fail; 5101 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5102 return MCDisassembler::Fail; 5103 if (Rm != 0xF) { // Writeback 5104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5105 return MCDisassembler::Fail; 5106 } 5107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5108 return MCDisassembler::Fail; 5109 Inst.addOperand(MCOperand::createImm(align)); 5110 if (Rm != 0xF) { 5111 if (Rm != 0xD) { 5112 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5113 return MCDisassembler::Fail; 5114 } else 5115 Inst.addOperand(MCOperand::createReg(0)); 5116 } 5117 5118 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5119 return MCDisassembler::Fail; 5120 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5121 return MCDisassembler::Fail; 5122 Inst.addOperand(MCOperand::createImm(index)); 5123 5124 return S; 5125 } 5126 5127 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 5128 uint64_t Address, const void *Decoder) { 5129 DecodeStatus S = MCDisassembler::Success; 5130 5131 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5132 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5133 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5134 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5135 unsigned size = fieldFromInstruction(Insn, 10, 2); 5136 5137 unsigned align = 0; 5138 unsigned index = 0; 5139 unsigned inc = 1; 5140 switch (size) { 5141 default: 5142 return MCDisassembler::Fail; 5143 case 0: 5144 index = fieldFromInstruction(Insn, 5, 3); 5145 if (fieldFromInstruction(Insn, 4, 1)) 5146 align = 2; 5147 break; 5148 case 1: 5149 index = fieldFromInstruction(Insn, 6, 2); 5150 if (fieldFromInstruction(Insn, 4, 1)) 5151 align = 4; 5152 if (fieldFromInstruction(Insn, 5, 1)) 5153 inc = 2; 5154 break; 5155 case 2: 5156 if (fieldFromInstruction(Insn, 5, 1)) 5157 return MCDisassembler::Fail; // UNDEFINED 5158 index = fieldFromInstruction(Insn, 7, 1); 5159 if (fieldFromInstruction(Insn, 4, 1) != 0) 5160 align = 8; 5161 if (fieldFromInstruction(Insn, 6, 1)) 5162 inc = 2; 5163 break; 5164 } 5165 5166 if (Rm != 0xF) { // Writeback 5167 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5168 return MCDisassembler::Fail; 5169 } 5170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5171 return MCDisassembler::Fail; 5172 Inst.addOperand(MCOperand::createImm(align)); 5173 if (Rm != 0xF) { 5174 if (Rm != 0xD) { 5175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5176 return MCDisassembler::Fail; 5177 } else 5178 Inst.addOperand(MCOperand::createReg(0)); 5179 } 5180 5181 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5182 return MCDisassembler::Fail; 5183 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5184 return MCDisassembler::Fail; 5185 Inst.addOperand(MCOperand::createImm(index)); 5186 5187 return S; 5188 } 5189 5190 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5191 uint64_t Address, const void *Decoder) { 5192 DecodeStatus S = MCDisassembler::Success; 5193 5194 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5195 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5196 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5197 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5198 unsigned size = fieldFromInstruction(Insn, 10, 2); 5199 5200 unsigned align = 0; 5201 unsigned index = 0; 5202 unsigned inc = 1; 5203 switch (size) { 5204 default: 5205 return MCDisassembler::Fail; 5206 case 0: 5207 if (fieldFromInstruction(Insn, 4, 1)) 5208 return MCDisassembler::Fail; // UNDEFINED 5209 index = fieldFromInstruction(Insn, 5, 3); 5210 break; 5211 case 1: 5212 if (fieldFromInstruction(Insn, 4, 1)) 5213 return MCDisassembler::Fail; // UNDEFINED 5214 index = fieldFromInstruction(Insn, 6, 2); 5215 if (fieldFromInstruction(Insn, 5, 1)) 5216 inc = 2; 5217 break; 5218 case 2: 5219 if (fieldFromInstruction(Insn, 4, 2)) 5220 return MCDisassembler::Fail; // UNDEFINED 5221 index = fieldFromInstruction(Insn, 7, 1); 5222 if (fieldFromInstruction(Insn, 6, 1)) 5223 inc = 2; 5224 break; 5225 } 5226 5227 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5228 return MCDisassembler::Fail; 5229 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5230 return MCDisassembler::Fail; 5231 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5232 return MCDisassembler::Fail; 5233 5234 if (Rm != 0xF) { // Writeback 5235 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5236 return MCDisassembler::Fail; 5237 } 5238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5239 return MCDisassembler::Fail; 5240 Inst.addOperand(MCOperand::createImm(align)); 5241 if (Rm != 0xF) { 5242 if (Rm != 0xD) { 5243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5244 return MCDisassembler::Fail; 5245 } else 5246 Inst.addOperand(MCOperand::createReg(0)); 5247 } 5248 5249 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5250 return MCDisassembler::Fail; 5251 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5252 return MCDisassembler::Fail; 5253 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5254 return MCDisassembler::Fail; 5255 Inst.addOperand(MCOperand::createImm(index)); 5256 5257 return S; 5258 } 5259 5260 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5261 uint64_t Address, const void *Decoder) { 5262 DecodeStatus S = MCDisassembler::Success; 5263 5264 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5265 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5266 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5267 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5268 unsigned size = fieldFromInstruction(Insn, 10, 2); 5269 5270 unsigned align = 0; 5271 unsigned index = 0; 5272 unsigned inc = 1; 5273 switch (size) { 5274 default: 5275 return MCDisassembler::Fail; 5276 case 0: 5277 if (fieldFromInstruction(Insn, 4, 1)) 5278 return MCDisassembler::Fail; // UNDEFINED 5279 index = fieldFromInstruction(Insn, 5, 3); 5280 break; 5281 case 1: 5282 if (fieldFromInstruction(Insn, 4, 1)) 5283 return MCDisassembler::Fail; // UNDEFINED 5284 index = fieldFromInstruction(Insn, 6, 2); 5285 if (fieldFromInstruction(Insn, 5, 1)) 5286 inc = 2; 5287 break; 5288 case 2: 5289 if (fieldFromInstruction(Insn, 4, 2)) 5290 return MCDisassembler::Fail; // UNDEFINED 5291 index = fieldFromInstruction(Insn, 7, 1); 5292 if (fieldFromInstruction(Insn, 6, 1)) 5293 inc = 2; 5294 break; 5295 } 5296 5297 if (Rm != 0xF) { // Writeback 5298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5299 return MCDisassembler::Fail; 5300 } 5301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5302 return MCDisassembler::Fail; 5303 Inst.addOperand(MCOperand::createImm(align)); 5304 if (Rm != 0xF) { 5305 if (Rm != 0xD) { 5306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5307 return MCDisassembler::Fail; 5308 } else 5309 Inst.addOperand(MCOperand::createReg(0)); 5310 } 5311 5312 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5313 return MCDisassembler::Fail; 5314 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5315 return MCDisassembler::Fail; 5316 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5317 return MCDisassembler::Fail; 5318 Inst.addOperand(MCOperand::createImm(index)); 5319 5320 return S; 5321 } 5322 5323 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5324 uint64_t Address, const void *Decoder) { 5325 DecodeStatus S = MCDisassembler::Success; 5326 5327 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5328 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5329 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5330 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5331 unsigned size = fieldFromInstruction(Insn, 10, 2); 5332 5333 unsigned align = 0; 5334 unsigned index = 0; 5335 unsigned inc = 1; 5336 switch (size) { 5337 default: 5338 return MCDisassembler::Fail; 5339 case 0: 5340 if (fieldFromInstruction(Insn, 4, 1)) 5341 align = 4; 5342 index = fieldFromInstruction(Insn, 5, 3); 5343 break; 5344 case 1: 5345 if (fieldFromInstruction(Insn, 4, 1)) 5346 align = 8; 5347 index = fieldFromInstruction(Insn, 6, 2); 5348 if (fieldFromInstruction(Insn, 5, 1)) 5349 inc = 2; 5350 break; 5351 case 2: 5352 switch (fieldFromInstruction(Insn, 4, 2)) { 5353 case 0: 5354 align = 0; break; 5355 case 3: 5356 return MCDisassembler::Fail; 5357 default: 5358 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5359 } 5360 5361 index = fieldFromInstruction(Insn, 7, 1); 5362 if (fieldFromInstruction(Insn, 6, 1)) 5363 inc = 2; 5364 break; 5365 } 5366 5367 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5368 return MCDisassembler::Fail; 5369 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5370 return MCDisassembler::Fail; 5371 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5372 return MCDisassembler::Fail; 5373 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5374 return MCDisassembler::Fail; 5375 5376 if (Rm != 0xF) { // Writeback 5377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5378 return MCDisassembler::Fail; 5379 } 5380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5381 return MCDisassembler::Fail; 5382 Inst.addOperand(MCOperand::createImm(align)); 5383 if (Rm != 0xF) { 5384 if (Rm != 0xD) { 5385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5386 return MCDisassembler::Fail; 5387 } else 5388 Inst.addOperand(MCOperand::createReg(0)); 5389 } 5390 5391 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5392 return MCDisassembler::Fail; 5393 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5394 return MCDisassembler::Fail; 5395 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5396 return MCDisassembler::Fail; 5397 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5398 return MCDisassembler::Fail; 5399 Inst.addOperand(MCOperand::createImm(index)); 5400 5401 return S; 5402 } 5403 5404 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5405 uint64_t Address, const void *Decoder) { 5406 DecodeStatus S = MCDisassembler::Success; 5407 5408 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5409 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5410 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5411 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5412 unsigned size = fieldFromInstruction(Insn, 10, 2); 5413 5414 unsigned align = 0; 5415 unsigned index = 0; 5416 unsigned inc = 1; 5417 switch (size) { 5418 default: 5419 return MCDisassembler::Fail; 5420 case 0: 5421 if (fieldFromInstruction(Insn, 4, 1)) 5422 align = 4; 5423 index = fieldFromInstruction(Insn, 5, 3); 5424 break; 5425 case 1: 5426 if (fieldFromInstruction(Insn, 4, 1)) 5427 align = 8; 5428 index = fieldFromInstruction(Insn, 6, 2); 5429 if (fieldFromInstruction(Insn, 5, 1)) 5430 inc = 2; 5431 break; 5432 case 2: 5433 switch (fieldFromInstruction(Insn, 4, 2)) { 5434 case 0: 5435 align = 0; break; 5436 case 3: 5437 return MCDisassembler::Fail; 5438 default: 5439 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5440 } 5441 5442 index = fieldFromInstruction(Insn, 7, 1); 5443 if (fieldFromInstruction(Insn, 6, 1)) 5444 inc = 2; 5445 break; 5446 } 5447 5448 if (Rm != 0xF) { // Writeback 5449 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5450 return MCDisassembler::Fail; 5451 } 5452 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5453 return MCDisassembler::Fail; 5454 Inst.addOperand(MCOperand::createImm(align)); 5455 if (Rm != 0xF) { 5456 if (Rm != 0xD) { 5457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5458 return MCDisassembler::Fail; 5459 } else 5460 Inst.addOperand(MCOperand::createReg(0)); 5461 } 5462 5463 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5464 return MCDisassembler::Fail; 5465 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5466 return MCDisassembler::Fail; 5467 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5468 return MCDisassembler::Fail; 5469 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5470 return MCDisassembler::Fail; 5471 Inst.addOperand(MCOperand::createImm(index)); 5472 5473 return S; 5474 } 5475 5476 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5477 uint64_t Address, const void *Decoder) { 5478 DecodeStatus S = MCDisassembler::Success; 5479 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5480 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5481 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5482 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5483 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5484 5485 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5486 S = MCDisassembler::SoftFail; 5487 5488 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5489 return MCDisassembler::Fail; 5490 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5491 return MCDisassembler::Fail; 5492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5493 return MCDisassembler::Fail; 5494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5495 return MCDisassembler::Fail; 5496 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5497 return MCDisassembler::Fail; 5498 5499 return S; 5500 } 5501 5502 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5503 uint64_t Address, const void *Decoder) { 5504 DecodeStatus S = MCDisassembler::Success; 5505 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5506 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5507 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5508 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5509 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5510 5511 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5512 S = MCDisassembler::SoftFail; 5513 5514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5515 return MCDisassembler::Fail; 5516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5517 return MCDisassembler::Fail; 5518 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5519 return MCDisassembler::Fail; 5520 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5521 return MCDisassembler::Fail; 5522 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5523 return MCDisassembler::Fail; 5524 5525 return S; 5526 } 5527 5528 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5529 uint64_t Address, const void *Decoder) { 5530 DecodeStatus S = MCDisassembler::Success; 5531 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5532 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5533 5534 if (pred == 0xF) { 5535 pred = 0xE; 5536 S = MCDisassembler::SoftFail; 5537 } 5538 5539 if (mask == 0x0) 5540 return MCDisassembler::Fail; 5541 5542 // IT masks are encoded as a sequence of replacement low-order bits 5543 // for the condition code. So if the low bit of the starting 5544 // condition code is 1, then we have to flip all the bits above the 5545 // terminating bit (which is the lowest 1 bit). 5546 if (pred & 1) { 5547 unsigned LowBit = mask & -mask; 5548 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5549 mask ^= BitsAboveLowBit; 5550 } 5551 5552 Inst.addOperand(MCOperand::createImm(pred)); 5553 Inst.addOperand(MCOperand::createImm(mask)); 5554 return S; 5555 } 5556 5557 static DecodeStatus 5558 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5559 uint64_t Address, const void *Decoder) { 5560 DecodeStatus S = MCDisassembler::Success; 5561 5562 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5563 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5564 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5565 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5566 unsigned W = fieldFromInstruction(Insn, 21, 1); 5567 unsigned U = fieldFromInstruction(Insn, 23, 1); 5568 unsigned P = fieldFromInstruction(Insn, 24, 1); 5569 bool writeback = (W == 1) | (P == 0); 5570 5571 addr |= (U << 8) | (Rn << 9); 5572 5573 if (writeback && (Rn == Rt || Rn == Rt2)) 5574 Check(S, MCDisassembler::SoftFail); 5575 if (Rt == Rt2) 5576 Check(S, MCDisassembler::SoftFail); 5577 5578 // Rt 5579 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5580 return MCDisassembler::Fail; 5581 // Rt2 5582 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5583 return MCDisassembler::Fail; 5584 // Writeback operand 5585 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5586 return MCDisassembler::Fail; 5587 // addr 5588 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5589 return MCDisassembler::Fail; 5590 5591 return S; 5592 } 5593 5594 static DecodeStatus 5595 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5596 uint64_t Address, const void *Decoder) { 5597 DecodeStatus S = MCDisassembler::Success; 5598 5599 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5600 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5601 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5602 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5603 unsigned W = fieldFromInstruction(Insn, 21, 1); 5604 unsigned U = fieldFromInstruction(Insn, 23, 1); 5605 unsigned P = fieldFromInstruction(Insn, 24, 1); 5606 bool writeback = (W == 1) | (P == 0); 5607 5608 addr |= (U << 8) | (Rn << 9); 5609 5610 if (writeback && (Rn == Rt || Rn == Rt2)) 5611 Check(S, MCDisassembler::SoftFail); 5612 5613 // Writeback operand 5614 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5615 return MCDisassembler::Fail; 5616 // Rt 5617 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5618 return MCDisassembler::Fail; 5619 // Rt2 5620 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5621 return MCDisassembler::Fail; 5622 // addr 5623 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5624 return MCDisassembler::Fail; 5625 5626 return S; 5627 } 5628 5629 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5630 uint64_t Address, const void *Decoder) { 5631 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5632 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5633 if (sign1 != sign2) return MCDisassembler::Fail; 5634 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5635 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5636 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5637 5638 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5639 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5640 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5641 // If sign, then it is decreasing the address. 5642 if (sign1) { 5643 // Following ARMv7 Architecture Manual, when the offset 5644 // is zero, it is decoded as a subw, not as a adr.w 5645 if (!Val) { 5646 Inst.setOpcode(ARM::t2SUBri12); 5647 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5648 } else 5649 Val = -Val; 5650 } 5651 Inst.addOperand(MCOperand::createImm(Val)); 5652 return S; 5653 } 5654 5655 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5656 uint64_t Address, 5657 const void *Decoder) { 5658 DecodeStatus S = MCDisassembler::Success; 5659 5660 // Shift of "asr #32" is not allowed in Thumb2 mode. 5661 if (Val == 0x20) S = MCDisassembler::Fail; 5662 Inst.addOperand(MCOperand::createImm(Val)); 5663 return S; 5664 } 5665 5666 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5667 uint64_t Address, const void *Decoder) { 5668 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5669 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5670 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5671 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5672 5673 if (pred == 0xF) 5674 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5675 5676 DecodeStatus S = MCDisassembler::Success; 5677 5678 if (Rt == Rn || Rn == Rt2) 5679 S = MCDisassembler::SoftFail; 5680 5681 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5682 return MCDisassembler::Fail; 5683 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5684 return MCDisassembler::Fail; 5685 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5686 return MCDisassembler::Fail; 5687 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5688 return MCDisassembler::Fail; 5689 5690 return S; 5691 } 5692 5693 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5694 uint64_t Address, const void *Decoder) { 5695 const FeatureBitset &featureBits = 5696 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5697 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5698 5699 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5700 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5701 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5702 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5703 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5704 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5705 unsigned op = fieldFromInstruction(Insn, 5, 1); 5706 5707 DecodeStatus S = MCDisassembler::Success; 5708 5709 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5710 if (!(imm & 0x38)) { 5711 if (cmode == 0xF) { 5712 if (op == 1) return MCDisassembler::Fail; 5713 Inst.setOpcode(ARM::VMOVv2f32); 5714 } 5715 if (hasFullFP16) { 5716 if (cmode == 0xE) { 5717 if (op == 1) { 5718 Inst.setOpcode(ARM::VMOVv1i64); 5719 } else { 5720 Inst.setOpcode(ARM::VMOVv8i8); 5721 } 5722 } 5723 if (cmode == 0xD) { 5724 if (op == 1) { 5725 Inst.setOpcode(ARM::VMVNv2i32); 5726 } else { 5727 Inst.setOpcode(ARM::VMOVv2i32); 5728 } 5729 } 5730 if (cmode == 0xC) { 5731 if (op == 1) { 5732 Inst.setOpcode(ARM::VMVNv2i32); 5733 } else { 5734 Inst.setOpcode(ARM::VMOVv2i32); 5735 } 5736 } 5737 } 5738 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5739 } 5740 5741 if (!(imm & 0x20)) return MCDisassembler::Fail; 5742 5743 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5744 return MCDisassembler::Fail; 5745 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5746 return MCDisassembler::Fail; 5747 Inst.addOperand(MCOperand::createImm(64 - imm)); 5748 5749 return S; 5750 } 5751 5752 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5753 uint64_t Address, const void *Decoder) { 5754 const FeatureBitset &featureBits = 5755 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5756 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5757 5758 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5759 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5760 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5761 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5762 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5763 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5764 unsigned op = fieldFromInstruction(Insn, 5, 1); 5765 5766 DecodeStatus S = MCDisassembler::Success; 5767 5768 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5769 if (!(imm & 0x38)) { 5770 if (cmode == 0xF) { 5771 if (op == 1) return MCDisassembler::Fail; 5772 Inst.setOpcode(ARM::VMOVv4f32); 5773 } 5774 if (hasFullFP16) { 5775 if (cmode == 0xE) { 5776 if (op == 1) { 5777 Inst.setOpcode(ARM::VMOVv2i64); 5778 } else { 5779 Inst.setOpcode(ARM::VMOVv16i8); 5780 } 5781 } 5782 if (cmode == 0xD) { 5783 if (op == 1) { 5784 Inst.setOpcode(ARM::VMVNv4i32); 5785 } else { 5786 Inst.setOpcode(ARM::VMOVv4i32); 5787 } 5788 } 5789 if (cmode == 0xC) { 5790 if (op == 1) { 5791 Inst.setOpcode(ARM::VMVNv4i32); 5792 } else { 5793 Inst.setOpcode(ARM::VMOVv4i32); 5794 } 5795 } 5796 } 5797 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5798 } 5799 5800 if (!(imm & 0x20)) return MCDisassembler::Fail; 5801 5802 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5803 return MCDisassembler::Fail; 5804 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5805 return MCDisassembler::Fail; 5806 Inst.addOperand(MCOperand::createImm(64 - imm)); 5807 5808 return S; 5809 } 5810 5811 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5812 unsigned Insn, 5813 uint64_t Address, 5814 const void *Decoder) { 5815 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5816 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5817 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5818 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5819 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5820 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5821 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5822 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5823 5824 DecodeStatus S = MCDisassembler::Success; 5825 5826 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5827 5828 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5829 return MCDisassembler::Fail; 5830 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5831 return MCDisassembler::Fail; 5832 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5833 return MCDisassembler::Fail; 5834 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5835 return MCDisassembler::Fail; 5836 // The lane index does not have any bits in the encoding, because it can only 5837 // be 0. 5838 Inst.addOperand(MCOperand::createImm(0)); 5839 Inst.addOperand(MCOperand::createImm(rotate)); 5840 5841 return S; 5842 } 5843 5844 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5845 uint64_t Address, const void *Decoder) { 5846 DecodeStatus S = MCDisassembler::Success; 5847 5848 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5849 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5850 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5851 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5852 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5853 5854 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5855 S = MCDisassembler::SoftFail; 5856 5857 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5858 return MCDisassembler::Fail; 5859 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5860 return MCDisassembler::Fail; 5861 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5862 return MCDisassembler::Fail; 5863 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5864 return MCDisassembler::Fail; 5865 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5866 return MCDisassembler::Fail; 5867 5868 return S; 5869 } 5870 5871 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5872 uint64_t Address, const void *Decoder) { 5873 DecodeStatus S = MCDisassembler::Success; 5874 5875 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5876 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5877 unsigned cop = fieldFromInstruction(Val, 8, 4); 5878 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5879 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5880 5881 if ((cop & ~0x1) == 0xa) 5882 return MCDisassembler::Fail; 5883 5884 if (Rt == Rt2) 5885 S = MCDisassembler::SoftFail; 5886 5887 // We have to check if the instruction is MRRC2 5888 // or MCRR2 when constructing the operands for 5889 // Inst. Reason is because MRRC2 stores to two 5890 // registers so it's tablegen desc has has two 5891 // outputs whereas MCRR doesn't store to any 5892 // registers so all of it's operands are listed 5893 // as inputs, therefore the operand order for 5894 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5895 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5896 5897 if (Inst.getOpcode() == ARM::MRRC2) { 5898 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5899 return MCDisassembler::Fail; 5900 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5901 return MCDisassembler::Fail; 5902 } 5903 Inst.addOperand(MCOperand::createImm(cop)); 5904 Inst.addOperand(MCOperand::createImm(opc1)); 5905 if (Inst.getOpcode() == ARM::MCRR2) { 5906 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5907 return MCDisassembler::Fail; 5908 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5909 return MCDisassembler::Fail; 5910 } 5911 Inst.addOperand(MCOperand::createImm(CRm)); 5912 5913 return S; 5914 } 5915 5916 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5917 uint64_t Address, 5918 const void *Decoder) { 5919 const FeatureBitset &featureBits = 5920 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5921 DecodeStatus S = MCDisassembler::Success; 5922 5923 // Add explicit operand for the destination sysreg, for cases where 5924 // we have to model it for code generation purposes. 5925 switch (Inst.getOpcode()) { 5926 case ARM::VMSR_FPSCR_NZCVQC: 5927 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5928 break; 5929 case ARM::VMSR_P0: 5930 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5931 break; 5932 } 5933 5934 if (Inst.getOpcode() != ARM::FMSTAT) { 5935 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5936 5937 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5938 if (Rt == 13 || Rt == 15) 5939 S = MCDisassembler::SoftFail; 5940 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5941 } else 5942 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5943 } 5944 5945 // Add explicit operand for the source sysreg, similarly to above. 5946 switch (Inst.getOpcode()) { 5947 case ARM::VMRS_FPSCR_NZCVQC: 5948 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5949 break; 5950 case ARM::VMRS_P0: 5951 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5952 break; 5953 } 5954 5955 if (featureBits[ARM::ModeThumb]) { 5956 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5957 Inst.addOperand(MCOperand::createReg(0)); 5958 } else { 5959 unsigned pred = fieldFromInstruction(Val, 28, 4); 5960 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5961 return MCDisassembler::Fail; 5962 } 5963 5964 return S; 5965 } 5966 5967 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 5968 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5969 uint64_t Address, 5970 const void *Decoder) { 5971 DecodeStatus S = MCDisassembler::Success; 5972 if (Val == 0 && !zeroPermitted) 5973 S = MCDisassembler::Fail; 5974 5975 uint64_t DecVal; 5976 if (isSigned) 5977 DecVal = SignExtend32<size + 1>(Val << 1); 5978 else 5979 DecVal = (Val << 1); 5980 5981 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5982 Decoder)) 5983 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5984 return S; 5985 } 5986 5987 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5988 uint64_t Address, 5989 const void *Decoder) { 5990 5991 uint64_t LocImm = Inst.getOperand(0).getImm(); 5992 Val = LocImm + (2 << Val); 5993 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5994 Decoder)) 5995 Inst.addOperand(MCOperand::createImm(Val)); 5996 return MCDisassembler::Success; 5997 } 5998 5999 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 6000 uint64_t Address, 6001 const void *Decoder) { 6002 if (Val >= ARMCC::AL) // also exclude the non-condition NV 6003 return MCDisassembler::Fail; 6004 Inst.addOperand(MCOperand::createImm(Val)); 6005 return MCDisassembler::Success; 6006 } 6007 6008 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 6009 const void *Decoder) { 6010 DecodeStatus S = MCDisassembler::Success; 6011 6012 if (Inst.getOpcode() == ARM::MVE_LCTP) 6013 return S; 6014 6015 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6016 fieldFromInstruction(Insn, 1, 10) << 1; 6017 switch (Inst.getOpcode()) { 6018 case ARM::t2LEUpdate: 6019 case ARM::MVE_LETP: 6020 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6021 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6022 LLVM_FALLTHROUGH; 6023 case ARM::t2LE: 6024 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6025 Inst, Imm, Address, Decoder))) 6026 return MCDisassembler::Fail; 6027 break; 6028 case ARM::t2WLS: 6029 case ARM::MVE_WLSTP_8: 6030 case ARM::MVE_WLSTP_16: 6031 case ARM::MVE_WLSTP_32: 6032 case ARM::MVE_WLSTP_64: 6033 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6034 if (!Check(S, 6035 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6036 Address, Decoder)) || 6037 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6038 Inst, Imm, Address, Decoder))) 6039 return MCDisassembler::Fail; 6040 break; 6041 case ARM::t2DLS: 6042 case ARM::MVE_DLSTP_8: 6043 case ARM::MVE_DLSTP_16: 6044 case ARM::MVE_DLSTP_32: 6045 case ARM::MVE_DLSTP_64: 6046 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6047 if (Rn == 0xF) { 6048 // Enforce all the rest of the instruction bits in LCTP, which 6049 // won't have been reliably checked based on LCTP's own tablegen 6050 // record, because we came to this decode by a roundabout route. 6051 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6052 if ((Insn & ~SBZMask) != CanonicalLCTP) 6053 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6054 if (Insn != CanonicalLCTP) 6055 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6056 6057 Inst.setOpcode(ARM::MVE_LCTP); 6058 } else { 6059 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6060 if (!Check(S, DecoderGPRRegisterClass(Inst, 6061 fieldFromInstruction(Insn, 16, 4), 6062 Address, Decoder))) 6063 return MCDisassembler::Fail; 6064 } 6065 break; 6066 } 6067 return S; 6068 } 6069 6070 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6071 uint64_t Address, 6072 const void *Decoder) { 6073 DecodeStatus S = MCDisassembler::Success; 6074 6075 if (Val == 0) 6076 Val = 32; 6077 6078 Inst.addOperand(MCOperand::createImm(Val)); 6079 6080 return S; 6081 } 6082 6083 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6084 uint64_t Address, const void *Decoder) { 6085 if ((RegNo) + 1 > 11) 6086 return MCDisassembler::Fail; 6087 6088 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6089 Inst.addOperand(MCOperand::createReg(Register)); 6090 return MCDisassembler::Success; 6091 } 6092 6093 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6094 uint64_t Address, const void *Decoder) { 6095 if ((RegNo) > 14) 6096 return MCDisassembler::Fail; 6097 6098 unsigned Register = GPRDecoderTable[(RegNo)]; 6099 Inst.addOperand(MCOperand::createReg(Register)); 6100 return MCDisassembler::Success; 6101 } 6102 6103 static DecodeStatus 6104 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6105 uint64_t Address, const void *Decoder) { 6106 if (RegNo == 15) { 6107 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6108 return MCDisassembler::Success; 6109 } 6110 6111 unsigned Register = GPRDecoderTable[RegNo]; 6112 Inst.addOperand(MCOperand::createReg(Register)); 6113 6114 if (RegNo == 13) 6115 return MCDisassembler::SoftFail; 6116 6117 return MCDisassembler::Success; 6118 } 6119 6120 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6121 const void *Decoder) { 6122 DecodeStatus S = MCDisassembler::Success; 6123 6124 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6125 Inst.addOperand(MCOperand::createReg(0)); 6126 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6127 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6128 (fieldFromInstruction(Insn, 12, 4) << 8) | 6129 (fieldFromInstruction(Insn, 22, 1) << 12); 6130 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6131 return MCDisassembler::Fail; 6132 } 6133 } else { 6134 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6135 (fieldFromInstruction(Insn, 22, 1) << 8) | 6136 (fieldFromInstruction(Insn, 12, 4) << 9); 6137 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6138 return MCDisassembler::Fail; 6139 } 6140 } 6141 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6142 6143 return S; 6144 } 6145 6146 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6147 uint64_t Address, 6148 const void *Decoder) { 6149 if (RegNo > 7) 6150 return MCDisassembler::Fail; 6151 6152 unsigned Register = QPRDecoderTable[RegNo]; 6153 Inst.addOperand(MCOperand::createReg(Register)); 6154 return MCDisassembler::Success; 6155 } 6156 6157 static const uint16_t QQPRDecoderTable[] = { 6158 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6159 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6160 }; 6161 6162 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6163 uint64_t Address, 6164 const void *Decoder) { 6165 if (RegNo > 6) 6166 return MCDisassembler::Fail; 6167 6168 unsigned Register = QQPRDecoderTable[RegNo]; 6169 Inst.addOperand(MCOperand::createReg(Register)); 6170 return MCDisassembler::Success; 6171 } 6172 6173 static const uint16_t QQQQPRDecoderTable[] = { 6174 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6175 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6176 }; 6177 6178 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6179 uint64_t Address, 6180 const void *Decoder) { 6181 if (RegNo > 4) 6182 return MCDisassembler::Fail; 6183 6184 unsigned Register = QQQQPRDecoderTable[RegNo]; 6185 Inst.addOperand(MCOperand::createReg(Register)); 6186 return MCDisassembler::Success; 6187 } 6188 6189 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6190 uint64_t Address, 6191 const void *Decoder) { 6192 DecodeStatus S = MCDisassembler::Success; 6193 6194 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6195 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6196 // 't' as 0 and finish with a 1. 6197 unsigned Imm = 0; 6198 // We always start with a 't'. 6199 unsigned CurBit = 0; 6200 for (int i = 3; i >= 0; --i) { 6201 // If the bit we are looking at is not the same as last one, invert the 6202 // CurBit, if it is the same leave it as is. 6203 CurBit ^= (Val >> i) & 1U; 6204 6205 // Encode the CurBit at the right place in the immediate. 6206 Imm |= (CurBit << i); 6207 6208 // If we are done, finish the encoding with a 1. 6209 if ((Val & ~(~0U << i)) == 0) { 6210 Imm |= 1U << i; 6211 break; 6212 } 6213 } 6214 6215 Inst.addOperand(MCOperand::createImm(Imm)); 6216 6217 return S; 6218 } 6219 6220 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6221 uint64_t Address, const void *Decoder) { 6222 // The vpred_r operand type includes an MQPR register field derived 6223 // from the encoding. But we don't actually want to add an operand 6224 // to the MCInst at this stage, because AddThumbPredicate will do it 6225 // later, and will infer the register number from the TIED_TO 6226 // constraint. So this is a deliberately empty decoder method that 6227 // will inhibit the auto-generated disassembly code from adding an 6228 // operand at all. 6229 return MCDisassembler::Success; 6230 } 6231 6232 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6233 unsigned Val, 6234 uint64_t Address, 6235 const void *Decoder) { 6236 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6237 return MCDisassembler::Success; 6238 } 6239 6240 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6241 unsigned Val, 6242 uint64_t Address, 6243 const void *Decoder) { 6244 unsigned Code; 6245 switch (Val & 0x3) { 6246 case 0: 6247 Code = ARMCC::GE; 6248 break; 6249 case 1: 6250 Code = ARMCC::LT; 6251 break; 6252 case 2: 6253 Code = ARMCC::GT; 6254 break; 6255 case 3: 6256 Code = ARMCC::LE; 6257 break; 6258 } 6259 Inst.addOperand(MCOperand::createImm(Code)); 6260 return MCDisassembler::Success; 6261 } 6262 6263 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6264 unsigned Val, 6265 uint64_t Address, 6266 const void *Decoder) { 6267 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6268 return MCDisassembler::Success; 6269 } 6270 6271 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6272 uint64_t Address, 6273 const void *Decoder) { 6274 unsigned Code; 6275 switch (Val) { 6276 default: 6277 return MCDisassembler::Fail; 6278 case 0: 6279 Code = ARMCC::EQ; 6280 break; 6281 case 1: 6282 Code = ARMCC::NE; 6283 break; 6284 case 4: 6285 Code = ARMCC::GE; 6286 break; 6287 case 5: 6288 Code = ARMCC::LT; 6289 break; 6290 case 6: 6291 Code = ARMCC::GT; 6292 break; 6293 case 7: 6294 Code = ARMCC::LE; 6295 break; 6296 } 6297 6298 Inst.addOperand(MCOperand::createImm(Code)); 6299 return MCDisassembler::Success; 6300 } 6301 6302 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6303 uint64_t Address, const void *Decoder) { 6304 DecodeStatus S = MCDisassembler::Success; 6305 6306 unsigned DecodedVal = 64 - Val; 6307 6308 switch (Inst.getOpcode()) { 6309 case ARM::MVE_VCVTf16s16_fix: 6310 case ARM::MVE_VCVTs16f16_fix: 6311 case ARM::MVE_VCVTf16u16_fix: 6312 case ARM::MVE_VCVTu16f16_fix: 6313 if (DecodedVal > 16) 6314 return MCDisassembler::Fail; 6315 break; 6316 case ARM::MVE_VCVTf32s32_fix: 6317 case ARM::MVE_VCVTs32f32_fix: 6318 case ARM::MVE_VCVTf32u32_fix: 6319 case ARM::MVE_VCVTu32f32_fix: 6320 if (DecodedVal > 32) 6321 return MCDisassembler::Fail; 6322 break; 6323 } 6324 6325 Inst.addOperand(MCOperand::createImm(64 - Val)); 6326 6327 return S; 6328 } 6329 6330 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6331 switch (Opcode) { 6332 case ARM::VSTR_P0_off: 6333 case ARM::VSTR_P0_pre: 6334 case ARM::VSTR_P0_post: 6335 case ARM::VLDR_P0_off: 6336 case ARM::VLDR_P0_pre: 6337 case ARM::VLDR_P0_post: 6338 return ARM::P0; 6339 default: 6340 return 0; 6341 } 6342 } 6343 6344 template<bool Writeback> 6345 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6346 uint64_t Address, 6347 const void *Decoder) { 6348 switch (Inst.getOpcode()) { 6349 case ARM::VSTR_FPSCR_pre: 6350 case ARM::VSTR_FPSCR_NZCVQC_pre: 6351 case ARM::VLDR_FPSCR_pre: 6352 case ARM::VLDR_FPSCR_NZCVQC_pre: 6353 case ARM::VSTR_FPSCR_off: 6354 case ARM::VSTR_FPSCR_NZCVQC_off: 6355 case ARM::VLDR_FPSCR_off: 6356 case ARM::VLDR_FPSCR_NZCVQC_off: 6357 case ARM::VSTR_FPSCR_post: 6358 case ARM::VSTR_FPSCR_NZCVQC_post: 6359 case ARM::VLDR_FPSCR_post: 6360 case ARM::VLDR_FPSCR_NZCVQC_post: 6361 const FeatureBitset &featureBits = 6362 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6363 6364 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6365 return MCDisassembler::Fail; 6366 } 6367 6368 DecodeStatus S = MCDisassembler::Success; 6369 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6370 Inst.addOperand(MCOperand::createReg(Sysreg)); 6371 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6372 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6373 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6374 6375 if (Writeback) { 6376 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6377 return MCDisassembler::Fail; 6378 } 6379 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6380 return MCDisassembler::Fail; 6381 6382 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6383 Inst.addOperand(MCOperand::createReg(0)); 6384 6385 return S; 6386 } 6387 6388 static inline DecodeStatus DecodeMVE_MEM_pre( 6389 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, 6390 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6391 DecodeStatus S = MCDisassembler::Success; 6392 6393 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6394 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6395 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6396 6397 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6398 return MCDisassembler::Fail; 6399 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6400 return MCDisassembler::Fail; 6401 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6402 return MCDisassembler::Fail; 6403 6404 return S; 6405 } 6406 6407 template <int shift> 6408 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6409 uint64_t Address, const void *Decoder) { 6410 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6411 fieldFromInstruction(Val, 16, 3), 6412 DecodetGPRRegisterClass, 6413 DecodeTAddrModeImm7<shift>); 6414 } 6415 6416 template <int shift> 6417 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6418 uint64_t Address, const void *Decoder) { 6419 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6420 fieldFromInstruction(Val, 16, 4), 6421 DecoderGPRRegisterClass, 6422 DecodeT2AddrModeImm7<shift,1>); 6423 } 6424 6425 template <int shift> 6426 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6427 uint64_t Address, const void *Decoder) { 6428 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6429 fieldFromInstruction(Val, 17, 3), 6430 DecodeMQPRRegisterClass, 6431 DecodeMveAddrModeQ<shift>); 6432 } 6433 6434 template<unsigned MinLog, unsigned MaxLog> 6435 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6436 uint64_t Address, 6437 const void *Decoder) { 6438 DecodeStatus S = MCDisassembler::Success; 6439 6440 if (Val < MinLog || Val > MaxLog) 6441 return MCDisassembler::Fail; 6442 6443 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6444 return S; 6445 } 6446 6447 template<unsigned start> 6448 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6449 uint64_t Address, 6450 const void *Decoder) { 6451 DecodeStatus S = MCDisassembler::Success; 6452 6453 Inst.addOperand(MCOperand::createImm(start + Val)); 6454 6455 return S; 6456 } 6457 6458 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6459 uint64_t Address, const void *Decoder) { 6460 DecodeStatus S = MCDisassembler::Success; 6461 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6462 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6463 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6464 fieldFromInstruction(Insn, 13, 3)); 6465 unsigned index = fieldFromInstruction(Insn, 4, 1); 6466 6467 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6468 return MCDisassembler::Fail; 6469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6470 return MCDisassembler::Fail; 6471 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6472 return MCDisassembler::Fail; 6473 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6474 return MCDisassembler::Fail; 6475 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6476 return MCDisassembler::Fail; 6477 6478 return S; 6479 } 6480 6481 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6482 uint64_t Address, const void *Decoder) { 6483 DecodeStatus S = MCDisassembler::Success; 6484 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6485 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6486 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6487 fieldFromInstruction(Insn, 13, 3)); 6488 unsigned index = fieldFromInstruction(Insn, 4, 1); 6489 6490 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6491 return MCDisassembler::Fail; 6492 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6493 return MCDisassembler::Fail; 6494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6495 return MCDisassembler::Fail; 6496 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6497 return MCDisassembler::Fail; 6498 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6499 return MCDisassembler::Fail; 6500 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6501 return MCDisassembler::Fail; 6502 6503 return S; 6504 } 6505 6506 static DecodeStatus DecodeMVEOverlappingLongShift( 6507 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6508 DecodeStatus S = MCDisassembler::Success; 6509 6510 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6511 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6512 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6513 6514 if (RdaHi == 14) { 6515 // This value of RdaHi (really indicating pc, because RdaHi has to 6516 // be an odd-numbered register, so the low bit will be set by the 6517 // decode function below) indicates that we must decode as SQRSHR 6518 // or UQRSHL, which both have a single Rda register field with all 6519 // four bits. 6520 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6521 6522 switch (Inst.getOpcode()) { 6523 case ARM::MVE_ASRLr: 6524 case ARM::MVE_SQRSHRL: 6525 Inst.setOpcode(ARM::MVE_SQRSHR); 6526 break; 6527 case ARM::MVE_LSLLr: 6528 case ARM::MVE_UQRSHLL: 6529 Inst.setOpcode(ARM::MVE_UQRSHL); 6530 break; 6531 default: 6532 llvm_unreachable("Unexpected starting opcode!"); 6533 } 6534 6535 // Rda as output parameter 6536 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6537 return MCDisassembler::Fail; 6538 6539 // Rda again as input parameter 6540 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6541 return MCDisassembler::Fail; 6542 6543 // Rm, the amount to shift by 6544 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6545 return MCDisassembler::Fail; 6546 6547 if (fieldFromInstruction (Insn, 6, 3) != 4) 6548 return MCDisassembler::SoftFail; 6549 6550 if (Rda == Rm) 6551 return MCDisassembler::SoftFail; 6552 6553 return S; 6554 } 6555 6556 // Otherwise, we decode as whichever opcode our caller has already 6557 // put into Inst. Those all look the same: 6558 6559 // RdaLo,RdaHi as output parameters 6560 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6561 return MCDisassembler::Fail; 6562 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6563 return MCDisassembler::Fail; 6564 6565 // RdaLo,RdaHi again as input parameters 6566 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6567 return MCDisassembler::Fail; 6568 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6569 return MCDisassembler::Fail; 6570 6571 // Rm, the amount to shift by 6572 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6573 return MCDisassembler::Fail; 6574 6575 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6576 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6577 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6578 // Saturate, the bit position for saturation 6579 Inst.addOperand(MCOperand::createImm(Saturate)); 6580 } 6581 6582 return S; 6583 } 6584 6585 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6586 const void *Decoder) { 6587 DecodeStatus S = MCDisassembler::Success; 6588 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6589 fieldFromInstruction(Insn, 13, 3)); 6590 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6591 fieldFromInstruction(Insn, 1, 3)); 6592 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6593 6594 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6595 return MCDisassembler::Fail; 6596 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6597 return MCDisassembler::Fail; 6598 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6599 return MCDisassembler::Fail; 6600 6601 return S; 6602 } 6603 6604 template<bool scalar, OperandDecoder predicate_decoder> 6605 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6606 const void *Decoder) { 6607 DecodeStatus S = MCDisassembler::Success; 6608 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6609 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6610 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6611 return MCDisassembler::Fail; 6612 6613 unsigned fc; 6614 6615 if (scalar) { 6616 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6617 fieldFromInstruction(Insn, 7, 1) | 6618 fieldFromInstruction(Insn, 5, 1) << 1; 6619 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6620 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6621 return MCDisassembler::Fail; 6622 } else { 6623 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6624 fieldFromInstruction(Insn, 7, 1) | 6625 fieldFromInstruction(Insn, 0, 1) << 1; 6626 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6627 fieldFromInstruction(Insn, 1, 3); 6628 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6629 return MCDisassembler::Fail; 6630 } 6631 6632 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6633 return MCDisassembler::Fail; 6634 6635 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6636 Inst.addOperand(MCOperand::createReg(0)); 6637 Inst.addOperand(MCOperand::createImm(0)); 6638 6639 return S; 6640 } 6641 6642 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6643 const void *Decoder) { 6644 DecodeStatus S = MCDisassembler::Success; 6645 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6646 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6647 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6648 return MCDisassembler::Fail; 6649 return S; 6650 } 6651 6652 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, 6653 const void *Decoder) { 6654 DecodeStatus S = MCDisassembler::Success; 6655 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6656 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6657 return S; 6658 } 6659 6660 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 6661 uint64_t Address, const void *Decoder) { 6662 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 6663 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6664 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 6665 fieldFromInstruction(Insn, 12, 3) << 8 | 6666 fieldFromInstruction(Insn, 0, 8); 6667 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 6668 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 6669 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 6670 unsigned S = fieldFromInstruction(Insn, 20, 1); 6671 if (sign1 != sign2) 6672 return MCDisassembler::Fail; 6673 6674 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 6675 DecodeStatus DS = MCDisassembler::Success; 6676 if ((!Check(DS, 6677 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 6678 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 6679 return MCDisassembler::Fail; 6680 if (TypeT3) { 6681 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 6682 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 6683 } else { 6684 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 6685 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 6686 return MCDisassembler::Fail; 6687 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 6688 return MCDisassembler::Fail; 6689 } 6690 6691 return DS; 6692 } 6693