1*0b57cec5SDimitry Andric//=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric// 9*0b57cec5SDimitry Andric// This file defines the itinerary class data for the ARM Cortex A8 processors. 10*0b57cec5SDimitry Andric// 11*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric// 14*0b57cec5SDimitry Andric// Scheduling information derived from "Cortex-A8 Technical Reference Manual". 15*0b57cec5SDimitry Andric// Functional Units. 16*0b57cec5SDimitry Andricdef A8_Pipe0 : FuncUnit; // pipeline 0 17*0b57cec5SDimitry Andricdef A8_Pipe1 : FuncUnit; // pipeline 1 18*0b57cec5SDimitry Andricdef A8_LSPipe : FuncUnit; // Load / store pipeline 19*0b57cec5SDimitry Andricdef A8_NPipe : FuncUnit; // NEON ALU/MUL pipe 20*0b57cec5SDimitry Andricdef A8_NLSPipe : FuncUnit; // NEON LS pipe 21*0b57cec5SDimitry Andric// 22*0b57cec5SDimitry Andric// Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1 23*0b57cec5SDimitry Andric// 24*0b57cec5SDimitry Andricdef CortexA8Itineraries : ProcessorItineraries< 25*0b57cec5SDimitry Andric [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe], 26*0b57cec5SDimitry Andric [], [ 27*0b57cec5SDimitry Andric // Two fully-pipelined integer ALU pipelines 28*0b57cec5SDimitry Andric // 29*0b57cec5SDimitry Andric // No operand cycles 30*0b57cec5SDimitry Andric InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, 31*0b57cec5SDimitry Andric // 32*0b57cec5SDimitry Andric // Binary Instructions that produce a result 33*0b57cec5SDimitry Andric InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 34*0b57cec5SDimitry Andric InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, 35*0b57cec5SDimitry Andric InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 36*0b57cec5SDimitry Andric InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>, 37*0b57cec5SDimitry Andric InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, 38*0b57cec5SDimitry Andric // 39*0b57cec5SDimitry Andric // Bitwise Instructions that produce a result 40*0b57cec5SDimitry Andric InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 41*0b57cec5SDimitry Andric InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, 42*0b57cec5SDimitry Andric InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 43*0b57cec5SDimitry Andric InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, 44*0b57cec5SDimitry Andric // 45*0b57cec5SDimitry Andric // Unary Instructions that produce a result 46*0b57cec5SDimitry Andric InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 47*0b57cec5SDimitry Andric InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 48*0b57cec5SDimitry Andric // 49*0b57cec5SDimitry Andric // Zero and sign extension instructions 50*0b57cec5SDimitry Andric InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, 51*0b57cec5SDimitry Andric InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 52*0b57cec5SDimitry Andric InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>, 53*0b57cec5SDimitry Andric // 54*0b57cec5SDimitry Andric // Compare instructions 55*0b57cec5SDimitry Andric InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>, 56*0b57cec5SDimitry Andric InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 57*0b57cec5SDimitry Andric InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 58*0b57cec5SDimitry Andric InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>, 59*0b57cec5SDimitry Andric // 60*0b57cec5SDimitry Andric // Test instructions 61*0b57cec5SDimitry Andric InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>, 62*0b57cec5SDimitry Andric InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 63*0b57cec5SDimitry Andric InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 64*0b57cec5SDimitry Andric InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>, 65*0b57cec5SDimitry Andric // 66*0b57cec5SDimitry Andric // Move instructions, unconditional 67*0b57cec5SDimitry Andric InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>, 68*0b57cec5SDimitry Andric InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, 69*0b57cec5SDimitry Andric InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, 70*0b57cec5SDimitry Andric InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>, 71*0b57cec5SDimitry Andric InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 72*0b57cec5SDimitry Andric InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>, 73*0b57cec5SDimitry Andric InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 74*0b57cec5SDimitry Andric InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 75*0b57cec5SDimitry Andric InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [3]>, 76*0b57cec5SDimitry Andric InstrItinData<IIC_iMOVix2ld,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 77*0b57cec5SDimitry Andric InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 78*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [5]>, 79*0b57cec5SDimitry Andric // 80*0b57cec5SDimitry Andric // Move instructions, conditional 81*0b57cec5SDimitry Andric InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>, 82*0b57cec5SDimitry Andric InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 83*0b57cec5SDimitry Andric InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 84*0b57cec5SDimitry Andric InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>, 85*0b57cec5SDimitry Andric InstrItinData<IIC_iCMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 86*0b57cec5SDimitry Andric InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [3, 1]>, 87*0b57cec5SDimitry Andric // 88*0b57cec5SDimitry Andric // MVN instructions 89*0b57cec5SDimitry Andric InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>, 90*0b57cec5SDimitry Andric InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, 91*0b57cec5SDimitry Andric InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, 92*0b57cec5SDimitry Andric InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>, 93*0b57cec5SDimitry Andric 94*0b57cec5SDimitry Andric // Integer multiply pipeline 95*0b57cec5SDimitry Andric // Result written in E5, but that is relative to the last cycle of multicycle, 96*0b57cec5SDimitry Andric // so we use 6 for those cases 97*0b57cec5SDimitry Andric // 98*0b57cec5SDimitry Andric InstrItinData<IIC_iMUL16 , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>, 99*0b57cec5SDimitry Andric InstrItinData<IIC_iMAC16 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>, 100*0b57cec5SDimitry Andric InstrItinData<IIC_iMUL32 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>, 101*0b57cec5SDimitry Andric InstrItinData<IIC_iMAC32 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>, 102*0b57cec5SDimitry Andric InstrItinData<IIC_iMUL64 , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>, 103*0b57cec5SDimitry Andric InstrItinData<IIC_iMAC64 , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>, 104*0b57cec5SDimitry Andric 105*0b57cec5SDimitry Andric // Integer load pipeline 106*0b57cec5SDimitry Andric // 107*0b57cec5SDimitry Andric // Immediate offset 108*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 109*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 1]>, 110*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 111*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 1]>, 112*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 113*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 1]>, 114*0b57cec5SDimitry Andric // 115*0b57cec5SDimitry Andric // Register offset 116*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 117*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, 118*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 119*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, 120*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 121*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, 122*0b57cec5SDimitry Andric // 123*0b57cec5SDimitry Andric // Scaled register offset, issues over 2 cycles 124*0b57cec5SDimitry Andric // FIXME: lsl by 2 takes 1 cycle. 125*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 126*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>, 127*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 128*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>, 129*0b57cec5SDimitry Andric // 130*0b57cec5SDimitry Andric // Immediate offset with update 131*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 132*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>, 133*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 134*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>, 135*0b57cec5SDimitry Andric // 136*0b57cec5SDimitry Andric // Register offset with update 137*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 138*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>, 139*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 140*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>, 141*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 142*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>, 143*0b57cec5SDimitry Andric // 144*0b57cec5SDimitry Andric // Scaled register offset with update, issues over 2 cycles 145*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 146*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>, 147*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 148*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>, 149*0b57cec5SDimitry Andric // 150*0b57cec5SDimitry Andric // Load multiple, def is the 5th operand. Pipeline 0 only. 151*0b57cec5SDimitry Andric // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. 152*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_m , [InstrStage<2, [A8_Pipe0], 0>, 153*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 154*0b57cec5SDimitry Andric [1, 1, 1, 1, 3], [], -1>, // dynamic uops 155*0b57cec5SDimitry Andric // 156*0b57cec5SDimitry Andric // Load multiple + update, defs are the 1st and 5th operands. 157*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>, 158*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 159*0b57cec5SDimitry Andric [2, 1, 1, 1, 3], [], -1>, // dynamic uops 160*0b57cec5SDimitry Andric // 161*0b57cec5SDimitry Andric // Load multiple plus branch 162*0b57cec5SDimitry Andric InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>, 163*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>, 164*0b57cec5SDimitry Andric InstrStage<1, [A8_Pipe0, A8_Pipe1]>], 165*0b57cec5SDimitry Andric [1, 2, 1, 1, 3], [], -1>, // dynamic uops 166*0b57cec5SDimitry Andric // 167*0b57cec5SDimitry Andric // Pop, def is the 3rd operand. 168*0b57cec5SDimitry Andric InstrItinData<IIC_iPop , [InstrStage<3, [A8_Pipe0], 0>, 169*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 170*0b57cec5SDimitry Andric [1, 1, 3], [], -1>, // dynamic uops 171*0b57cec5SDimitry Andric // 172*0b57cec5SDimitry Andric // Push, def is the 3th operand. 173*0b57cec5SDimitry Andric InstrItinData<IIC_iPop_Br, [InstrStage<3, [A8_Pipe0], 0>, 174*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>, 175*0b57cec5SDimitry Andric InstrStage<1, [A8_Pipe0, A8_Pipe1]>], 176*0b57cec5SDimitry Andric [1, 1, 3], [], -1>, // dynamic uops 177*0b57cec5SDimitry Andric // 178*0b57cec5SDimitry Andric // iLoadi + iALUr for t2LDRpci_pic. 179*0b57cec5SDimitry Andric InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 180*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>, 181*0b57cec5SDimitry Andric InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>, 182*0b57cec5SDimitry Andric 183*0b57cec5SDimitry Andric 184*0b57cec5SDimitry Andric // Integer store pipeline 185*0b57cec5SDimitry Andric // 186*0b57cec5SDimitry Andric // Immediate offset 187*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 188*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 1]>, 189*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 190*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 1]>, 191*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 192*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 1]>, 193*0b57cec5SDimitry Andric // 194*0b57cec5SDimitry Andric // Register offset 195*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 196*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, 197*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 198*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, 199*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 200*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, 201*0b57cec5SDimitry Andric // 202*0b57cec5SDimitry Andric // Scaled register offset, issues over 2 cycles 203*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 204*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>, 205*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 206*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>, 207*0b57cec5SDimitry Andric // 208*0b57cec5SDimitry Andric // Immediate offset with update 209*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 210*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>, 211*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 212*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>, 213*0b57cec5SDimitry Andric // 214*0b57cec5SDimitry Andric // Register offset with update 215*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 216*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>, 217*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 218*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>, 219*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 220*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>, 221*0b57cec5SDimitry Andric // 222*0b57cec5SDimitry Andric // Scaled register offset with update, issues over 2 cycles 223*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 224*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>, 225*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 226*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>, 227*0b57cec5SDimitry Andric // 228*0b57cec5SDimitry Andric // Store multiple. Pipeline 0 only. 229*0b57cec5SDimitry Andric // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. 230*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>, 231*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 232*0b57cec5SDimitry Andric [], [], -1>, // dynamic uops 233*0b57cec5SDimitry Andric // 234*0b57cec5SDimitry Andric // Store multiple + update 235*0b57cec5SDimitry Andric InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>, 236*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 237*0b57cec5SDimitry Andric [2], [], -1>, // dynamic uops 238*0b57cec5SDimitry Andric // 239*0b57cec5SDimitry Andric // Preload 240*0b57cec5SDimitry Andric InstrItinData<IIC_Preload, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 241*0b57cec5SDimitry Andric 242*0b57cec5SDimitry Andric // Branch 243*0b57cec5SDimitry Andric // 244*0b57cec5SDimitry Andric // no delay slots, so the latency of a branch is unimportant 245*0b57cec5SDimitry Andric InstrItinData<IIC_Br , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, 246*0b57cec5SDimitry Andric 247*0b57cec5SDimitry Andric // VFP 248*0b57cec5SDimitry Andric // Issue through integer pipeline, and execute in NEON unit. We assume 249*0b57cec5SDimitry Andric // RunFast mode so that NFP pipeline is used for single-precision when 250*0b57cec5SDimitry Andric // possible. 251*0b57cec5SDimitry Andric // 252*0b57cec5SDimitry Andric // FP Special Register to Integer Register File Move 253*0b57cec5SDimitry Andric InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 254*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>], [20]>, 255*0b57cec5SDimitry Andric // 256*0b57cec5SDimitry Andric // Single-precision FP Unary 257*0b57cec5SDimitry Andric InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 258*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [7, 1]>, 259*0b57cec5SDimitry Andric // 260*0b57cec5SDimitry Andric // Double-precision FP Unary 261*0b57cec5SDimitry Andric InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 262*0b57cec5SDimitry Andric InstrStage<4, [A8_NPipe], 0>, 263*0b57cec5SDimitry Andric InstrStage<4, [A8_NLSPipe]>], [4, 1]>, 264*0b57cec5SDimitry Andric // 265*0b57cec5SDimitry Andric // Single-precision FP Compare 266*0b57cec5SDimitry Andric InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 267*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [1, 1]>, 268*0b57cec5SDimitry Andric // 269*0b57cec5SDimitry Andric // Double-precision FP Compare 270*0b57cec5SDimitry Andric InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 271*0b57cec5SDimitry Andric InstrStage<4, [A8_NPipe], 0>, 272*0b57cec5SDimitry Andric InstrStage<4, [A8_NLSPipe]>], [4, 1]>, 273*0b57cec5SDimitry Andric // 274*0b57cec5SDimitry Andric // Single to Double FP Convert 275*0b57cec5SDimitry Andric InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 276*0b57cec5SDimitry Andric InstrStage<7, [A8_NPipe], 0>, 277*0b57cec5SDimitry Andric InstrStage<7, [A8_NLSPipe]>], [7, 1]>, 278*0b57cec5SDimitry Andric // 279*0b57cec5SDimitry Andric // Double to Single FP Convert 280*0b57cec5SDimitry Andric InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 281*0b57cec5SDimitry Andric InstrStage<5, [A8_NPipe], 0>, 282*0b57cec5SDimitry Andric InstrStage<5, [A8_NLSPipe]>], [5, 1]>, 283*0b57cec5SDimitry Andric // 284*0b57cec5SDimitry Andric // Single-Precision FP to Integer Convert 285*0b57cec5SDimitry Andric InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 286*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [7, 1]>, 287*0b57cec5SDimitry Andric // 288*0b57cec5SDimitry Andric // Double-Precision FP to Integer Convert 289*0b57cec5SDimitry Andric InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 290*0b57cec5SDimitry Andric InstrStage<8, [A8_NPipe], 0>, 291*0b57cec5SDimitry Andric InstrStage<8, [A8_NLSPipe]>], [8, 1]>, 292*0b57cec5SDimitry Andric // 293*0b57cec5SDimitry Andric // Integer to Single-Precision FP Convert 294*0b57cec5SDimitry Andric InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 295*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [7, 1]>, 296*0b57cec5SDimitry Andric // 297*0b57cec5SDimitry Andric // Integer to Double-Precision FP Convert 298*0b57cec5SDimitry Andric InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 299*0b57cec5SDimitry Andric InstrStage<8, [A8_NPipe], 0>, 300*0b57cec5SDimitry Andric InstrStage<8, [A8_NLSPipe]>], [8, 1]>, 301*0b57cec5SDimitry Andric // 302*0b57cec5SDimitry Andric // Single-precision FP ALU 303*0b57cec5SDimitry Andric InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 304*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [7, 1, 1]>, 305*0b57cec5SDimitry Andric // 306*0b57cec5SDimitry Andric // Double-precision FP ALU 307*0b57cec5SDimitry Andric InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 308*0b57cec5SDimitry Andric InstrStage<9, [A8_NPipe], 0>, 309*0b57cec5SDimitry Andric InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>, 310*0b57cec5SDimitry Andric // 311*0b57cec5SDimitry Andric // Single-precision FP Multiply 312*0b57cec5SDimitry Andric InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 313*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [7, 1, 1]>, 314*0b57cec5SDimitry Andric // 315*0b57cec5SDimitry Andric // Double-precision FP Multiply 316*0b57cec5SDimitry Andric InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 317*0b57cec5SDimitry Andric InstrStage<11, [A8_NPipe], 0>, 318*0b57cec5SDimitry Andric InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>, 319*0b57cec5SDimitry Andric // 320*0b57cec5SDimitry Andric // Single-precision FP MAC 321*0b57cec5SDimitry Andric InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 322*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>, 323*0b57cec5SDimitry Andric // 324*0b57cec5SDimitry Andric // Double-precision FP MAC 325*0b57cec5SDimitry Andric InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 326*0b57cec5SDimitry Andric InstrStage<19, [A8_NPipe], 0>, 327*0b57cec5SDimitry Andric InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>, 328*0b57cec5SDimitry Andric // 329*0b57cec5SDimitry Andric // Single-precision Fused FP MAC 330*0b57cec5SDimitry Andric InstrItinData<IIC_fpFMAC32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 331*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>, 332*0b57cec5SDimitry Andric // 333*0b57cec5SDimitry Andric // Double-precision Fused FP MAC 334*0b57cec5SDimitry Andric InstrItinData<IIC_fpFMAC64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 335*0b57cec5SDimitry Andric InstrStage<19, [A8_NPipe], 0>, 336*0b57cec5SDimitry Andric InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>, 337*0b57cec5SDimitry Andric // 338*0b57cec5SDimitry Andric // Single-precision FP DIV 339*0b57cec5SDimitry Andric InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 340*0b57cec5SDimitry Andric InstrStage<20, [A8_NPipe], 0>, 341*0b57cec5SDimitry Andric InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>, 342*0b57cec5SDimitry Andric // 343*0b57cec5SDimitry Andric // Double-precision FP DIV 344*0b57cec5SDimitry Andric InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 345*0b57cec5SDimitry Andric InstrStage<29, [A8_NPipe], 0>, 346*0b57cec5SDimitry Andric InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>, 347*0b57cec5SDimitry Andric // 348*0b57cec5SDimitry Andric // Single-precision FP SQRT 349*0b57cec5SDimitry Andric InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 350*0b57cec5SDimitry Andric InstrStage<19, [A8_NPipe], 0>, 351*0b57cec5SDimitry Andric InstrStage<19, [A8_NLSPipe]>], [19, 1]>, 352*0b57cec5SDimitry Andric // 353*0b57cec5SDimitry Andric // Double-precision FP SQRT 354*0b57cec5SDimitry Andric InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 355*0b57cec5SDimitry Andric InstrStage<29, [A8_NPipe], 0>, 356*0b57cec5SDimitry Andric InstrStage<29, [A8_NLSPipe]>], [29, 1]>, 357*0b57cec5SDimitry Andric 358*0b57cec5SDimitry Andric // 359*0b57cec5SDimitry Andric // Integer to Single-precision Move 360*0b57cec5SDimitry Andric InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 361*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], 362*0b57cec5SDimitry Andric [2, 1]>, 363*0b57cec5SDimitry Andric // 364*0b57cec5SDimitry Andric // Integer to Double-precision Move 365*0b57cec5SDimitry Andric InstrItinData<IIC_fpMOVID, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 366*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], 367*0b57cec5SDimitry Andric [2, 1, 1]>, 368*0b57cec5SDimitry Andric // 369*0b57cec5SDimitry Andric // Single-precision to Integer Move 370*0b57cec5SDimitry Andric InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 371*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], 372*0b57cec5SDimitry Andric [20, 1]>, 373*0b57cec5SDimitry Andric // 374*0b57cec5SDimitry Andric // Double-precision to Integer Move 375*0b57cec5SDimitry Andric InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 376*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], 377*0b57cec5SDimitry Andric [20, 20, 1]>, 378*0b57cec5SDimitry Andric 379*0b57cec5SDimitry Andric // 380*0b57cec5SDimitry Andric // Single-precision FP Load 381*0b57cec5SDimitry Andric InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 382*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe], 0>, 383*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], 384*0b57cec5SDimitry Andric [2, 1]>, 385*0b57cec5SDimitry Andric // 386*0b57cec5SDimitry Andric // Double-precision FP Load 387*0b57cec5SDimitry Andric InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 388*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe], 0>, 389*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], 390*0b57cec5SDimitry Andric [2, 1]>, 391*0b57cec5SDimitry Andric // 392*0b57cec5SDimitry Andric // FP Load Multiple 393*0b57cec5SDimitry Andric // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. 394*0b57cec5SDimitry Andric InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 395*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe], 0>, 396*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>, 397*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe], 0>, 398*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], 399*0b57cec5SDimitry Andric [1, 1, 1, 2], [], -1>, // dynamic uops 400*0b57cec5SDimitry Andric // 401*0b57cec5SDimitry Andric // FP Load Multiple + update 402*0b57cec5SDimitry Andric InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 403*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe], 0>, 404*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>, 405*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe], 0>, 406*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], 407*0b57cec5SDimitry Andric [2, 1, 1, 1, 2], [], -1>, // dynamic uops 408*0b57cec5SDimitry Andric // 409*0b57cec5SDimitry Andric // Single-precision FP Store 410*0b57cec5SDimitry Andric InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 411*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe], 0>, 412*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], 413*0b57cec5SDimitry Andric [1, 1]>, 414*0b57cec5SDimitry Andric // 415*0b57cec5SDimitry Andric // Double-precision FP Store 416*0b57cec5SDimitry Andric InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 417*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe], 0>, 418*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], 419*0b57cec5SDimitry Andric [1, 1]>, 420*0b57cec5SDimitry Andric // 421*0b57cec5SDimitry Andric // FP Store Multiple 422*0b57cec5SDimitry Andric InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 423*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe], 0>, 424*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>, 425*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe], 0>, 426*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], 427*0b57cec5SDimitry Andric [1, 1, 1, 1], [], -1>, // dynamic uops 428*0b57cec5SDimitry Andric // 429*0b57cec5SDimitry Andric // FP Store Multiple + update 430*0b57cec5SDimitry Andric InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 431*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe], 0>, 432*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>, 433*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe], 0>, 434*0b57cec5SDimitry Andric InstrStage<1, [A8_LSPipe]>], 435*0b57cec5SDimitry Andric [2, 1, 1, 1, 1], [], -1>, // dynamic uops 436*0b57cec5SDimitry Andric // NEON 437*0b57cec5SDimitry Andric // Issue through integer pipeline, and execute in NEON unit. 438*0b57cec5SDimitry Andric // 439*0b57cec5SDimitry Andric // VLD1 440*0b57cec5SDimitry Andric InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 441*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 442*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 443*0b57cec5SDimitry Andric [2, 1]>, 444*0b57cec5SDimitry Andric // VLD1x2 445*0b57cec5SDimitry Andric InstrItinData<IIC_VLD1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 446*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 447*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 448*0b57cec5SDimitry Andric [2, 2, 1]>, 449*0b57cec5SDimitry Andric // 450*0b57cec5SDimitry Andric // VLD1x3 451*0b57cec5SDimitry Andric InstrItinData<IIC_VLD1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 452*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 453*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 454*0b57cec5SDimitry Andric [2, 2, 3, 1]>, 455*0b57cec5SDimitry Andric // 456*0b57cec5SDimitry Andric // VLD1x4 457*0b57cec5SDimitry Andric InstrItinData<IIC_VLD1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 458*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 459*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 460*0b57cec5SDimitry Andric [2, 2, 3, 3, 1]>, 461*0b57cec5SDimitry Andric // 462*0b57cec5SDimitry Andric // VLD1u 463*0b57cec5SDimitry Andric InstrItinData<IIC_VLD1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 464*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 465*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 466*0b57cec5SDimitry Andric [2, 2, 1]>, 467*0b57cec5SDimitry Andric // 468*0b57cec5SDimitry Andric // VLD1x2u 469*0b57cec5SDimitry Andric InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 470*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 471*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 472*0b57cec5SDimitry Andric [2, 2, 2, 1]>, 473*0b57cec5SDimitry Andric // 474*0b57cec5SDimitry Andric // VLD1x3u 475*0b57cec5SDimitry Andric InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 476*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 477*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 478*0b57cec5SDimitry Andric [2, 2, 3, 2, 1]>, 479*0b57cec5SDimitry Andric // 480*0b57cec5SDimitry Andric // VLD1x4u 481*0b57cec5SDimitry Andric InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 482*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 483*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 484*0b57cec5SDimitry Andric [2, 2, 3, 3, 2, 1]>, 485*0b57cec5SDimitry Andric // 486*0b57cec5SDimitry Andric // VLD1ln 487*0b57cec5SDimitry Andric InstrItinData<IIC_VLD1ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 488*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 489*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 490*0b57cec5SDimitry Andric [3, 1, 1, 1]>, 491*0b57cec5SDimitry Andric // 492*0b57cec5SDimitry Andric // VLD1lnu 493*0b57cec5SDimitry Andric InstrItinData<IIC_VLD1lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 494*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 495*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 496*0b57cec5SDimitry Andric [3, 2, 1, 1, 1, 1]>, 497*0b57cec5SDimitry Andric // 498*0b57cec5SDimitry Andric // VLD1dup 499*0b57cec5SDimitry Andric InstrItinData<IIC_VLD1dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 500*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 501*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 502*0b57cec5SDimitry Andric [2, 1]>, 503*0b57cec5SDimitry Andric // 504*0b57cec5SDimitry Andric // VLD1dupu 505*0b57cec5SDimitry Andric InstrItinData<IIC_VLD1dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 506*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 507*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 508*0b57cec5SDimitry Andric [2, 2, 1, 1]>, 509*0b57cec5SDimitry Andric // 510*0b57cec5SDimitry Andric // VLD2 511*0b57cec5SDimitry Andric InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 512*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 513*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 514*0b57cec5SDimitry Andric [2, 2, 1]>, 515*0b57cec5SDimitry Andric // 516*0b57cec5SDimitry Andric // VLD2x2 517*0b57cec5SDimitry Andric InstrItinData<IIC_VLD2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 518*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 519*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 520*0b57cec5SDimitry Andric [2, 2, 3, 3, 1]>, 521*0b57cec5SDimitry Andric // 522*0b57cec5SDimitry Andric // VLD2ln 523*0b57cec5SDimitry Andric InstrItinData<IIC_VLD2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 524*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 525*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 526*0b57cec5SDimitry Andric [3, 3, 1, 1, 1, 1]>, 527*0b57cec5SDimitry Andric // 528*0b57cec5SDimitry Andric // VLD2u 529*0b57cec5SDimitry Andric InstrItinData<IIC_VLD2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 530*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 531*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 532*0b57cec5SDimitry Andric [2, 2, 2, 1, 1, 1]>, 533*0b57cec5SDimitry Andric // 534*0b57cec5SDimitry Andric // VLD2x2u 535*0b57cec5SDimitry Andric InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 536*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 537*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 538*0b57cec5SDimitry Andric [2, 2, 3, 3, 2, 1]>, 539*0b57cec5SDimitry Andric // 540*0b57cec5SDimitry Andric // VLD2lnu 541*0b57cec5SDimitry Andric InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 542*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 543*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 544*0b57cec5SDimitry Andric [3, 3, 2, 1, 1, 1, 1, 1]>, 545*0b57cec5SDimitry Andric // 546*0b57cec5SDimitry Andric // VLD2dup 547*0b57cec5SDimitry Andric InstrItinData<IIC_VLD2dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 548*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 549*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 550*0b57cec5SDimitry Andric [2, 2, 1]>, 551*0b57cec5SDimitry Andric // 552*0b57cec5SDimitry Andric // VLD2dupu 553*0b57cec5SDimitry Andric InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 554*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 555*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 556*0b57cec5SDimitry Andric [2, 2, 2, 1, 1]>, 557*0b57cec5SDimitry Andric // 558*0b57cec5SDimitry Andric // VLD3 559*0b57cec5SDimitry Andric InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 560*0b57cec5SDimitry Andric InstrStage<4, [A8_NLSPipe], 0>, 561*0b57cec5SDimitry Andric InstrStage<4, [A8_LSPipe]>], 562*0b57cec5SDimitry Andric [3, 3, 4, 1]>, 563*0b57cec5SDimitry Andric // 564*0b57cec5SDimitry Andric // VLD3ln 565*0b57cec5SDimitry Andric InstrItinData<IIC_VLD3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 566*0b57cec5SDimitry Andric InstrStage<5, [A8_NLSPipe], 0>, 567*0b57cec5SDimitry Andric InstrStage<5, [A8_LSPipe]>], 568*0b57cec5SDimitry Andric [4, 4, 5, 1, 1, 1, 1, 2]>, 569*0b57cec5SDimitry Andric // 570*0b57cec5SDimitry Andric // VLD3u 571*0b57cec5SDimitry Andric InstrItinData<IIC_VLD3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 572*0b57cec5SDimitry Andric InstrStage<4, [A8_NLSPipe], 0>, 573*0b57cec5SDimitry Andric InstrStage<4, [A8_LSPipe]>], 574*0b57cec5SDimitry Andric [3, 3, 4, 2, 1]>, 575*0b57cec5SDimitry Andric // 576*0b57cec5SDimitry Andric // VLD3lnu 577*0b57cec5SDimitry Andric InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 578*0b57cec5SDimitry Andric InstrStage<5, [A8_NLSPipe], 0>, 579*0b57cec5SDimitry Andric InstrStage<5, [A8_LSPipe]>], 580*0b57cec5SDimitry Andric [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>, 581*0b57cec5SDimitry Andric // 582*0b57cec5SDimitry Andric // VLD3dup 583*0b57cec5SDimitry Andric InstrItinData<IIC_VLD3dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 584*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 585*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 586*0b57cec5SDimitry Andric [2, 2, 3, 1]>, 587*0b57cec5SDimitry Andric // 588*0b57cec5SDimitry Andric // VLD3dupu 589*0b57cec5SDimitry Andric InstrItinData<IIC_VLD3dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 590*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 591*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 592*0b57cec5SDimitry Andric [2, 2, 3, 2, 1, 1]>, 593*0b57cec5SDimitry Andric // 594*0b57cec5SDimitry Andric // VLD4 595*0b57cec5SDimitry Andric InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 596*0b57cec5SDimitry Andric InstrStage<4, [A8_NLSPipe], 0>, 597*0b57cec5SDimitry Andric InstrStage<4, [A8_LSPipe]>], 598*0b57cec5SDimitry Andric [3, 3, 4, 4, 1]>, 599*0b57cec5SDimitry Andric // 600*0b57cec5SDimitry Andric // VLD4ln 601*0b57cec5SDimitry Andric InstrItinData<IIC_VLD4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 602*0b57cec5SDimitry Andric InstrStage<5, [A8_NLSPipe], 0>, 603*0b57cec5SDimitry Andric InstrStage<5, [A8_LSPipe]>], 604*0b57cec5SDimitry Andric [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>, 605*0b57cec5SDimitry Andric // 606*0b57cec5SDimitry Andric // VLD4u 607*0b57cec5SDimitry Andric InstrItinData<IIC_VLD4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 608*0b57cec5SDimitry Andric InstrStage<4, [A8_NLSPipe], 0>, 609*0b57cec5SDimitry Andric InstrStage<4, [A8_LSPipe]>], 610*0b57cec5SDimitry Andric [3, 3, 4, 4, 2, 1]>, 611*0b57cec5SDimitry Andric // 612*0b57cec5SDimitry Andric // VLD4lnu 613*0b57cec5SDimitry Andric InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 614*0b57cec5SDimitry Andric InstrStage<5, [A8_NLSPipe], 0>, 615*0b57cec5SDimitry Andric InstrStage<5, [A8_LSPipe]>], 616*0b57cec5SDimitry Andric [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>, 617*0b57cec5SDimitry Andric // 618*0b57cec5SDimitry Andric // VLD4dup 619*0b57cec5SDimitry Andric InstrItinData<IIC_VLD4dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 620*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 621*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 622*0b57cec5SDimitry Andric [2, 2, 3, 3, 1]>, 623*0b57cec5SDimitry Andric // 624*0b57cec5SDimitry Andric // VLD4dupu 625*0b57cec5SDimitry Andric InstrItinData<IIC_VLD4dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 626*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 627*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 628*0b57cec5SDimitry Andric [2, 2, 3, 3, 2, 1, 1]>, 629*0b57cec5SDimitry Andric // 630*0b57cec5SDimitry Andric // VST1 631*0b57cec5SDimitry Andric InstrItinData<IIC_VST1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 632*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 633*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 634*0b57cec5SDimitry Andric [1, 1, 1]>, 635*0b57cec5SDimitry Andric // 636*0b57cec5SDimitry Andric // VST1x2 637*0b57cec5SDimitry Andric InstrItinData<IIC_VST1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 638*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 639*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 640*0b57cec5SDimitry Andric [1, 1, 1, 1]>, 641*0b57cec5SDimitry Andric // 642*0b57cec5SDimitry Andric // VST1x3 643*0b57cec5SDimitry Andric InstrItinData<IIC_VST1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 644*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 645*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 646*0b57cec5SDimitry Andric [1, 1, 1, 1, 2]>, 647*0b57cec5SDimitry Andric // 648*0b57cec5SDimitry Andric // VST1x4 649*0b57cec5SDimitry Andric InstrItinData<IIC_VST1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 650*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 651*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 652*0b57cec5SDimitry Andric [1, 1, 1, 1, 2, 2]>, 653*0b57cec5SDimitry Andric // 654*0b57cec5SDimitry Andric // VST1u 655*0b57cec5SDimitry Andric InstrItinData<IIC_VST1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 656*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 657*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 658*0b57cec5SDimitry Andric [2, 1, 1, 1, 1]>, 659*0b57cec5SDimitry Andric // 660*0b57cec5SDimitry Andric // VST1x2u 661*0b57cec5SDimitry Andric InstrItinData<IIC_VST1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 662*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 663*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 664*0b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1]>, 665*0b57cec5SDimitry Andric // 666*0b57cec5SDimitry Andric // VST1x3u 667*0b57cec5SDimitry Andric InstrItinData<IIC_VST1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 668*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 669*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 670*0b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2]>, 671*0b57cec5SDimitry Andric // 672*0b57cec5SDimitry Andric // VST1x4u 673*0b57cec5SDimitry Andric InstrItinData<IIC_VST1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 674*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 675*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 676*0b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2, 2]>, 677*0b57cec5SDimitry Andric // 678*0b57cec5SDimitry Andric // VST1ln 679*0b57cec5SDimitry Andric InstrItinData<IIC_VST1ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 680*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 681*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 682*0b57cec5SDimitry Andric [1, 1, 1]>, 683*0b57cec5SDimitry Andric // 684*0b57cec5SDimitry Andric // VST1lnu 685*0b57cec5SDimitry Andric InstrItinData<IIC_VST1lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 686*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 687*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 688*0b57cec5SDimitry Andric [2, 1, 1, 1, 1]>, 689*0b57cec5SDimitry Andric // 690*0b57cec5SDimitry Andric // VST2 691*0b57cec5SDimitry Andric InstrItinData<IIC_VST2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 692*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 693*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 694*0b57cec5SDimitry Andric [1, 1, 1, 1]>, 695*0b57cec5SDimitry Andric // 696*0b57cec5SDimitry Andric // VST2x2 697*0b57cec5SDimitry Andric InstrItinData<IIC_VST2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 698*0b57cec5SDimitry Andric InstrStage<4, [A8_NLSPipe], 0>, 699*0b57cec5SDimitry Andric InstrStage<4, [A8_LSPipe]>], 700*0b57cec5SDimitry Andric [1, 1, 1, 1, 2, 2]>, 701*0b57cec5SDimitry Andric // 702*0b57cec5SDimitry Andric // VST2u 703*0b57cec5SDimitry Andric InstrItinData<IIC_VST2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 704*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 705*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 706*0b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1]>, 707*0b57cec5SDimitry Andric // 708*0b57cec5SDimitry Andric // VST2x2u 709*0b57cec5SDimitry Andric InstrItinData<IIC_VST2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 710*0b57cec5SDimitry Andric InstrStage<4, [A8_NLSPipe], 0>, 711*0b57cec5SDimitry Andric InstrStage<4, [A8_LSPipe]>], 712*0b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2, 2]>, 713*0b57cec5SDimitry Andric // 714*0b57cec5SDimitry Andric // VST2ln 715*0b57cec5SDimitry Andric InstrItinData<IIC_VST2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 716*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 717*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 718*0b57cec5SDimitry Andric [1, 1, 1, 1]>, 719*0b57cec5SDimitry Andric // 720*0b57cec5SDimitry Andric // VST2lnu 721*0b57cec5SDimitry Andric InstrItinData<IIC_VST2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 722*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 723*0b57cec5SDimitry Andric InstrStage<2, [A8_LSPipe]>], 724*0b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1]>, 725*0b57cec5SDimitry Andric // 726*0b57cec5SDimitry Andric // VST3 727*0b57cec5SDimitry Andric InstrItinData<IIC_VST3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 728*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 729*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 730*0b57cec5SDimitry Andric [1, 1, 1, 1, 2]>, 731*0b57cec5SDimitry Andric // 732*0b57cec5SDimitry Andric // VST3u 733*0b57cec5SDimitry Andric InstrItinData<IIC_VST3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 734*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 735*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 736*0b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2]>, 737*0b57cec5SDimitry Andric // 738*0b57cec5SDimitry Andric // VST3ln 739*0b57cec5SDimitry Andric InstrItinData<IIC_VST3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 740*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 741*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 742*0b57cec5SDimitry Andric [1, 1, 1, 1, 2]>, 743*0b57cec5SDimitry Andric // 744*0b57cec5SDimitry Andric // VST3lnu 745*0b57cec5SDimitry Andric InstrItinData<IIC_VST3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 746*0b57cec5SDimitry Andric InstrStage<3, [A8_NLSPipe], 0>, 747*0b57cec5SDimitry Andric InstrStage<3, [A8_LSPipe]>], 748*0b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2]>, 749*0b57cec5SDimitry Andric // 750*0b57cec5SDimitry Andric // VST4 751*0b57cec5SDimitry Andric InstrItinData<IIC_VST4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 752*0b57cec5SDimitry Andric InstrStage<4, [A8_NLSPipe], 0>, 753*0b57cec5SDimitry Andric InstrStage<4, [A8_LSPipe]>], 754*0b57cec5SDimitry Andric [1, 1, 1, 1, 2, 2]>, 755*0b57cec5SDimitry Andric // 756*0b57cec5SDimitry Andric // VST4u 757*0b57cec5SDimitry Andric InstrItinData<IIC_VST4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 758*0b57cec5SDimitry Andric InstrStage<4, [A8_NLSPipe], 0>, 759*0b57cec5SDimitry Andric InstrStage<4, [A8_LSPipe]>], 760*0b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2, 2]>, 761*0b57cec5SDimitry Andric // 762*0b57cec5SDimitry Andric // VST4ln 763*0b57cec5SDimitry Andric InstrItinData<IIC_VST4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 764*0b57cec5SDimitry Andric InstrStage<4, [A8_NLSPipe], 0>, 765*0b57cec5SDimitry Andric InstrStage<4, [A8_LSPipe]>], 766*0b57cec5SDimitry Andric [1, 1, 1, 1, 2, 2]>, 767*0b57cec5SDimitry Andric // 768*0b57cec5SDimitry Andric // VST4lnu 769*0b57cec5SDimitry Andric InstrItinData<IIC_VST4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 770*0b57cec5SDimitry Andric InstrStage<4, [A8_NLSPipe], 0>, 771*0b57cec5SDimitry Andric InstrStage<4, [A8_LSPipe]>], 772*0b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2, 2]>, 773*0b57cec5SDimitry Andric // 774*0b57cec5SDimitry Andric // Double-register FP Unary 775*0b57cec5SDimitry Andric InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 776*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [5, 2]>, 777*0b57cec5SDimitry Andric // 778*0b57cec5SDimitry Andric // Quad-register FP Unary 779*0b57cec5SDimitry Andric // Result written in N5, but that is relative to the last cycle of multicycle, 780*0b57cec5SDimitry Andric // so we use 6 for those cases 781*0b57cec5SDimitry Andric InstrItinData<IIC_VUNAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 782*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [6, 2]>, 783*0b57cec5SDimitry Andric // 784*0b57cec5SDimitry Andric // Double-register FP Binary 785*0b57cec5SDimitry Andric InstrItinData<IIC_VBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 786*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [5, 2, 2]>, 787*0b57cec5SDimitry Andric // 788*0b57cec5SDimitry Andric // VPADD, etc. 789*0b57cec5SDimitry Andric InstrItinData<IIC_VPBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 790*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [5, 2, 2]>, 791*0b57cec5SDimitry Andric // 792*0b57cec5SDimitry Andric // Double-register FP VMUL 793*0b57cec5SDimitry Andric InstrItinData<IIC_VFMULD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 794*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [5, 2, 1]>, 795*0b57cec5SDimitry Andric 796*0b57cec5SDimitry Andric // 797*0b57cec5SDimitry Andric // Quad-register FP Binary 798*0b57cec5SDimitry Andric // Result written in N5, but that is relative to the last cycle of multicycle, 799*0b57cec5SDimitry Andric // so we use 6 for those cases 800*0b57cec5SDimitry Andric InstrItinData<IIC_VBINQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 801*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [6, 2, 2]>, 802*0b57cec5SDimitry Andric // 803*0b57cec5SDimitry Andric // Quad-register FP VMUL 804*0b57cec5SDimitry Andric InstrItinData<IIC_VFMULQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 805*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [6, 2, 1]>, 806*0b57cec5SDimitry Andric // 807*0b57cec5SDimitry Andric // Move 808*0b57cec5SDimitry Andric InstrItinData<IIC_VMOV, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 809*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [1, 1]>, 810*0b57cec5SDimitry Andric // 811*0b57cec5SDimitry Andric // Move Immediate 812*0b57cec5SDimitry Andric InstrItinData<IIC_VMOVImm, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 813*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [3]>, 814*0b57cec5SDimitry Andric // 815*0b57cec5SDimitry Andric // Double-register Permute Move 816*0b57cec5SDimitry Andric InstrItinData<IIC_VMOVD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 817*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>], [2, 1]>, 818*0b57cec5SDimitry Andric // 819*0b57cec5SDimitry Andric // Quad-register Permute Move 820*0b57cec5SDimitry Andric // Result written in N2, but that is relative to the last cycle of multicycle, 821*0b57cec5SDimitry Andric // so we use 3 for those cases 822*0b57cec5SDimitry Andric InstrItinData<IIC_VMOVQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 823*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>], [3, 1]>, 824*0b57cec5SDimitry Andric // 825*0b57cec5SDimitry Andric // Integer to Single-precision Move 826*0b57cec5SDimitry Andric InstrItinData<IIC_VMOVIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 827*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>], [2, 1]>, 828*0b57cec5SDimitry Andric // 829*0b57cec5SDimitry Andric // Integer to Double-precision Move 830*0b57cec5SDimitry Andric InstrItinData<IIC_VMOVID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 831*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>, 832*0b57cec5SDimitry Andric // 833*0b57cec5SDimitry Andric // Single-precision to Integer Move 834*0b57cec5SDimitry Andric InstrItinData<IIC_VMOVSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 835*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>], [20, 1]>, 836*0b57cec5SDimitry Andric // 837*0b57cec5SDimitry Andric // Double-precision to Integer Move 838*0b57cec5SDimitry Andric InstrItinData<IIC_VMOVDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 839*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>, 840*0b57cec5SDimitry Andric // 841*0b57cec5SDimitry Andric // Integer to Lane Move 842*0b57cec5SDimitry Andric InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 843*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>, 844*0b57cec5SDimitry Andric // 845*0b57cec5SDimitry Andric // Vector narrow move 846*0b57cec5SDimitry Andric InstrItinData<IIC_VMOVN , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 847*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [2, 1]>, 848*0b57cec5SDimitry Andric // 849*0b57cec5SDimitry Andric // Double-register Permute 850*0b57cec5SDimitry Andric InstrItinData<IIC_VPERMD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 851*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>, 852*0b57cec5SDimitry Andric // 853*0b57cec5SDimitry Andric // Quad-register Permute 854*0b57cec5SDimitry Andric // Result written in N2, but that is relative to the last cycle of multicycle, 855*0b57cec5SDimitry Andric // so we use 3 for those cases 856*0b57cec5SDimitry Andric InstrItinData<IIC_VPERMQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 857*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>, 858*0b57cec5SDimitry Andric // 859*0b57cec5SDimitry Andric // Quad-register Permute (3 cycle issue) 860*0b57cec5SDimitry Andric // Result written in N2, but that is relative to the last cycle of multicycle, 861*0b57cec5SDimitry Andric // so we use 4 for those cases 862*0b57cec5SDimitry Andric InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 863*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>, 864*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe], 0>, 865*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>, 866*0b57cec5SDimitry Andric // 867*0b57cec5SDimitry Andric // Double-register FP Multiple-Accumulate 868*0b57cec5SDimitry Andric InstrItinData<IIC_VMACD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 869*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>, 870*0b57cec5SDimitry Andric // 871*0b57cec5SDimitry Andric // Quad-register FP Multiple-Accumulate 872*0b57cec5SDimitry Andric // Result written in N9, but that is relative to the last cycle of multicycle, 873*0b57cec5SDimitry Andric // so we use 10 for those cases 874*0b57cec5SDimitry Andric InstrItinData<IIC_VMACQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 875*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>, 876*0b57cec5SDimitry Andric // 877*0b57cec5SDimitry Andric // Double-register Fused FP Multiple-Accumulate 878*0b57cec5SDimitry Andric InstrItinData<IIC_VFMACD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 879*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>, 880*0b57cec5SDimitry Andric // 881*0b57cec5SDimitry Andric // Quad-register Fused FP Multiple-Accumulate 882*0b57cec5SDimitry Andric // Result written in N9, but that is relative to the last cycle of multicycle, 883*0b57cec5SDimitry Andric // so we use 10 for those cases 884*0b57cec5SDimitry Andric InstrItinData<IIC_VFMACQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 885*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>, 886*0b57cec5SDimitry Andric // 887*0b57cec5SDimitry Andric // Double-register Reciprical Step 888*0b57cec5SDimitry Andric InstrItinData<IIC_VRECSD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 889*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [9, 2, 2]>, 890*0b57cec5SDimitry Andric // 891*0b57cec5SDimitry Andric // Quad-register Reciprical Step 892*0b57cec5SDimitry Andric InstrItinData<IIC_VRECSQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 893*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [10, 2, 2]>, 894*0b57cec5SDimitry Andric // 895*0b57cec5SDimitry Andric // Double-register Integer Count 896*0b57cec5SDimitry Andric InstrItinData<IIC_VCNTiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 897*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [3, 2, 2]>, 898*0b57cec5SDimitry Andric // 899*0b57cec5SDimitry Andric // Quad-register Integer Count 900*0b57cec5SDimitry Andric // Result written in N3, but that is relative to the last cycle of multicycle, 901*0b57cec5SDimitry Andric // so we use 4 for those cases 902*0b57cec5SDimitry Andric InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 903*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [4, 2, 2]>, 904*0b57cec5SDimitry Andric // 905*0b57cec5SDimitry Andric // Double-register Integer Unary 906*0b57cec5SDimitry Andric InstrItinData<IIC_VUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 907*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [4, 2]>, 908*0b57cec5SDimitry Andric // 909*0b57cec5SDimitry Andric // Quad-register Integer Unary 910*0b57cec5SDimitry Andric InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 911*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [4, 2]>, 912*0b57cec5SDimitry Andric // 913*0b57cec5SDimitry Andric // Double-register Integer Q-Unary 914*0b57cec5SDimitry Andric InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 915*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [4, 1]>, 916*0b57cec5SDimitry Andric // 917*0b57cec5SDimitry Andric // Quad-register Integer CountQ-Unary 918*0b57cec5SDimitry Andric InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 919*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [4, 1]>, 920*0b57cec5SDimitry Andric // 921*0b57cec5SDimitry Andric // Double-register Integer Binary 922*0b57cec5SDimitry Andric InstrItinData<IIC_VBINiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 923*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [3, 2, 2]>, 924*0b57cec5SDimitry Andric // 925*0b57cec5SDimitry Andric // Quad-register Integer Binary 926*0b57cec5SDimitry Andric InstrItinData<IIC_VBINiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 927*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [3, 2, 2]>, 928*0b57cec5SDimitry Andric // 929*0b57cec5SDimitry Andric // Double-register Integer Binary (4 cycle) 930*0b57cec5SDimitry Andric InstrItinData<IIC_VBINi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 931*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, 932*0b57cec5SDimitry Andric // 933*0b57cec5SDimitry Andric // Quad-register Integer Binary (4 cycle) 934*0b57cec5SDimitry Andric InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 935*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, 936*0b57cec5SDimitry Andric 937*0b57cec5SDimitry Andric // 938*0b57cec5SDimitry Andric // Double-register Integer Subtract 939*0b57cec5SDimitry Andric InstrItinData<IIC_VSUBiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 940*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [3, 2, 1]>, 941*0b57cec5SDimitry Andric // 942*0b57cec5SDimitry Andric // Quad-register Integer Subtract 943*0b57cec5SDimitry Andric InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 944*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [3, 2, 1]>, 945*0b57cec5SDimitry Andric // 946*0b57cec5SDimitry Andric // Double-register Integer Subtract 947*0b57cec5SDimitry Andric InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 948*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, 949*0b57cec5SDimitry Andric // 950*0b57cec5SDimitry Andric // Quad-register Integer Subtract 951*0b57cec5SDimitry Andric InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 952*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, 953*0b57cec5SDimitry Andric // 954*0b57cec5SDimitry Andric // Double-register Integer Shift 955*0b57cec5SDimitry Andric InstrItinData<IIC_VSHLiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 956*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [3, 1, 1]>, 957*0b57cec5SDimitry Andric // 958*0b57cec5SDimitry Andric // Quad-register Integer Shift 959*0b57cec5SDimitry Andric InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 960*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [4, 1, 1]>, 961*0b57cec5SDimitry Andric // 962*0b57cec5SDimitry Andric // Double-register Integer Shift (4 cycle) 963*0b57cec5SDimitry Andric InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 964*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [4, 1, 1]>, 965*0b57cec5SDimitry Andric // 966*0b57cec5SDimitry Andric // Quad-register Integer Shift (4 cycle) 967*0b57cec5SDimitry Andric InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 968*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [5, 1, 1]>, 969*0b57cec5SDimitry Andric // 970*0b57cec5SDimitry Andric // Double-register Integer Pair Add Long 971*0b57cec5SDimitry Andric InstrItinData<IIC_VPALiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 972*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [6, 3, 1]>, 973*0b57cec5SDimitry Andric // 974*0b57cec5SDimitry Andric // Quad-register Integer Pair Add Long 975*0b57cec5SDimitry Andric InstrItinData<IIC_VPALiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 976*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [7, 3, 1]>, 977*0b57cec5SDimitry Andric // 978*0b57cec5SDimitry Andric // Double-register Absolute Difference and Accumulate 979*0b57cec5SDimitry Andric InstrItinData<IIC_VABAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 980*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>, 981*0b57cec5SDimitry Andric // 982*0b57cec5SDimitry Andric // Quad-register Absolute Difference and Accumulate 983*0b57cec5SDimitry Andric InstrItinData<IIC_VABAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 984*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>, 985*0b57cec5SDimitry Andric 986*0b57cec5SDimitry Andric // 987*0b57cec5SDimitry Andric // Double-register Integer Multiply (.8, .16) 988*0b57cec5SDimitry Andric InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 989*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [6, 2, 2]>, 990*0b57cec5SDimitry Andric // 991*0b57cec5SDimitry Andric // Double-register Integer Multiply (.32) 992*0b57cec5SDimitry Andric InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 993*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [7, 2, 1]>, 994*0b57cec5SDimitry Andric // 995*0b57cec5SDimitry Andric // Quad-register Integer Multiply (.8, .16) 996*0b57cec5SDimitry Andric InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 997*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [7, 2, 2]>, 998*0b57cec5SDimitry Andric // 999*0b57cec5SDimitry Andric // Quad-register Integer Multiply (.32) 1000*0b57cec5SDimitry Andric InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1001*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>, 1002*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 1003*0b57cec5SDimitry Andric InstrStage<3, [A8_NPipe]>], [9, 2, 1]>, 1004*0b57cec5SDimitry Andric // 1005*0b57cec5SDimitry Andric // Double-register Integer Multiply-Accumulate (.8, .16) 1006*0b57cec5SDimitry Andric InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1007*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>, 1008*0b57cec5SDimitry Andric // 1009*0b57cec5SDimitry Andric // Double-register Integer Multiply-Accumulate (.32) 1010*0b57cec5SDimitry Andric InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1011*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>, 1012*0b57cec5SDimitry Andric // 1013*0b57cec5SDimitry Andric // Quad-register Integer Multiply-Accumulate (.8, .16) 1014*0b57cec5SDimitry Andric InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1015*0b57cec5SDimitry Andric InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>, 1016*0b57cec5SDimitry Andric // 1017*0b57cec5SDimitry Andric // Quad-register Integer Multiply-Accumulate (.32) 1018*0b57cec5SDimitry Andric InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1019*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe]>, 1020*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe], 0>, 1021*0b57cec5SDimitry Andric InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>, 1022*0b57cec5SDimitry Andric // 1023*0b57cec5SDimitry Andric // Double-register VEXT 1024*0b57cec5SDimitry Andric InstrItinData<IIC_VEXTD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1025*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>, 1026*0b57cec5SDimitry Andric // 1027*0b57cec5SDimitry Andric // Quad-register VEXT 1028*0b57cec5SDimitry Andric InstrItinData<IIC_VEXTQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1029*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>, 1030*0b57cec5SDimitry Andric // 1031*0b57cec5SDimitry Andric // VTB 1032*0b57cec5SDimitry Andric InstrItinData<IIC_VTB1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1033*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>, 1034*0b57cec5SDimitry Andric InstrItinData<IIC_VTB2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1035*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>, 1036*0b57cec5SDimitry Andric InstrItinData<IIC_VTB3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1037*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>, 1038*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe], 0>, 1039*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>, 1040*0b57cec5SDimitry Andric InstrItinData<IIC_VTB4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1041*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>, 1042*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe], 0>, 1043*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>, 1044*0b57cec5SDimitry Andric // 1045*0b57cec5SDimitry Andric // VTBX 1046*0b57cec5SDimitry Andric InstrItinData<IIC_VTBX1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1047*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>, 1048*0b57cec5SDimitry Andric InstrItinData<IIC_VTBX2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1049*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>, 1050*0b57cec5SDimitry Andric InstrItinData<IIC_VTBX3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1051*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>, 1052*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe], 0>, 1053*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>, 1054*0b57cec5SDimitry Andric InstrItinData<IIC_VTBX4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1055*0b57cec5SDimitry Andric InstrStage<1, [A8_NLSPipe]>, 1056*0b57cec5SDimitry Andric InstrStage<1, [A8_NPipe], 0>, 1057*0b57cec5SDimitry Andric InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]> 1058*0b57cec5SDimitry Andric]>; 1059*0b57cec5SDimitry Andric 1060*0b57cec5SDimitry Andric// ===---------------------------------------------------------------------===// 1061*0b57cec5SDimitry Andric// This following definitions describe the simple machine model which 1062*0b57cec5SDimitry Andric// will replace itineraries. 1063*0b57cec5SDimitry Andric 1064*0b57cec5SDimitry Andric// Cortex-A8 machine model for scheduling and other instruction cost heuristics. 1065*0b57cec5SDimitry Andricdef CortexA8Model : SchedMachineModel { 1066*0b57cec5SDimitry Andric let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. 1067*0b57cec5SDimitry Andric let LoadLatency = 2; // Optimistic load latency assuming bypass. 1068*0b57cec5SDimitry Andric // This is overriden by OperandCycles if the 1069*0b57cec5SDimitry Andric // Itineraries are queried instead. 1070*0b57cec5SDimitry Andric let MispredictPenalty = 13; // Based on estimate of pipeline depth. 1071*0b57cec5SDimitry Andric let CompleteModel = 0; 1072*0b57cec5SDimitry Andric 1073*0b57cec5SDimitry Andric let Itineraries = CortexA8Itineraries; 1074*0b57cec5SDimitry Andric} 1075