10b57cec5SDimitry Andric //===-- ARMHazardRecognizer.h - ARM Hazard Recognizers ----------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file defines hazard recognizers for scheduling ARM functions. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_ARM_ARMHAZARDRECOGNIZER_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_ARM_ARMHAZARDRECOGNIZER_H 150b57cec5SDimitry Andric 16e8d8bef9SDimitry Andric #include "ARMBaseInstrInfo.h" 17e8d8bef9SDimitry Andric #include "llvm/ADT/BitmaskEnum.h" 18e8d8bef9SDimitry Andric #include "llvm/ADT/SmallVector.h" 19e8d8bef9SDimitry Andric #include "llvm/CodeGen/ScheduleHazardRecognizer.h" 20e8d8bef9SDimitry Andric #include "llvm/Support/DataTypes.h" 21e8d8bef9SDimitry Andric #include <initializer_list> 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric namespace llvm { 240b57cec5SDimitry Andric 25e8d8bef9SDimitry Andric class DataLayout; 26e8d8bef9SDimitry Andric class MachineFunction; 270b57cec5SDimitry Andric class MachineInstr; 28e8d8bef9SDimitry Andric class ScheduleDAG; 290b57cec5SDimitry Andric 30e8d8bef9SDimitry Andric // Hazards related to FP MLx instructions 31e8d8bef9SDimitry Andric class ARMHazardRecognizerFPMLx : public ScheduleHazardRecognizer { 32480093f4SDimitry Andric MachineInstr *LastMI = nullptr; 33480093f4SDimitry Andric unsigned FpMLxStalls = 0; 340b57cec5SDimitry Andric 350b57cec5SDimitry Andric public: ARMHazardRecognizerFPMLx()36*04eeddc0SDimitry Andric ARMHazardRecognizerFPMLx() { MaxLookAhead = 1; } 370b57cec5SDimitry Andric 380b57cec5SDimitry Andric HazardType getHazardType(SUnit *SU, int Stalls) override; 390b57cec5SDimitry Andric void Reset() override; 400b57cec5SDimitry Andric void EmitInstruction(SUnit *SU) override; 410b57cec5SDimitry Andric void AdvanceCycle() override; 420b57cec5SDimitry Andric void RecedeCycle() override; 430b57cec5SDimitry Andric }; 440b57cec5SDimitry Andric 45e8d8bef9SDimitry Andric // Hazards related to bank conflicts 46e8d8bef9SDimitry Andric class ARMBankConflictHazardRecognizer : public ScheduleHazardRecognizer { 47e8d8bef9SDimitry Andric SmallVector<MachineInstr *, 8> Accesses; 48e8d8bef9SDimitry Andric const MachineFunction &MF; 49e8d8bef9SDimitry Andric const DataLayout &DL; 50e8d8bef9SDimitry Andric int64_t DataMask; 51e8d8bef9SDimitry Andric bool AssumeITCMBankConflict; 52e8d8bef9SDimitry Andric 53e8d8bef9SDimitry Andric public: 54e8d8bef9SDimitry Andric ARMBankConflictHazardRecognizer(const ScheduleDAG *DAG, int64_t DDM, 55e8d8bef9SDimitry Andric bool ABC); 56e8d8bef9SDimitry Andric HazardType getHazardType(SUnit *SU, int Stalls) override; 57e8d8bef9SDimitry Andric void Reset() override; 58e8d8bef9SDimitry Andric void EmitInstruction(SUnit *SU) override; 59e8d8bef9SDimitry Andric void AdvanceCycle() override; 60e8d8bef9SDimitry Andric void RecedeCycle() override; 61e8d8bef9SDimitry Andric 62e8d8bef9SDimitry Andric private: 63e8d8bef9SDimitry Andric inline HazardType CheckOffsets(unsigned O0, unsigned O1); 64e8d8bef9SDimitry Andric }; 65e8d8bef9SDimitry Andric 660b57cec5SDimitry Andric } // end namespace llvm 670b57cec5SDimitry Andric 680b57cec5SDimitry Andric #endif 69