10b57cec5SDimitry Andric //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file contains the code shared between ARM CodeGen and ARM MC 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_ARM_ARMFEATURES_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_ARM_ARMFEATURES_H 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include "MCTargetDesc/ARMMCTargetDesc.h" 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric namespace llvm { 190b57cec5SDimitry Andric 200b57cec5SDimitry Andric template<typename InstrType> // could be MachineInstr or MCInst 210b57cec5SDimitry Andric bool IsCPSRDead(const InstrType *Instr); 220b57cec5SDimitry Andric 230b57cec5SDimitry Andric template<typename InstrType> // could be MachineInstr or MCInst isV8EligibleForIT(const InstrType * Instr)240b57cec5SDimitry Andricinline bool isV8EligibleForIT(const InstrType *Instr) { 250b57cec5SDimitry Andric switch (Instr->getOpcode()) { 260b57cec5SDimitry Andric default: 270b57cec5SDimitry Andric return false; 280b57cec5SDimitry Andric case ARM::tADC: 290b57cec5SDimitry Andric case ARM::tADDi3: 300b57cec5SDimitry Andric case ARM::tADDi8: 310b57cec5SDimitry Andric case ARM::tADDrr: 320b57cec5SDimitry Andric case ARM::tAND: 330b57cec5SDimitry Andric case ARM::tASRri: 340b57cec5SDimitry Andric case ARM::tASRrr: 350b57cec5SDimitry Andric case ARM::tBIC: 360b57cec5SDimitry Andric case ARM::tEOR: 370b57cec5SDimitry Andric case ARM::tLSLri: 380b57cec5SDimitry Andric case ARM::tLSLrr: 390b57cec5SDimitry Andric case ARM::tLSRri: 400b57cec5SDimitry Andric case ARM::tLSRrr: 410b57cec5SDimitry Andric case ARM::tMOVi8: 420b57cec5SDimitry Andric case ARM::tMUL: 430b57cec5SDimitry Andric case ARM::tMVN: 440b57cec5SDimitry Andric case ARM::tORR: 450b57cec5SDimitry Andric case ARM::tROR: 460b57cec5SDimitry Andric case ARM::tRSB: 470b57cec5SDimitry Andric case ARM::tSBC: 480b57cec5SDimitry Andric case ARM::tSUBi3: 490b57cec5SDimitry Andric case ARM::tSUBi8: 500b57cec5SDimitry Andric case ARM::tSUBrr: 510b57cec5SDimitry Andric // Outside of an IT block, these set CPSR. 520b57cec5SDimitry Andric return IsCPSRDead(Instr); 530b57cec5SDimitry Andric case ARM::tADDrSPi: 540b57cec5SDimitry Andric case ARM::tCMNz: 550b57cec5SDimitry Andric case ARM::tCMPi8: 560b57cec5SDimitry Andric case ARM::tCMPr: 570b57cec5SDimitry Andric case ARM::tLDRBi: 580b57cec5SDimitry Andric case ARM::tLDRBr: 590b57cec5SDimitry Andric case ARM::tLDRHi: 600b57cec5SDimitry Andric case ARM::tLDRHr: 610b57cec5SDimitry Andric case ARM::tLDRSB: 620b57cec5SDimitry Andric case ARM::tLDRSH: 630b57cec5SDimitry Andric case ARM::tLDRi: 640b57cec5SDimitry Andric case ARM::tLDRr: 650b57cec5SDimitry Andric case ARM::tLDRspi: 660b57cec5SDimitry Andric case ARM::tSTRBi: 670b57cec5SDimitry Andric case ARM::tSTRBr: 680b57cec5SDimitry Andric case ARM::tSTRHi: 690b57cec5SDimitry Andric case ARM::tSTRHr: 700b57cec5SDimitry Andric case ARM::tSTRi: 710b57cec5SDimitry Andric case ARM::tSTRr: 720b57cec5SDimitry Andric case ARM::tSTRspi: 730b57cec5SDimitry Andric case ARM::tTST: 740b57cec5SDimitry Andric return true; 750b57cec5SDimitry Andric // there are some "conditionally deprecated" opcodes 760b57cec5SDimitry Andric case ARM::tADDspr: 770b57cec5SDimitry Andric case ARM::tBLXr: 78*e8d8bef9SDimitry Andric case ARM::tBLXr_noip: 790b57cec5SDimitry Andric return Instr->getOperand(2).getReg() != ARM::PC; 800b57cec5SDimitry Andric // ADD PC, SP and BLX PC were always unpredictable, 810b57cec5SDimitry Andric // now on top of it they're deprecated 820b57cec5SDimitry Andric case ARM::tADDrSP: 830b57cec5SDimitry Andric case ARM::tBX: 840b57cec5SDimitry Andric return Instr->getOperand(0).getReg() != ARM::PC; 850b57cec5SDimitry Andric case ARM::tADDhirr: 860b57cec5SDimitry Andric return Instr->getOperand(0).getReg() != ARM::PC && 870b57cec5SDimitry Andric Instr->getOperand(2).getReg() != ARM::PC; 880b57cec5SDimitry Andric case ARM::tCMPhir: 890b57cec5SDimitry Andric case ARM::tMOVr: 900b57cec5SDimitry Andric return Instr->getOperand(0).getReg() != ARM::PC && 910b57cec5SDimitry Andric Instr->getOperand(1).getReg() != ARM::PC; 920b57cec5SDimitry Andric } 930b57cec5SDimitry Andric } 940b57cec5SDimitry Andric 950b57cec5SDimitry Andric } 960b57cec5SDimitry Andric 970b57cec5SDimitry Andric #endif 98