1*0b57cec5SDimitry Andric//===-- R700Instructions.td - R700 Instruction defs -------*- tablegen -*-===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric// 9*0b57cec5SDimitry Andric// TableGen definitions for instructions which are: 10*0b57cec5SDimitry Andric// - Available to R700 and newer VLIW4/VLIW5 GPUs 11*0b57cec5SDimitry Andric// - Available only on R700 family GPUs. 12*0b57cec5SDimitry Andric// 13*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andricdef isR700 : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::R700">; 16*0b57cec5SDimitry Andric 17*0b57cec5SDimitry Andriclet Predicates = [isR700] in { 18*0b57cec5SDimitry Andric def SIN_r700 : SIN_Common<0x6E>; 19*0b57cec5SDimitry Andric def COS_r700 : COS_Common<0x6F>; 20*0b57cec5SDimitry Andric} 21