1*0b57cec5SDimitry Andric//===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric// 9*0b57cec5SDimitry Andric// R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction 10*0b57cec5SDimitry Andric// slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS 11*0b57cec5SDimitry Andric// slot has been removed. 12*0b57cec5SDimitry Andric// 13*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andricdef ALU_X : FuncUnit; 17*0b57cec5SDimitry Andricdef ALU_Y : FuncUnit; 18*0b57cec5SDimitry Andricdef ALU_Z : FuncUnit; 19*0b57cec5SDimitry Andricdef ALU_W : FuncUnit; 20*0b57cec5SDimitry Andricdef TRANS : FuncUnit; 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andricdef AnyALU : InstrItinClass; 23*0b57cec5SDimitry Andricdef VecALU : InstrItinClass; 24*0b57cec5SDimitry Andricdef TransALU : InstrItinClass; 25*0b57cec5SDimitry Andricdef XALU : InstrItinClass; 26*0b57cec5SDimitry Andric 27*0b57cec5SDimitry Andricdef R600_VLIW5_Itin : ProcessorItineraries < 28*0b57cec5SDimitry Andric [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS, ALU_NULL], 29*0b57cec5SDimitry Andric [], 30*0b57cec5SDimitry Andric [ 31*0b57cec5SDimitry Andric InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>, 32*0b57cec5SDimitry Andric InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, 33*0b57cec5SDimitry Andric InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>, 34*0b57cec5SDimitry Andric InstrItinData<XALU, [InstrStage<1, [ALU_X]>]>, 35*0b57cec5SDimitry Andric InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]> 36*0b57cec5SDimitry Andric ] 37*0b57cec5SDimitry Andric>; 38*0b57cec5SDimitry Andric 39*0b57cec5SDimitry Andricdef R600_VLIW4_Itin : ProcessorItineraries < 40*0b57cec5SDimitry Andric [ALU_X, ALU_Y, ALU_Z, ALU_W, ALU_NULL], 41*0b57cec5SDimitry Andric [], 42*0b57cec5SDimitry Andric [ 43*0b57cec5SDimitry Andric InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, 44*0b57cec5SDimitry Andric InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, 45*0b57cec5SDimitry Andric InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>, 46*0b57cec5SDimitry Andric InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]> 47*0b57cec5SDimitry Andric ] 48*0b57cec5SDimitry Andric>; 49