xref: /freebsd-src/contrib/llvm-project/llvm/lib/MC/MCInstrDesc.cpp (revision 06c3fb2749bda94cb5201f81ffdb8fa6c3161b2e)
10b57cec5SDimitry Andric //===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric //
90b57cec5SDimitry Andric // This file defines methods on the MCOperandInfo and MCInstrDesc classes, which
100b57cec5SDimitry Andric // are used to describe target instructions and their operands.
110b57cec5SDimitry Andric //
120b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
130b57cec5SDimitry Andric 
140b57cec5SDimitry Andric #include "llvm/MC/MCInstrDesc.h"
150b57cec5SDimitry Andric #include "llvm/MC/MCInst.h"
160b57cec5SDimitry Andric #include "llvm/MC/MCRegisterInfo.h"
170b57cec5SDimitry Andric 
180b57cec5SDimitry Andric using namespace llvm;
190b57cec5SDimitry Andric 
mayAffectControlFlow(const MCInst & MI,const MCRegisterInfo & RI) const200b57cec5SDimitry Andric bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
210b57cec5SDimitry Andric                                        const MCRegisterInfo &RI) const {
220b57cec5SDimitry Andric   if (isBranch() || isCall() || isReturn() || isIndirectBranch())
230b57cec5SDimitry Andric     return true;
240b57cec5SDimitry Andric   unsigned PC = RI.getProgramCounter();
250b57cec5SDimitry Andric   if (PC == 0)
260b57cec5SDimitry Andric     return false;
270b57cec5SDimitry Andric   if (hasDefOfPhysReg(MI, PC, RI))
280b57cec5SDimitry Andric     return true;
290b57cec5SDimitry Andric   return false;
300b57cec5SDimitry Andric }
310b57cec5SDimitry Andric 
hasImplicitDefOfPhysReg(unsigned Reg,const MCRegisterInfo * MRI) const320b57cec5SDimitry Andric bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
330b57cec5SDimitry Andric                                           const MCRegisterInfo *MRI) const {
34bdd1243dSDimitry Andric   for (MCPhysReg ImpDef : implicit_defs())
35bdd1243dSDimitry Andric     if (ImpDef == Reg || (MRI && MRI->isSubRegister(Reg, ImpDef)))
360b57cec5SDimitry Andric       return true;
370b57cec5SDimitry Andric   return false;
380b57cec5SDimitry Andric }
390b57cec5SDimitry Andric 
hasDefOfPhysReg(const MCInst & MI,unsigned Reg,const MCRegisterInfo & RI) const400b57cec5SDimitry Andric bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
410b57cec5SDimitry Andric                                   const MCRegisterInfo &RI) const {
420b57cec5SDimitry Andric   for (int i = 0, e = NumDefs; i != e; ++i)
43*06c3fb27SDimitry Andric     if (MI.getOperand(i).isReg() && MI.getOperand(i).getReg() &&
440b57cec5SDimitry Andric         RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
450b57cec5SDimitry Andric       return true;
460b57cec5SDimitry Andric   if (variadicOpsAreDefs())
470b57cec5SDimitry Andric     for (int i = NumOperands - 1, e = MI.getNumOperands(); i != e; ++i)
480b57cec5SDimitry Andric       if (MI.getOperand(i).isReg() &&
490b57cec5SDimitry Andric           RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
500b57cec5SDimitry Andric         return true;
510b57cec5SDimitry Andric   return hasImplicitDefOfPhysReg(Reg, &RI);
520b57cec5SDimitry Andric }
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