10b57cec5SDimitry Andric //===- MacroFusion.cpp - Macro Fusion -------------------------------------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric //
90b57cec5SDimitry Andric /// \file This file contains the implementation of the DAG scheduling mutation
100b57cec5SDimitry Andric /// to pair instructions back to back.
110b57cec5SDimitry Andric //
120b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
130b57cec5SDimitry Andric
140b57cec5SDimitry Andric #include "llvm/CodeGen/MacroFusion.h"
150b57cec5SDimitry Andric #include "llvm/ADT/Statistic.h"
160b57cec5SDimitry Andric #include "llvm/CodeGen/MachineInstr.h"
170b57cec5SDimitry Andric #include "llvm/CodeGen/ScheduleDAG.h"
1881ad6265SDimitry Andric #include "llvm/CodeGen/ScheduleDAGInstrs.h"
190b57cec5SDimitry Andric #include "llvm/CodeGen/ScheduleDAGMutation.h"
200b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h"
210b57cec5SDimitry Andric #include "llvm/Support/CommandLine.h"
220b57cec5SDimitry Andric #include "llvm/Support/Debug.h"
230b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h"
240b57cec5SDimitry Andric
250b57cec5SDimitry Andric #define DEBUG_TYPE "machine-scheduler"
260b57cec5SDimitry Andric
270b57cec5SDimitry Andric STATISTIC(NumFused, "Number of instr pairs fused");
280b57cec5SDimitry Andric
290b57cec5SDimitry Andric using namespace llvm;
300b57cec5SDimitry Andric
310b57cec5SDimitry Andric static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
320b57cec5SDimitry Andric cl::desc("Enable scheduling for macro fusion."), cl::init(true));
330b57cec5SDimitry Andric
isHazard(const SDep & Dep)340b57cec5SDimitry Andric static bool isHazard(const SDep &Dep) {
350b57cec5SDimitry Andric return Dep.getKind() == SDep::Anti || Dep.getKind() == SDep::Output;
360b57cec5SDimitry Andric }
370b57cec5SDimitry Andric
getPredClusterSU(const SUnit & SU)38480093f4SDimitry Andric static SUnit *getPredClusterSU(const SUnit &SU) {
39480093f4SDimitry Andric for (const SDep &SI : SU.Preds)
40480093f4SDimitry Andric if (SI.isCluster())
41480093f4SDimitry Andric return SI.getSUnit();
42480093f4SDimitry Andric
43480093f4SDimitry Andric return nullptr;
44480093f4SDimitry Andric }
45480093f4SDimitry Andric
hasLessThanNumFused(const SUnit & SU,unsigned FuseLimit)46349cc55cSDimitry Andric bool llvm::hasLessThanNumFused(const SUnit &SU, unsigned FuseLimit) {
47480093f4SDimitry Andric unsigned Num = 1;
48480093f4SDimitry Andric const SUnit *CurrentSU = &SU;
49480093f4SDimitry Andric while ((CurrentSU = getPredClusterSU(*CurrentSU)) && Num < FuseLimit) Num ++;
50480093f4SDimitry Andric return Num < FuseLimit;
51480093f4SDimitry Andric }
52480093f4SDimitry Andric
fuseInstructionPair(ScheduleDAGInstrs & DAG,SUnit & FirstSU,SUnit & SecondSU)53349cc55cSDimitry Andric bool llvm::fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU,
540b57cec5SDimitry Andric SUnit &SecondSU) {
550b57cec5SDimitry Andric // Check that neither instr is already paired with another along the edge
560b57cec5SDimitry Andric // between them.
570b57cec5SDimitry Andric for (SDep &SI : FirstSU.Succs)
580b57cec5SDimitry Andric if (SI.isCluster())
590b57cec5SDimitry Andric return false;
600b57cec5SDimitry Andric
610b57cec5SDimitry Andric for (SDep &SI : SecondSU.Preds)
620b57cec5SDimitry Andric if (SI.isCluster())
630b57cec5SDimitry Andric return false;
640b57cec5SDimitry Andric // Though the reachability checks above could be made more generic,
650b57cec5SDimitry Andric // perhaps as part of ScheduleDAGInstrs::addEdge(), since such edges are valid,
660b57cec5SDimitry Andric // the extra computation cost makes it less interesting in general cases.
670b57cec5SDimitry Andric
680b57cec5SDimitry Andric // Create a single weak edge between the adjacent instrs. The only effect is
690b57cec5SDimitry Andric // to cause bottom-up scheduling to heavily prioritize the clustered instrs.
700b57cec5SDimitry Andric if (!DAG.addEdge(&SecondSU, SDep(&FirstSU, SDep::Cluster)))
710b57cec5SDimitry Andric return false;
720b57cec5SDimitry Andric
73480093f4SDimitry Andric // TODO - If we want to chain more than two instructions, we need to create
74480093f4SDimitry Andric // artifical edges to make dependencies from the FirstSU also dependent
75480093f4SDimitry Andric // on other chained instructions, and other chained instructions also
76480093f4SDimitry Andric // dependent on the dependencies of the SecondSU, to prevent them from being
77480093f4SDimitry Andric // scheduled into these chained instructions.
78480093f4SDimitry Andric assert(hasLessThanNumFused(FirstSU, 2) &&
79480093f4SDimitry Andric "Currently we only support chaining together two instructions");
80480093f4SDimitry Andric
810b57cec5SDimitry Andric // Adjust the latency between both instrs.
820b57cec5SDimitry Andric for (SDep &SI : FirstSU.Succs)
830b57cec5SDimitry Andric if (SI.getSUnit() == &SecondSU)
840b57cec5SDimitry Andric SI.setLatency(0);
850b57cec5SDimitry Andric
860b57cec5SDimitry Andric for (SDep &SI : SecondSU.Preds)
870b57cec5SDimitry Andric if (SI.getSUnit() == &FirstSU)
880b57cec5SDimitry Andric SI.setLatency(0);
890b57cec5SDimitry Andric
900b57cec5SDimitry Andric LLVM_DEBUG(
910b57cec5SDimitry Andric dbgs() << "Macro fuse: "; DAG.dumpNodeName(FirstSU); dbgs() << " - ";
920b57cec5SDimitry Andric DAG.dumpNodeName(SecondSU); dbgs() << " / ";
930b57cec5SDimitry Andric dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - "
940b57cec5SDimitry Andric << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';);
950b57cec5SDimitry Andric
960b57cec5SDimitry Andric // Make data dependencies from the FirstSU also dependent on the SecondSU to
970b57cec5SDimitry Andric // prevent them from being scheduled between the FirstSU and the SecondSU.
980b57cec5SDimitry Andric if (&SecondSU != &DAG.ExitSU)
990b57cec5SDimitry Andric for (const SDep &SI : FirstSU.Succs) {
1000b57cec5SDimitry Andric SUnit *SU = SI.getSUnit();
1010b57cec5SDimitry Andric if (SI.isWeak() || isHazard(SI) ||
1020b57cec5SDimitry Andric SU == &DAG.ExitSU || SU == &SecondSU || SU->isPred(&SecondSU))
1030b57cec5SDimitry Andric continue;
1040b57cec5SDimitry Andric LLVM_DEBUG(dbgs() << " Bind "; DAG.dumpNodeName(SecondSU);
1050b57cec5SDimitry Andric dbgs() << " - "; DAG.dumpNodeName(*SU); dbgs() << '\n';);
1060b57cec5SDimitry Andric DAG.addEdge(SU, SDep(&SecondSU, SDep::Artificial));
1070b57cec5SDimitry Andric }
1080b57cec5SDimitry Andric
1090b57cec5SDimitry Andric // Make the FirstSU also dependent on the dependencies of the SecondSU to
1100b57cec5SDimitry Andric // prevent them from being scheduled between the FirstSU and the SecondSU.
1110b57cec5SDimitry Andric if (&FirstSU != &DAG.EntrySU) {
1120b57cec5SDimitry Andric for (const SDep &SI : SecondSU.Preds) {
1130b57cec5SDimitry Andric SUnit *SU = SI.getSUnit();
1140b57cec5SDimitry Andric if (SI.isWeak() || isHazard(SI) || &FirstSU == SU || FirstSU.isSucc(SU))
1150b57cec5SDimitry Andric continue;
1160b57cec5SDimitry Andric LLVM_DEBUG(dbgs() << " Bind "; DAG.dumpNodeName(*SU); dbgs() << " - ";
1170b57cec5SDimitry Andric DAG.dumpNodeName(FirstSU); dbgs() << '\n';);
1180b57cec5SDimitry Andric DAG.addEdge(&FirstSU, SDep(SU, SDep::Artificial));
1190b57cec5SDimitry Andric }
1200b57cec5SDimitry Andric // ExitSU comes last by design, which acts like an implicit dependency
1210b57cec5SDimitry Andric // between ExitSU and any bottom root in the graph. We should transfer
1220b57cec5SDimitry Andric // this to FirstSU as well.
1230b57cec5SDimitry Andric if (&SecondSU == &DAG.ExitSU) {
1240b57cec5SDimitry Andric for (SUnit &SU : DAG.SUnits) {
1250b57cec5SDimitry Andric if (SU.Succs.empty())
1260b57cec5SDimitry Andric DAG.addEdge(&FirstSU, SDep(&SU, SDep::Artificial));
1270b57cec5SDimitry Andric }
1280b57cec5SDimitry Andric }
1290b57cec5SDimitry Andric }
1300b57cec5SDimitry Andric
1310b57cec5SDimitry Andric ++NumFused;
1320b57cec5SDimitry Andric return true;
1330b57cec5SDimitry Andric }
1340b57cec5SDimitry Andric
1350b57cec5SDimitry Andric namespace {
1360b57cec5SDimitry Andric
1370b57cec5SDimitry Andric /// Post-process the DAG to create cluster edges between instrs that may
1380b57cec5SDimitry Andric /// be fused by the processor into a single operation.
1390b57cec5SDimitry Andric class MacroFusion : public ScheduleDAGMutation {
1405f757f3fSDimitry Andric std::vector<MacroFusionPredTy> Predicates;
1410b57cec5SDimitry Andric bool FuseBlock;
1420b57cec5SDimitry Andric bool scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU);
1430b57cec5SDimitry Andric
1440b57cec5SDimitry Andric public:
MacroFusion(ArrayRef<MacroFusionPredTy> Predicates,bool FuseBlock)1455f757f3fSDimitry Andric MacroFusion(ArrayRef<MacroFusionPredTy> Predicates, bool FuseBlock)
1465f757f3fSDimitry Andric : Predicates(Predicates.begin(), Predicates.end()), FuseBlock(FuseBlock) {
1475f757f3fSDimitry Andric }
1480b57cec5SDimitry Andric
1490b57cec5SDimitry Andric void apply(ScheduleDAGInstrs *DAGInstrs) override;
1505f757f3fSDimitry Andric
1515f757f3fSDimitry Andric bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
1525f757f3fSDimitry Andric const TargetSubtargetInfo &STI,
1535f757f3fSDimitry Andric const MachineInstr *FirstMI,
1545f757f3fSDimitry Andric const MachineInstr &SecondMI);
1550b57cec5SDimitry Andric };
1560b57cec5SDimitry Andric
1570b57cec5SDimitry Andric } // end anonymous namespace
1580b57cec5SDimitry Andric
shouldScheduleAdjacent(const TargetInstrInfo & TII,const TargetSubtargetInfo & STI,const MachineInstr * FirstMI,const MachineInstr & SecondMI)1595f757f3fSDimitry Andric bool MacroFusion::shouldScheduleAdjacent(const TargetInstrInfo &TII,
1605f757f3fSDimitry Andric const TargetSubtargetInfo &STI,
1615f757f3fSDimitry Andric const MachineInstr *FirstMI,
1625f757f3fSDimitry Andric const MachineInstr &SecondMI) {
1635f757f3fSDimitry Andric return llvm::any_of(Predicates, [&](MacroFusionPredTy Predicate) {
1645f757f3fSDimitry Andric return Predicate(TII, STI, FirstMI, SecondMI);
1655f757f3fSDimitry Andric });
1665f757f3fSDimitry Andric }
1675f757f3fSDimitry Andric
apply(ScheduleDAGInstrs * DAG)1680b57cec5SDimitry Andric void MacroFusion::apply(ScheduleDAGInstrs *DAG) {
1690b57cec5SDimitry Andric if (FuseBlock)
1700b57cec5SDimitry Andric // For each of the SUnits in the scheduling block, try to fuse the instr in
1710b57cec5SDimitry Andric // it with one in its predecessors.
1720b57cec5SDimitry Andric for (SUnit &ISU : DAG->SUnits)
1730b57cec5SDimitry Andric scheduleAdjacentImpl(*DAG, ISU);
1740b57cec5SDimitry Andric
1750b57cec5SDimitry Andric if (DAG->ExitSU.getInstr())
1760b57cec5SDimitry Andric // Try to fuse the instr in the ExitSU with one in its predecessors.
1770b57cec5SDimitry Andric scheduleAdjacentImpl(*DAG, DAG->ExitSU);
1780b57cec5SDimitry Andric }
1790b57cec5SDimitry Andric
1800b57cec5SDimitry Andric /// Implement the fusion of instr pairs in the scheduling DAG,
1810b57cec5SDimitry Andric /// anchored at the instr in AnchorSU..
scheduleAdjacentImpl(ScheduleDAGInstrs & DAG,SUnit & AnchorSU)1820b57cec5SDimitry Andric bool MacroFusion::scheduleAdjacentImpl(ScheduleDAGInstrs &DAG, SUnit &AnchorSU) {
1830b57cec5SDimitry Andric const MachineInstr &AnchorMI = *AnchorSU.getInstr();
1840b57cec5SDimitry Andric const TargetInstrInfo &TII = *DAG.TII;
1850b57cec5SDimitry Andric const TargetSubtargetInfo &ST = DAG.MF.getSubtarget();
1860b57cec5SDimitry Andric
1870b57cec5SDimitry Andric // Check if the anchor instr may be fused.
1880b57cec5SDimitry Andric if (!shouldScheduleAdjacent(TII, ST, nullptr, AnchorMI))
1890b57cec5SDimitry Andric return false;
1900b57cec5SDimitry Andric
1910b57cec5SDimitry Andric // Explorer for fusion candidates among the dependencies of the anchor instr.
1920b57cec5SDimitry Andric for (SDep &Dep : AnchorSU.Preds) {
1930b57cec5SDimitry Andric // Ignore dependencies other than data or strong ordering.
1940b57cec5SDimitry Andric if (Dep.isWeak() || isHazard(Dep))
1950b57cec5SDimitry Andric continue;
1960b57cec5SDimitry Andric
1970b57cec5SDimitry Andric SUnit &DepSU = *Dep.getSUnit();
1980b57cec5SDimitry Andric if (DepSU.isBoundaryNode())
1990b57cec5SDimitry Andric continue;
2000b57cec5SDimitry Andric
201480093f4SDimitry Andric // Only chain two instructions together at most.
2020b57cec5SDimitry Andric const MachineInstr *DepMI = DepSU.getInstr();
203480093f4SDimitry Andric if (!hasLessThanNumFused(DepSU, 2) ||
204480093f4SDimitry Andric !shouldScheduleAdjacent(TII, ST, DepMI, AnchorMI))
2050b57cec5SDimitry Andric continue;
2060b57cec5SDimitry Andric
2070b57cec5SDimitry Andric if (fuseInstructionPair(DAG, DepSU, AnchorSU))
2080b57cec5SDimitry Andric return true;
2090b57cec5SDimitry Andric }
2100b57cec5SDimitry Andric
2110b57cec5SDimitry Andric return false;
2120b57cec5SDimitry Andric }
2130b57cec5SDimitry Andric
2140b57cec5SDimitry Andric std::unique_ptr<ScheduleDAGMutation>
createMacroFusionDAGMutation(ArrayRef<MacroFusionPredTy> Predicates,bool BranchOnly)215*cb14a3feSDimitry Andric llvm::createMacroFusionDAGMutation(ArrayRef<MacroFusionPredTy> Predicates,
216*cb14a3feSDimitry Andric bool BranchOnly) {
2170b57cec5SDimitry Andric if (EnableMacroFusion)
218*cb14a3feSDimitry Andric return std::make_unique<MacroFusion>(Predicates, !BranchOnly);
2190b57cec5SDimitry Andric return nullptr;
2200b57cec5SDimitry Andric }
221