10b57cec5SDimitry Andric //===- LiveIntervalUnion.cpp - Live interval union data structure ---------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric //
90b57cec5SDimitry Andric // LiveIntervalUnion represents a coalesced set of live intervals. This may be
100b57cec5SDimitry Andric // used during coalescing to represent a congruence class, or during register
110b57cec5SDimitry Andric // allocation to model liveness of a physical register.
120b57cec5SDimitry Andric //
130b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
140b57cec5SDimitry Andric
150b57cec5SDimitry Andric #include "llvm/CodeGen/LiveIntervalUnion.h"
160b57cec5SDimitry Andric #include "llvm/ADT/STLExtras.h"
170b57cec5SDimitry Andric #include "llvm/CodeGen/LiveInterval.h"
180b57cec5SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h"
190b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h"
200b57cec5SDimitry Andric #include <cassert>
210b57cec5SDimitry Andric #include <cstdlib>
220b57cec5SDimitry Andric
230b57cec5SDimitry Andric using namespace llvm;
240b57cec5SDimitry Andric
250b57cec5SDimitry Andric #define DEBUG_TYPE "regalloc"
260b57cec5SDimitry Andric
270b57cec5SDimitry Andric // Merge a LiveInterval's segments. Guarantee no overlaps.
unify(const LiveInterval & VirtReg,const LiveRange & Range)28*81ad6265SDimitry Andric void LiveIntervalUnion::unify(const LiveInterval &VirtReg,
29*81ad6265SDimitry Andric const LiveRange &Range) {
300b57cec5SDimitry Andric if (Range.empty())
310b57cec5SDimitry Andric return;
320b57cec5SDimitry Andric ++Tag;
330b57cec5SDimitry Andric
340b57cec5SDimitry Andric // Insert each of the virtual register's live segments into the map.
350b57cec5SDimitry Andric LiveRange::const_iterator RegPos = Range.begin();
360b57cec5SDimitry Andric LiveRange::const_iterator RegEnd = Range.end();
370b57cec5SDimitry Andric SegmentIter SegPos = Segments.find(RegPos->start);
380b57cec5SDimitry Andric
390b57cec5SDimitry Andric while (SegPos.valid()) {
400b57cec5SDimitry Andric SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
410b57cec5SDimitry Andric if (++RegPos == RegEnd)
420b57cec5SDimitry Andric return;
430b57cec5SDimitry Andric SegPos.advanceTo(RegPos->start);
440b57cec5SDimitry Andric }
450b57cec5SDimitry Andric
460b57cec5SDimitry Andric // We have reached the end of Segments, so it is no longer necessary to search
470b57cec5SDimitry Andric // for the insertion position.
480b57cec5SDimitry Andric // It is faster to insert the end first.
490b57cec5SDimitry Andric --RegEnd;
500b57cec5SDimitry Andric SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
510b57cec5SDimitry Andric for (; RegPos != RegEnd; ++RegPos, ++SegPos)
520b57cec5SDimitry Andric SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
530b57cec5SDimitry Andric }
540b57cec5SDimitry Andric
550b57cec5SDimitry Andric // Remove a live virtual register's segments from this union.
extract(const LiveInterval & VirtReg,const LiveRange & Range)56*81ad6265SDimitry Andric void LiveIntervalUnion::extract(const LiveInterval &VirtReg,
57*81ad6265SDimitry Andric const LiveRange &Range) {
580b57cec5SDimitry Andric if (Range.empty())
590b57cec5SDimitry Andric return;
600b57cec5SDimitry Andric ++Tag;
610b57cec5SDimitry Andric
620b57cec5SDimitry Andric // Remove each of the virtual register's live segments from the map.
630b57cec5SDimitry Andric LiveRange::const_iterator RegPos = Range.begin();
640b57cec5SDimitry Andric LiveRange::const_iterator RegEnd = Range.end();
650b57cec5SDimitry Andric SegmentIter SegPos = Segments.find(RegPos->start);
660b57cec5SDimitry Andric
670b57cec5SDimitry Andric while (true) {
680b57cec5SDimitry Andric assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
690b57cec5SDimitry Andric SegPos.erase();
700b57cec5SDimitry Andric if (!SegPos.valid())
710b57cec5SDimitry Andric return;
720b57cec5SDimitry Andric
730b57cec5SDimitry Andric // Skip all segments that may have been coalesced.
740b57cec5SDimitry Andric RegPos = Range.advanceTo(RegPos, SegPos.start());
750b57cec5SDimitry Andric if (RegPos == RegEnd)
760b57cec5SDimitry Andric return;
770b57cec5SDimitry Andric
780b57cec5SDimitry Andric SegPos.advanceTo(RegPos->start);
790b57cec5SDimitry Andric }
800b57cec5SDimitry Andric }
810b57cec5SDimitry Andric
820b57cec5SDimitry Andric void
print(raw_ostream & OS,const TargetRegisterInfo * TRI) const830b57cec5SDimitry Andric LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
840b57cec5SDimitry Andric if (empty()) {
850b57cec5SDimitry Andric OS << " empty\n";
860b57cec5SDimitry Andric return;
870b57cec5SDimitry Andric }
880b57cec5SDimitry Andric for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
89e8d8bef9SDimitry Andric OS << " [" << SI.start() << ' ' << SI.stop()
90e8d8bef9SDimitry Andric << "):" << printReg(SI.value()->reg(), TRI);
910b57cec5SDimitry Andric }
920b57cec5SDimitry Andric OS << '\n';
930b57cec5SDimitry Andric }
940b57cec5SDimitry Andric
950b57cec5SDimitry Andric #ifndef NDEBUG
960b57cec5SDimitry Andric // Verify the live intervals in this union and add them to the visited set.
verify(LiveVirtRegBitSet & VisitedVRegs)970b57cec5SDimitry Andric void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
980b57cec5SDimitry Andric for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
99e8d8bef9SDimitry Andric VisitedVRegs.set(SI.value()->reg());
1000b57cec5SDimitry Andric }
1010b57cec5SDimitry Andric #endif //!NDEBUG
1020b57cec5SDimitry Andric
getOneVReg() const103*81ad6265SDimitry Andric const LiveInterval *LiveIntervalUnion::getOneVReg() const {
104e8d8bef9SDimitry Andric if (empty())
105e8d8bef9SDimitry Andric return nullptr;
106e8d8bef9SDimitry Andric for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
107e8d8bef9SDimitry Andric // return the first valid live interval
108e8d8bef9SDimitry Andric return SI.value();
109e8d8bef9SDimitry Andric }
110e8d8bef9SDimitry Andric return nullptr;
111e8d8bef9SDimitry Andric }
112e8d8bef9SDimitry Andric
1130b57cec5SDimitry Andric // Scan the vector of interfering virtual registers in this union. Assume it's
1140b57cec5SDimitry Andric // quite small.
isSeenInterference(const LiveInterval * VirtReg) const115*81ad6265SDimitry Andric bool LiveIntervalUnion::Query::isSeenInterference(
116*81ad6265SDimitry Andric const LiveInterval *VirtReg) const {
117349cc55cSDimitry Andric return is_contained(InterferingVRegs, VirtReg);
1180b57cec5SDimitry Andric }
1190b57cec5SDimitry Andric
1200b57cec5SDimitry Andric // Collect virtual registers in this union that interfere with this
1210b57cec5SDimitry Andric // query's live virtual register.
1220b57cec5SDimitry Andric //
1230b57cec5SDimitry Andric // The query state is one of:
1240b57cec5SDimitry Andric //
1250b57cec5SDimitry Andric // 1. CheckedFirstInterference == false: Iterators are uninitialized.
1260b57cec5SDimitry Andric // 2. SeenAllInterferences == true: InterferingVRegs complete, iterators unused.
1270b57cec5SDimitry Andric // 3. Iterators left at the last seen intersection.
1280b57cec5SDimitry Andric //
129349cc55cSDimitry Andric unsigned
collectInterferingVRegs(unsigned MaxInterferingRegs)130349cc55cSDimitry Andric LiveIntervalUnion::Query::collectInterferingVRegs(unsigned MaxInterferingRegs) {
1310b57cec5SDimitry Andric // Fast path return if we already have the desired information.
132349cc55cSDimitry Andric if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs)
133349cc55cSDimitry Andric return InterferingVRegs.size();
1340b57cec5SDimitry Andric
1350b57cec5SDimitry Andric // Set up iterators on the first call.
1360b57cec5SDimitry Andric if (!CheckedFirstInterference) {
1370b57cec5SDimitry Andric CheckedFirstInterference = true;
1380b57cec5SDimitry Andric
1390b57cec5SDimitry Andric // Quickly skip interference check for empty sets.
1400b57cec5SDimitry Andric if (LR->empty() || LiveUnion->empty()) {
1410b57cec5SDimitry Andric SeenAllInterferences = true;
1420b57cec5SDimitry Andric return 0;
1430b57cec5SDimitry Andric }
1440b57cec5SDimitry Andric
1450b57cec5SDimitry Andric // In most cases, the union will start before LR.
1460b57cec5SDimitry Andric LRI = LR->begin();
1470b57cec5SDimitry Andric LiveUnionI.setMap(LiveUnion->getMap());
1480b57cec5SDimitry Andric LiveUnionI.find(LRI->start);
1490b57cec5SDimitry Andric }
1500b57cec5SDimitry Andric
1510b57cec5SDimitry Andric LiveRange::const_iterator LREnd = LR->end();
152*81ad6265SDimitry Andric const LiveInterval *RecentReg = nullptr;
1530b57cec5SDimitry Andric while (LiveUnionI.valid()) {
1540b57cec5SDimitry Andric assert(LRI != LREnd && "Reached end of LR");
1550b57cec5SDimitry Andric
1560b57cec5SDimitry Andric // Check for overlapping interference.
1570b57cec5SDimitry Andric while (LRI->start < LiveUnionI.stop() && LRI->end > LiveUnionI.start()) {
1580b57cec5SDimitry Andric // This is an overlap, record the interfering register.
159*81ad6265SDimitry Andric const LiveInterval *VReg = LiveUnionI.value();
1600b57cec5SDimitry Andric if (VReg != RecentReg && !isSeenInterference(VReg)) {
1610b57cec5SDimitry Andric RecentReg = VReg;
162349cc55cSDimitry Andric InterferingVRegs.push_back(VReg);
163349cc55cSDimitry Andric if (InterferingVRegs.size() >= MaxInterferingRegs)
164349cc55cSDimitry Andric return InterferingVRegs.size();
1650b57cec5SDimitry Andric }
1660b57cec5SDimitry Andric // This LiveUnion segment is no longer interesting.
1670b57cec5SDimitry Andric if (!(++LiveUnionI).valid()) {
1680b57cec5SDimitry Andric SeenAllInterferences = true;
169349cc55cSDimitry Andric return InterferingVRegs.size();
1700b57cec5SDimitry Andric }
1710b57cec5SDimitry Andric }
1720b57cec5SDimitry Andric
1730b57cec5SDimitry Andric // The iterators are now not overlapping, LiveUnionI has been advanced
1740b57cec5SDimitry Andric // beyond LRI.
1750b57cec5SDimitry Andric assert(LRI->end <= LiveUnionI.start() && "Expected non-overlap");
1760b57cec5SDimitry Andric
1770b57cec5SDimitry Andric // Advance the iterator that ends first.
1780b57cec5SDimitry Andric LRI = LR->advanceTo(LRI, LiveUnionI.start());
1790b57cec5SDimitry Andric if (LRI == LREnd)
1800b57cec5SDimitry Andric break;
1810b57cec5SDimitry Andric
1820b57cec5SDimitry Andric // Detect overlap, handle above.
1830b57cec5SDimitry Andric if (LRI->start < LiveUnionI.stop())
1840b57cec5SDimitry Andric continue;
1850b57cec5SDimitry Andric
1860b57cec5SDimitry Andric // Still not overlapping. Catch up LiveUnionI.
1870b57cec5SDimitry Andric LiveUnionI.advanceTo(LRI->start);
1880b57cec5SDimitry Andric }
1890b57cec5SDimitry Andric SeenAllInterferences = true;
190349cc55cSDimitry Andric return InterferingVRegs.size();
1910b57cec5SDimitry Andric }
1920b57cec5SDimitry Andric
init(LiveIntervalUnion::Allocator & Alloc,unsigned NSize)1930b57cec5SDimitry Andric void LiveIntervalUnion::Array::init(LiveIntervalUnion::Allocator &Alloc,
1940b57cec5SDimitry Andric unsigned NSize) {
1950b57cec5SDimitry Andric // Reuse existing allocation.
1960b57cec5SDimitry Andric if (NSize == Size)
1970b57cec5SDimitry Andric return;
1980b57cec5SDimitry Andric clear();
1990b57cec5SDimitry Andric Size = NSize;
2000b57cec5SDimitry Andric LIUs = static_cast<LiveIntervalUnion*>(
2010b57cec5SDimitry Andric safe_malloc(sizeof(LiveIntervalUnion)*NSize));
2020b57cec5SDimitry Andric for (unsigned i = 0; i != Size; ++i)
2030b57cec5SDimitry Andric new(LIUs + i) LiveIntervalUnion(Alloc);
2040b57cec5SDimitry Andric }
2050b57cec5SDimitry Andric
clear()2060b57cec5SDimitry Andric void LiveIntervalUnion::Array::clear() {
2070b57cec5SDimitry Andric if (!LIUs)
2080b57cec5SDimitry Andric return;
2090b57cec5SDimitry Andric for (unsigned i = 0; i != Size; ++i)
2100b57cec5SDimitry Andric LIUs[i].~LiveIntervalUnion();
2110b57cec5SDimitry Andric free(LIUs);
2120b57cec5SDimitry Andric Size = 0;
2130b57cec5SDimitry Andric LIUs = nullptr;
2140b57cec5SDimitry Andric }
215