1 //===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by 2 // combiner ------*- C++ -*-===// 3 // 4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 5 // See https://llvm.org/LICENSE.txt for license information. 6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines instruction pattern supported by combiner 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H 15 #define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H 16 17 namespace llvm { 18 19 /// These are instruction patterns matched by the machine combiner pass. 20 enum class MachineCombinerPattern { 21 // These are commutative variants for reassociating a computation chain. See 22 // the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp. 23 REASSOC_AX_BY, 24 REASSOC_AX_YB, 25 REASSOC_XA_BY, 26 REASSOC_XA_YB, 27 28 // These are patterns matched by the PowerPC to reassociate FMA chains. 29 REASSOC_XY_AMM_BMM, 30 REASSOC_XMM_AMM_BMM, 31 32 // These are multiply-add patterns matched by the AArch64 machine combiner. 33 MULADDW_OP1, 34 MULADDW_OP2, 35 MULSUBW_OP1, 36 MULSUBW_OP2, 37 MULADDWI_OP1, 38 MULSUBWI_OP1, 39 MULADDX_OP1, 40 MULADDX_OP2, 41 MULSUBX_OP1, 42 MULSUBX_OP2, 43 MULADDXI_OP1, 44 MULSUBXI_OP1, 45 // NEON integers vectors 46 MULADDv8i8_OP1, 47 MULADDv8i8_OP2, 48 MULADDv16i8_OP1, 49 MULADDv16i8_OP2, 50 MULADDv4i16_OP1, 51 MULADDv4i16_OP2, 52 MULADDv8i16_OP1, 53 MULADDv8i16_OP2, 54 MULADDv2i32_OP1, 55 MULADDv2i32_OP2, 56 MULADDv4i32_OP1, 57 MULADDv4i32_OP2, 58 59 MULSUBv8i8_OP1, 60 MULSUBv8i8_OP2, 61 MULSUBv16i8_OP1, 62 MULSUBv16i8_OP2, 63 MULSUBv4i16_OP1, 64 MULSUBv4i16_OP2, 65 MULSUBv8i16_OP1, 66 MULSUBv8i16_OP2, 67 MULSUBv2i32_OP1, 68 MULSUBv2i32_OP2, 69 MULSUBv4i32_OP1, 70 MULSUBv4i32_OP2, 71 72 MULADDv4i16_indexed_OP1, 73 MULADDv4i16_indexed_OP2, 74 MULADDv8i16_indexed_OP1, 75 MULADDv8i16_indexed_OP2, 76 MULADDv2i32_indexed_OP1, 77 MULADDv2i32_indexed_OP2, 78 MULADDv4i32_indexed_OP1, 79 MULADDv4i32_indexed_OP2, 80 81 MULSUBv4i16_indexed_OP1, 82 MULSUBv4i16_indexed_OP2, 83 MULSUBv8i16_indexed_OP1, 84 MULSUBv8i16_indexed_OP2, 85 MULSUBv2i32_indexed_OP1, 86 MULSUBv2i32_indexed_OP2, 87 MULSUBv4i32_indexed_OP1, 88 MULSUBv4i32_indexed_OP2, 89 90 // Floating Point 91 FMULADDH_OP1, 92 FMULADDH_OP2, 93 FMULSUBH_OP1, 94 FMULSUBH_OP2, 95 FMULADDS_OP1, 96 FMULADDS_OP2, 97 FMULSUBS_OP1, 98 FMULSUBS_OP2, 99 FMULADDD_OP1, 100 FMULADDD_OP2, 101 FMULSUBD_OP1, 102 FMULSUBD_OP2, 103 FNMULSUBH_OP1, 104 FNMULSUBS_OP1, 105 FNMULSUBD_OP1, 106 FMLAv1i32_indexed_OP1, 107 FMLAv1i32_indexed_OP2, 108 FMLAv1i64_indexed_OP1, 109 FMLAv1i64_indexed_OP2, 110 FMLAv4f16_OP1, 111 FMLAv4f16_OP2, 112 FMLAv8f16_OP1, 113 FMLAv8f16_OP2, 114 FMLAv2f32_OP2, 115 FMLAv2f32_OP1, 116 FMLAv2f64_OP1, 117 FMLAv2f64_OP2, 118 FMLAv4i16_indexed_OP1, 119 FMLAv4i16_indexed_OP2, 120 FMLAv8i16_indexed_OP1, 121 FMLAv8i16_indexed_OP2, 122 FMLAv2i32_indexed_OP1, 123 FMLAv2i32_indexed_OP2, 124 FMLAv2i64_indexed_OP1, 125 FMLAv2i64_indexed_OP2, 126 FMLAv4f32_OP1, 127 FMLAv4f32_OP2, 128 FMLAv4i32_indexed_OP1, 129 FMLAv4i32_indexed_OP2, 130 FMLSv1i32_indexed_OP2, 131 FMLSv1i64_indexed_OP2, 132 FMLSv4f16_OP1, 133 FMLSv4f16_OP2, 134 FMLSv8f16_OP1, 135 FMLSv8f16_OP2, 136 FMLSv2f32_OP1, 137 FMLSv2f32_OP2, 138 FMLSv2f64_OP1, 139 FMLSv2f64_OP2, 140 FMLSv4i16_indexed_OP1, 141 FMLSv4i16_indexed_OP2, 142 FMLSv8i16_indexed_OP1, 143 FMLSv8i16_indexed_OP2, 144 FMLSv2i32_indexed_OP1, 145 FMLSv2i32_indexed_OP2, 146 FMLSv2i64_indexed_OP1, 147 FMLSv2i64_indexed_OP2, 148 FMLSv4f32_OP1, 149 FMLSv4f32_OP2, 150 FMLSv4i32_indexed_OP1, 151 FMLSv4i32_indexed_OP2 152 }; 153 154 } // end namespace llvm 155 156 #endif 157